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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-allmodconfig in repository toolchain/ci/llvm-project.
from c7d8cc48c13 lld-link: Make Options.td formatting more self-consistent. adds 60aadd19cbf [CodeEmitter] Support instruction widths > 64 bits adds a088b95f891 [CodeEmitter] Improve testing for APInt encoding adds 06b309d5274 [ARM] Simplify and update vmla test. NFC adds b6a0faaa0c7 [SLP] limit vectorization of Constant subclasses (PR33958) adds b325c057322 [ARM] Masked loads and stores adds 4f234aaf2c9 [DebugInfo] Don't dereference a dyn_cast<PDBSymbolData> res [...] adds 556fbfec135 [OpenMP] Fix OMPClauseReader::readClause() uninitialized va [...] adds 2b4ace3f299 InterleavedLoadCombine - merge isa<> and dyn_cast<> duplica [...] adds 4e46ea3946c [LoadStoreVectorizer] vectorizeLoadChain - ensure we find a [...] adds a8a4953fdf3 [GlobalISel] findGISelOptimalMemOpLowering - remove dead in [...] adds 07d824a7c39 [PowerPC][NFC] Add a testcase for fdiv expansion. adds c77ad16f8e5 [InstCombine] add icmp tests with extra uses; NFC adds 3daf168fa98 [InstCombine] remove unneeded one-use checks for icmp fold adds f7877dd4b63 Commit missing part of "Split many_tls_keys.cpp into two tests" adds 431141c5cc3 [Attributor] Heap-To-Stack Conversion adds f5d5cd205e7 AMDGPU/GlobalISel: Fix VALU s16 fneg adds 0a6123595f9 AMDGPU/GlobalISel: Select s32->s16 G_[US]ITOFP adds 9f52c1ea583 AMDGPU/GlobalISel: Select S16->S32 fptoint adds 60169ed6130 AMDGPU/GlobalISel: Set type on vgpr live in special arguments adds 01c7f40de3e AMDGPU/GlobalISel: Legalize s1 source G_[SU]ITOFP new 48b158acae6 AMDGPU/GlobalISel: RegBankSelect for kill new bc8de8a8da7 AMDGPU/GlobalISel: Select SMRD loads for more types
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Summary of changes: clang/lib/Serialization/ASTReader.cpp | 4 +- .../test/lsan/TestCases/many_tls_keys_pthread.cpp | 34 +- .../test/lsan/TestCases/many_tls_keys_thread.cpp | 2 +- llvm/include/llvm/Transforms/IPO/Attributor.h | 49 +- llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp | 4 +- llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp | 4 +- llvm/lib/DebugInfo/PDB/UDTLayout.cpp | 2 +- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 5 +- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 4 + llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 3 +- llvm/lib/Target/AMDGPU/SIInstructions.td | 18 +- llvm/lib/Target/AMDGPU/SMInstructions.td | 15 +- llvm/lib/Target/ARM/ARMISelLowering.cpp | 31 + llvm/lib/Target/ARM/ARMInstrMVE.td | 83 + llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp | 20 + llvm/lib/Target/ARM/ARMTargetTransformInfo.h | 3 + llvm/lib/Transforms/IPO/Attributor.cpp | 264 +- .../Transforms/InstCombine/InstCombineCompares.cpp | 7 +- .../Transforms/Vectorize/LoadStoreVectorizer.cpp | 3 +- llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 7 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir | 20 +- .../AMDGPU/GlobalISel/inst-select-fptosi.mir | 132 + .../AMDGPU/GlobalISel/inst-select-fptoui.mir | 83 +- .../GlobalISel/inst-select-load-constant.mir | 1007 +++++ .../AMDGPU/GlobalISel/inst-select-sitofp.mir | 58 +- .../AMDGPU/GlobalISel/inst-select-uitofp.mir | 86 + .../CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir | 4 +- .../CodeGen/AMDGPU/GlobalISel/legalize-uitofp.mir | 4 +- .../AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll | 27 + .../GlobalISel/regbankselect-amdgcn.kill.mir | 68 + .../AMDGPU/GlobalISel/regbankselect-sitofp.mir | 36 + .../AMDGPU/GlobalISel/regbankselect-uitofp.mir | 36 + llvm/test/CodeGen/PowerPC/fdiv.ll | 16 + llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll | 1128 +----- llvm/test/CodeGen/Thumb2/mve-masked-load.ll | 3877 +------------------- llvm/test/CodeGen/Thumb2/mve-masked-store.ll | 2502 +------------ llvm/test/CodeGen/Thumb2/mve-vmaxv.ll | 1 + llvm/test/CodeGen/Thumb2/mve-vmla.ll | 76 +- llvm/test/TableGen/BigEncoder.td | 66 + llvm/test/TableGen/RegisterEncoder.td | 5 +- .../test/Transforms/FunctionAttrs/heap_to_stack.ll | 318 ++ llvm/test/Transforms/InstCombine/icmp.ll | 34 + .../Transforms/LoopVectorize/ARM/mve-maskedldst.ll | 40 + .../SLPVectorizer/X86/consecutive-access.ll | 15 +- llvm/utils/TableGen/CodeEmitterGen.cpp | 188 +- 45 files changed, 3185 insertions(+), 7204 deletions(-) create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptosi.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-constant.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uitofp.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kill.mir create mode 100644 llvm/test/CodeGen/PowerPC/fdiv.ll create mode 100644 llvm/test/TableGen/BigEncoder.td create mode 100644 llvm/test/Transforms/FunctionAttrs/heap_to_stack.ll create mode 100644 llvm/test/Transforms/LoopVectorize/ARM/mve-maskedldst.ll