[Tcwg-commits] [llvm] branch master updated (9f1c2395ce1 -> 0e00ed71fae)

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from 9f1c2395ce1 [ORC] Add LLJIT and LLLazyJIT, and replace OrcLazyJIT in LL [...] new 0e00ed71fae [X86] Add test for SDIV by sign bit (minsigned) value

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Summary of changes: test/CodeGen/X86/combine-sdiv.ll | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+)