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from 698667025ab Handle invariant.group.barrier in BasicAA new 49a37e6bb12 [AMDGPU] Merge M0 initializations new 9d3f4cc120f AMDGPU: Set StackGrowsUp in MCAsmInfo new 38bd5524b01 AMDGPU: Select scratch mubuf offsets when pointer is a constant new a23ad66819b Move value type list from TargetRegisterClass to TargetRegi [...]
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Summary of changes: include/llvm/Target/TargetLowering.h | 3 +- include/llvm/Target/TargetRegisterInfo.h | 45 ++--- lib/CodeGen/SelectionDAG/InstrEmitter.cpp | 3 +- lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 14 +- lib/CodeGen/SelectionDAG/TargetLowering.cpp | 6 +- lib/CodeGen/TargetLoweringBase.cpp | 9 +- lib/CodeGen/TargetRegisterInfo.cpp | 4 +- lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 53 +++++- lib/Target/AMDGPU/BUFInstructions.td | 75 ++++++--- lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp | 1 + lib/Target/AMDGPU/SIFixSGPRCopies.cpp | 185 ++++++++++++++++++++- lib/Target/AMDGPU/SIRegisterInfo.cpp | 3 + lib/Target/AVR/AVRInstrInfo.cpp | 8 +- lib/Target/AVR/AVRRegisterInfo.cpp | 5 +- lib/Target/Mips/MipsOptimizePICCall.cpp | 5 +- lib/Target/Mips/MipsSEInstrInfo.cpp | 16 +- lib/Target/PowerPC/PPCISelLowering.cpp | 4 +- lib/Target/Sparc/SparcISelLowering.cpp | 4 +- lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp | 3 +- lib/Target/X86/X86ISelLowering.cpp | 12 +- lib/Target/X86/X86InstrInfo.cpp | 4 +- test/CodeGen/AMDGPU/addrspacecast.ll | 9 +- test/CodeGen/AMDGPU/merge-m0.mir | 132 +++++++++++++++ test/CodeGen/AMDGPU/mubuf-offset-private.ll | 136 +++++++++++++++ test/CodeGen/AMDGPU/private-access-no-objects.ll | 16 +- test/CodeGen/AMDGPU/spill-m0.ll | 22 +-- 26 files changed, 643 insertions(+), 134 deletions(-) create mode 100644 test/CodeGen/AMDGPU/merge-m0.mir create mode 100644 test/CodeGen/AMDGPU/mubuf-offset-private.ll