[Tcwg-commits] [llvm] branch master updated (8e051316c49 -> f295ff3a3ee)

8 Jul 2019


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unknown user pushed a change to branch master
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from  8e051316c49 Add, and infer, a nofree function attribute
       new  f295ff3a3ee [AMDGPU][MC][DOC] Updated AMD GPU assembler syntax description.
The 1 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails.  The revisions
listed as "adds" were already present in the repository and have only
been added to this reference.
Summary of changes:
 docs/AMDGPU/AMDGPUAsmGFX10.rst                     | 2176 ++++++++++++++++++++
 docs/AMDGPU/AMDGPUAsmGFX7.rst                      |  532 ++---
 docs/AMDGPU/AMDGPUAsmGFX8.rst                      |  641 +++---
 docs/AMDGPU/AMDGPUAsmGFX9.rst                      |  781 +++----
 docs/AMDGPU/gfx10_addr_buf.rst                     |   22 +
 .../{gfx7_ssrc32_1.rst => gfx10_addr_ds.rst}       |    8 +-
 .../{gfx7_ssrc64_2.rst => gfx10_addr_flat.rst}     |    8 +-
 docs/AMDGPU/gfx10_addr_mimg.rst                    |   23 +
 docs/AMDGPU/gfx10_attr.rst                         |   30 +
 ...{gfx7_ssrc64_2.rst => gfx10_base_smem_addr.rst} |    8 +-
 .../{gfx7_ssrc32_1.rst => gfx10_base_smem_buf.rst} |   10 +-
 ...x7_ssrc64_2.rst => gfx10_base_smem_scratch.rst} |    8 +-
 .../AMDGPU/{gfx7_ssrc32_1.rst => gfx10_bimm16.rst} |    9 +-
 .../AMDGPU/{gfx7_ssrc32_1.rst => gfx10_bimm32.rst} |    9 +-
 docs/AMDGPU/gfx10_data_buf_atomic128.rst           |   21 +
 docs/AMDGPU/gfx10_data_buf_atomic32.rst            |   21 +
 docs/AMDGPU/gfx10_data_buf_atomic64.rst            |   21 +
 docs/AMDGPU/gfx10_data_mimg_atomic_cmp.rst         |   27 +
 docs/AMDGPU/gfx10_data_mimg_atomic_reg.rst         |   26 +
 ...gfx7_ssrc32_1.rst => gfx10_data_mimg_store.rst} |   11 +-
 docs/AMDGPU/gfx10_data_mimg_store_d16.rst          |   21 +
 ...7_src32_3.rst => gfx10_data_smem_atomic128.rst} |   14 +-
 docs/AMDGPU/gfx10_data_smem_atomic32.rst           |   21 +
 ...7_ssrc64_0.rst => gfx10_data_smem_atomic64.rst} |   12 +-
 .../{gfx7_ssrc32_1.rst => gfx10_dst_buf_128.rst}   |   10 +-
 .../{gfx7_ssrc32_1.rst => gfx10_dst_buf_32.rst}    |   10 +-
 .../{gfx7_ssrc32_1.rst => gfx10_dst_buf_64.rst}    |   10 +-
 .../{gfx7_ssrc32_1.rst => gfx10_dst_buf_96.rst}    |   10 +-
 docs/AMDGPU/gfx10_dst_buf_lds.rst                  |   21 +
 ...x7_ssrc32_1.rst => gfx10_dst_flat_atomic32.rst} |   10 +-
 ...x7_ssrc64_2.rst => gfx10_dst_flat_atomic64.rst} |   10 +-
 docs/AMDGPU/gfx10_dst_mimg_gather4.rst             |   22 +
 docs/AMDGPU/gfx10_dst_mimg_regular.rst             |   20 +
 docs/AMDGPU/gfx10_dst_mimg_regular_d16.rst         |   22 +
 .../AMDGPU/{gfx7_ssrc32_1.rst => gfx10_fimm16.rst} |    9 +-
 .../AMDGPU/{gfx7_ssrc32_1.rst => gfx10_fimm32.rst} |    9 +-
 docs/AMDGPU/gfx10_hwreg.rst                        |   69 +
 docs/AMDGPU/gfx10_label.rst                        |   30 +
 .../{gfx7_ssrc32_4.rst => gfx10_mad_type_dev.rst}  |   10 +-
 ...ssrc32_1.rst => gfx10_mod_dpp_sdwa_abs_neg.rst} |    9 +-
 .../{gfx7_ssrc32_1.rst => gfx10_mod_sdwa_sext.rst} |    9 +-
 ...fx7_ssrc32_1.rst => gfx10_mod_vop3_abs_neg.rst} |    9 +-
 docs/AMDGPU/{gfx9_msg.rst => gfx10_msg.rst}        |    3 +-
 .../{gfx8_offset_buf.rst => gfx10_offset_buf.rst}  |    4 +-
 docs/AMDGPU/gfx10_offset_smem_buf.rst              |   19 +
 docs/AMDGPU/gfx10_offset_smem_plain.rst            |   22 +
 docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_opt.rst}   |    9 +-
 docs/AMDGPU/gfx10_param.rst                        |   22 +
 docs/AMDGPU/gfx10_perm_smem.rst                    |   24 +
 docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_ret.rst}   |    9 +-
 .../{gfx7_ssrc32_1.rst => gfx10_rsrc_buf.rst}      |   10 +-
 docs/AMDGPU/gfx10_rsrc_mimg.rst                    |   17 +
 docs/AMDGPU/gfx10_saddr_flat_global.rst            |   19 +
 docs/AMDGPU/gfx10_saddr_flat_scratch.rst           |   19 +
 .../{gfx7_ssrc32_1.rst => gfx10_samp_mimg.rst}     |   10 +-
 .../{gfx7_ssrc32_1.rst => gfx10_sdata128_0.rst}    |    8 +-
 .../{gfx7_ssrc32_1.rst => gfx10_sdata32_0.rst}     |    6 +-
 .../{gfx7_ssrc64_2.rst => gfx10_sdata64_0.rst}     |    6 +-
 .../{gfx7_ssrc32_1.rst => gfx10_sdst128_0.rst}     |   10 +-
 .../{gfx7_ssrc32_1.rst => gfx10_sdst256_0.rst}     |   10 +-
 .../{gfx7_ssrc32_1.rst => gfx10_sdst32_0.rst}      |    8 +-
 .../{gfx7_ssrc32_1.rst => gfx10_sdst32_1.rst}      |    8 +-
 .../{gfx7_ssrc32_1.rst => gfx10_sdst32_2.rst}      |    8 +-
 .../{gfx7_ssrc32_1.rst => gfx10_sdst512_0.rst}     |   10 +-
 .../{gfx7_ssrc64_2.rst => gfx10_sdst64_0.rst}      |    8 +-
 .../{gfx7_ssrc64_2.rst => gfx10_sdst64_1.rst}      |    8 +-
 .../AMDGPU/{gfx7_ssrc32_1.rst => gfx10_simm16.rst} |    9 +-
 .../AMDGPU/{gfx7_src32_0.rst => gfx10_src32_0.rst} |    4 +-
 .../AMDGPU/{gfx7_src32_0.rst => gfx10_src32_1.rst} |    4 +-
 .../AMDGPU/{gfx7_src32_0.rst => gfx10_src32_2.rst} |    4 +-
 .../AMDGPU/{gfx7_src32_0.rst => gfx10_src32_3.rst} |    4 +-
 .../AMDGPU/{gfx7_src64_0.rst => gfx10_src64_0.rst} |    4 +-
 docs/AMDGPU/gfx10_src_exp.rst                      |   28 +
 docs/AMDGPU/gfx10_ssrc32_0.rst                     |   17 +
 .../{gfx7_ssrc32_1.rst => gfx10_ssrc32_1.rst}      |    4 +-
 .../{gfx7_ssrc32_1.rst => gfx10_ssrc32_2.rst}      |    4 +-
 .../{gfx7_ssrc32_0.rst => gfx10_ssrc32_3.rst}      |    4 +-
 .../{gfx7_ssrc32_1.rst => gfx10_ssrc32_4.rst}      |    4 +-
 docs/AMDGPU/gfx10_ssrc32_5.rst                     |   17 +
 .../{gfx7_ssrc64_2.rst => gfx10_ssrc64_0.rst}      |    4 +-
 .../{gfx7_ssrc64_2.rst => gfx10_ssrc64_1.rst}      |    4 +-
 docs/AMDGPU/gfx10_tgt.rst                          |   25 +
 .../{gfx7_ssrc32_1.rst => gfx10_type_dev.rst}      |    9 +-
 .../AMDGPU/{gfx7_ssrc32_1.rst => gfx10_uimm16.rst} |    9 +-
 docs/AMDGPU/gfx10_vaddr_flat_global.rst            |   22 +
 docs/AMDGPU/gfx10_vaddr_flat_scratch.rst           |   19 +
 .../AMDGPU/{gfx7_ssrc32_1.rst => gfx10_vcc_32.rst} |   10 +-
 .../{gfx7_ssrc32_1.rst => gfx10_vdata128_0.rst}    |    8 +-
 .../{gfx7_ssrc32_1.rst => gfx10_vdata32_0.rst}     |    6 +-
 .../{gfx7_ssrc64_2.rst => gfx10_vdata64_0.rst}     |    6 +-
 .../{gfx7_ssrc32_1.rst => gfx10_vdata96_0.rst}     |    8 +-
 .../{gfx7_ssrc32_1.rst => gfx10_vdst128_0.rst}     |   10 +-
 .../{gfx7_ssrc32_1.rst => gfx10_vdst32_0.rst}      |    8 +-
 .../{gfx7_ssrc64_2.rst => gfx10_vdst64_0.rst}      |    8 +-
 .../{gfx7_ssrc32_1.rst => gfx10_vdst96_0.rst}      |   10 +-
 .../{gfx7_ssrc32_1.rst => gfx10_vsrc128_0.rst}     |    8 +-
 .../{gfx7_ssrc32_1.rst => gfx10_vsrc32_0.rst}      |    6 +-
 .../{gfx7_ssrc32_1.rst => gfx10_vsrc32_1.rst}      |    6 +-
 .../{gfx7_ssrc64_2.rst => gfx10_vsrc64_0.rst}      |    6 +-
 docs/AMDGPU/gfx10_waitcnt.rst                      |   56 +
 docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_wsdst.rst} |   10 +-
 docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_wssrc.rst} |    6 +-
 docs/AMDGPU/gfx7_offset_buf.rst                    |    2 +-
 docs/AMDGPU/gfx7_src32_0.rst                       |    2 +-
 docs/AMDGPU/gfx7_src32_1.rst                       |    2 +-
 docs/AMDGPU/gfx7_src32_2.rst                       |    2 +-
 docs/AMDGPU/gfx7_src32_3.rst                       |    2 +-
 docs/AMDGPU/{gfx7_src32_0.rst => gfx7_src32_4.rst} |    4 +-
 docs/AMDGPU/{gfx7_src32_0.rst => gfx7_src32_5.rst} |    4 +-
 docs/AMDGPU/{gfx7_src32_0.rst => gfx7_src32_6.rst} |    4 +-
 docs/AMDGPU/gfx7_src64_0.rst                       |    2 +-
 docs/AMDGPU/gfx7_src64_1.rst                       |    2 +-
 docs/AMDGPU/gfx7_src64_2.rst                       |    2 +-
 docs/AMDGPU/gfx7_ssrc32_0.rst                      |    2 +-
 docs/AMDGPU/gfx7_ssrc32_1.rst                      |    2 +-
 docs/AMDGPU/gfx7_ssrc32_3.rst                      |    2 +-
 docs/AMDGPU/gfx7_ssrc32_4.rst                      |    2 +-
 .../{gfx7_ssrc32_4.rst => gfx7_ssrc32_5.rst}       |    2 +-
 .../{gfx7_ssrc32_0.rst => gfx7_ssrc32_6.rst}       |    4 +-
 docs/AMDGPU/gfx7_ssrc64_0.rst                      |    2 +-
 docs/AMDGPU/gfx7_ssrc64_2.rst                      |    2 +-
 .../{gfx7_ssrc32_1.rst => gfx7_vsrc32_1.rst}       |    6 +-
 docs/AMDGPU/gfx8_offset_buf.rst                    |    2 +-
 docs/AMDGPU/gfx8_src32_0.rst                       |    2 +-
 docs/AMDGPU/gfx8_src32_1.rst                       |    2 +-
 docs/AMDGPU/{gfx8_src32_0.rst => gfx8_src32_2.rst} |    4 +-
 docs/AMDGPU/{gfx8_src32_0.rst => gfx8_src32_3.rst} |    4 +-
 docs/AMDGPU/gfx8_src64_0.rst                       |    2 +-
 docs/AMDGPU/gfx8_src64_1.rst                       |    2 +-
 docs/AMDGPU/gfx8_ssrc32_0.rst                      |    2 +-
 docs/AMDGPU/gfx8_ssrc32_4.rst                      |    2 +-
 docs/AMDGPU/gfx8_ssrc64_0.rst                      |    2 +-
 docs/AMDGPU/gfx8_ssrc64_2.rst                      |    2 +-
 .../{gfx7_ssrc32_1.rst => gfx8_vsrc32_1.rst}       |    6 +-
 docs/AMDGPU/gfx9_msg.rst                           |    1 +
 docs/AMDGPU/gfx9_offset_buf.rst                    |    2 +-
 docs/AMDGPU/gfx9_src32_0.rst                       |    2 +-
 docs/AMDGPU/gfx9_src32_1.rst                       |    2 +-
 docs/AMDGPU/{gfx9_src32_0.rst => gfx9_src32_2.rst} |    4 +-
 docs/AMDGPU/{gfx9_src32_0.rst => gfx9_src32_3.rst} |    4 +-
 docs/AMDGPU/gfx9_src64_0.rst                       |    2 +-
 docs/AMDGPU/gfx9_src64_1.rst                       |    2 +-
 docs/AMDGPU/gfx9_ssrc32_0.rst                      |    2 +-
 docs/AMDGPU/gfx9_ssrc32_4.rst                      |    2 +-
 docs/AMDGPU/gfx9_ssrc64_0.rst                      |    2 +-
 docs/AMDGPU/gfx9_ssrc64_2.rst                      |    2 +-
 .../{gfx7_ssrc32_1.rst => gfx9_vsrc32_1.rst}       |    6 +-
 docs/AMDGPUInstructionSyntax.rst                   |    2 +
 docs/AMDGPUModifierSyntax.rst                      |  349 +++-
 docs/AMDGPUOperandSyntax.rst                       |  113 +-
 docs/AMDGPUUsage.rst                               |    7 +-
 151 files changed, 4602 insertions(+), 1393 deletions(-)
 create mode 100644 docs/AMDGPU/AMDGPUAsmGFX10.rst
 create mode 100644 docs/AMDGPU/gfx10_addr_buf.rst
 copy docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_addr_ds.rst} (55%)
 copy docs/AMDGPU/{gfx7_ssrc64_2.rst => gfx10_addr_flat.rst} (54%)
 create mode 100644 docs/AMDGPU/gfx10_addr_mimg.rst
 create mode 100644 docs/AMDGPU/gfx10_attr.rst
 copy docs/AMDGPU/{gfx7_ssrc64_2.rst => gfx10_base_smem_addr.rst} (54%)
 copy docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_base_smem_buf.rst} (52%)
 copy docs/AMDGPU/{gfx7_ssrc64_2.rst => gfx10_base_smem_scratch.rst} (54%)
 copy docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_bimm16.rst} (52%)
 copy docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_bimm32.rst} (52%)
 create mode 100644 docs/AMDGPU/gfx10_data_buf_atomic128.rst
 create mode 100644 docs/AMDGPU/gfx10_data_buf_atomic32.rst
 create mode 100644 docs/AMDGPU/gfx10_data_buf_atomic64.rst
 create mode 100644 docs/AMDGPU/gfx10_data_mimg_atomic_cmp.rst
 create mode 100644 docs/AMDGPU/gfx10_data_mimg_atomic_reg.rst
 copy docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_data_mimg_store.rst} (52%)
 create mode 100644 docs/AMDGPU/gfx10_data_mimg_store_d16.rst
 copy docs/AMDGPU/{gfx7_src32_3.rst => gfx10_data_smem_atomic128.rst} (50%)
 create mode 100644 docs/AMDGPU/gfx10_data_smem_atomic32.rst
 copy docs/AMDGPU/{gfx7_ssrc64_0.rst => gfx10_data_smem_atomic64.rst} (51%)
 copy docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_dst_buf_128.rst} (52%)
 copy docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_dst_buf_32.rst} (52%)
 copy docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_dst_buf_64.rst} (52%)
 copy docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_dst_buf_96.rst} (52%)
 create mode 100644 docs/AMDGPU/gfx10_dst_buf_lds.rst
 copy docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_dst_flat_atomic32.rst} (55%)
 copy docs/AMDGPU/{gfx7_ssrc64_2.rst => gfx10_dst_flat_atomic64.rst} (54%)
 create mode 100644 docs/AMDGPU/gfx10_dst_mimg_gather4.rst
 create mode 100644 docs/AMDGPU/gfx10_dst_mimg_regular.rst
 create mode 100644 docs/AMDGPU/gfx10_dst_mimg_regular_d16.rst
 copy docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_fimm16.rst} (52%)
 copy docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_fimm32.rst} (52%)
 create mode 100644 docs/AMDGPU/gfx10_hwreg.rst
 create mode 100644 docs/AMDGPU/gfx10_label.rst
 copy docs/AMDGPU/{gfx7_ssrc32_4.rst => gfx10_mad_type_dev.rst} (52%)
 copy docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_mod_dpp_sdwa_abs_neg.rst} (52%)
 copy docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_mod_sdwa_sext.rst} (52%)
 copy docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_mod_vop3_abs_neg.rst} (52%)
 copy docs/AMDGPU/{gfx9_msg.rst => gfx10_msg.rst} (97%)
 copy docs/AMDGPU/{gfx8_offset_buf.rst => gfx10_offset_buf.rst} (52%)
 create mode 100644 docs/AMDGPU/gfx10_offset_smem_buf.rst
 create mode 100644 docs/AMDGPU/gfx10_offset_smem_plain.rst
 copy docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_opt.rst} (52%)
 create mode 100644 docs/AMDGPU/gfx10_param.rst
 create mode 100644 docs/AMDGPU/gfx10_perm_smem.rst
 copy docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_ret.rst} (52%)
 copy docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_rsrc_buf.rst} (52%)
 create mode 100644 docs/AMDGPU/gfx10_rsrc_mimg.rst
 create mode 100644 docs/AMDGPU/gfx10_saddr_flat_global.rst
 create mode 100644 docs/AMDGPU/gfx10_saddr_flat_scratch.rst
 copy docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_samp_mimg.rst} (52%)
 copy docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_sdata128_0.rst} (56%)
 copy docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_sdata32_0.rst} (59%)
 copy docs/AMDGPU/{gfx7_ssrc64_2.rst => gfx10_sdata64_0.rst} (58%)
 copy docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_sdst128_0.rst} (52%)
 copy docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_sdst256_0.rst} (52%)
 copy docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_sdst32_0.rst} (55%)
 copy docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_sdst32_1.rst} (55%)
 copy docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_sdst32_2.rst} (55%)
 copy docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_sdst512_0.rst} (52%)
 copy docs/AMDGPU/{gfx7_ssrc64_2.rst => gfx10_sdst64_0.rst} (54%)
 copy docs/AMDGPU/{gfx7_ssrc64_2.rst => gfx10_sdst64_1.rst} (54%)
 copy docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_simm16.rst} (52%)
 copy docs/AMDGPU/{gfx7_src32_0.rst => gfx10_src32_0.rst} (59%)
 copy docs/AMDGPU/{gfx7_src32_0.rst => gfx10_src32_1.rst} (53%)
 copy docs/AMDGPU/{gfx7_src32_0.rst => gfx10_src32_2.rst} (56%)
 copy docs/AMDGPU/{gfx7_src32_0.rst => gfx10_src32_3.rst} (55%)
 copy docs/AMDGPU/{gfx7_src64_0.rst => gfx10_src64_0.rst} (58%)
 create mode 100644 docs/AMDGPU/gfx10_src_exp.rst
 create mode 100644 docs/AMDGPU/gfx10_ssrc32_0.rst
 copy docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_ssrc32_1.rst} (59%)
 copy docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_ssrc32_2.rst} (59%)
 copy docs/AMDGPU/{gfx7_ssrc32_0.rst => gfx10_ssrc32_3.rst} (52%)
 copy docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_ssrc32_4.rst} (59%)
 create mode 100644 docs/AMDGPU/gfx10_ssrc32_5.rst
 copy docs/AMDGPU/{gfx7_ssrc64_2.rst => gfx10_ssrc64_0.rst} (51%)
 copy docs/AMDGPU/{gfx7_ssrc64_2.rst => gfx10_ssrc64_1.rst} (58%)
 create mode 100644 docs/AMDGPU/gfx10_tgt.rst
 copy docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_type_dev.rst} (52%)
 copy docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_uimm16.rst} (52%)
 create mode 100644 docs/AMDGPU/gfx10_vaddr_flat_global.rst
 create mode 100644 docs/AMDGPU/gfx10_vaddr_flat_scratch.rst
 copy docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_vcc_32.rst} (52%)
 copy docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_vdata128_0.rst} (56%)
 copy docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_vdata32_0.rst} (59%)
 copy docs/AMDGPU/{gfx7_ssrc64_2.rst => gfx10_vdata64_0.rst} (58%)
 copy docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_vdata96_0.rst} (56%)
 copy docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_vdst128_0.rst} (52%)
 copy docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_vdst32_0.rst} (55%)
 copy docs/AMDGPU/{gfx7_ssrc64_2.rst => gfx10_vdst64_0.rst} (54%)
 copy docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_vdst96_0.rst} (52%)
 copy docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_vsrc128_0.rst} (56%)
 copy docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_vsrc32_0.rst} (59%)
 copy docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_vsrc32_1.rst} (59%)
 copy docs/AMDGPU/{gfx7_ssrc64_2.rst => gfx10_vsrc64_0.rst} (58%)
 create mode 100644 docs/AMDGPU/gfx10_waitcnt.rst
 copy docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_wsdst.rst} (52%)
 copy docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx10_wssrc.rst} (57%)
 copy docs/AMDGPU/{gfx7_src32_0.rst => gfx7_src32_4.rst} (72%)
 copy docs/AMDGPU/{gfx7_src32_0.rst => gfx7_src32_5.rst} (72%)
 copy docs/AMDGPU/{gfx7_src32_0.rst => gfx7_src32_6.rst} (73%)
 copy docs/AMDGPU/{gfx7_ssrc32_4.rst => gfx7_ssrc32_5.rst} (95%)
 copy docs/AMDGPU/{gfx7_ssrc32_0.rst => gfx7_ssrc32_6.rst} (67%)
 copy docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx7_vsrc32_1.rst} (59%)
 copy docs/AMDGPU/{gfx8_src32_0.rst => gfx8_src32_2.rst} (73%)
 copy docs/AMDGPU/{gfx8_src32_0.rst => gfx8_src32_3.rst} (77%)
 copy docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx8_vsrc32_1.rst} (59%)
 copy docs/AMDGPU/{gfx9_src32_0.rst => gfx9_src32_2.rst} (73%)
 copy docs/AMDGPU/{gfx9_src32_0.rst => gfx9_src32_3.rst} (77%)
 copy docs/AMDGPU/{gfx7_ssrc32_1.rst => gfx9_vsrc32_1.rst} (59%)
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[Tcwg-commits] [llvm] branch master updated (8e051316c49 -> f295ff3a3ee)