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from f633076fd1a [AArch64] Clean up code (NFC) new 72d58f8a940 AMDGPU/GlobalISel: Remove default register mapping new 679df750a90 [X86][SSE] Regenerate float to/from i8/i16 vector tests new 9fcecef7269 AMDGPU/GlobalISel: Define instruction mapping for G_OR new 05580dd9e5a AMDGPU/GlobalISel: Define instruction mapping for @llvm.amd [...]
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Summary of changes: lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 83 +++++-- lib/Target/AMDGPU/AMDGPURegisterBankInfo.h | 3 + ...icmp.mir => regbankselect-amdgcn.cvt.pkrtz.mir} | 37 ++- ...regbankselect-icmp.mir => regbankselect-or.mir} | 41 ++-- test/CodeGen/X86/vec_cast2.ll | 258 +++++++++++++++++++-- 5 files changed, 347 insertions(+), 75 deletions(-) copy test/CodeGen/AMDGPU/GlobalISel/{regbankselect-icmp.mir => regbankselect-amdgc [...] copy test/CodeGen/AMDGPU/GlobalISel/{regbankselect-icmp.mir => regbankselect-or.mi [...]