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from 98ce5f9f8c7 [X86] getFauxShuffle - add DemandedElts as a filter new dbfb2af6216 [ARM] Tighten restrictions on use of SP in v8.1-M CSEL. new c27a34eed4e [ARM] Make coprocessor number restrictions consistent. new c82b7efc96f [ARM] Fix handling of zero offsets in LOB instructions. new 3a2501e0a00 [ARM] Fix bogus assertions in copyPhysReg v8.1-M cases.
The 4 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.
Summary of changes: lib/Target/ARM/ARMBaseInstrInfo.cpp | 8 +- lib/Target/ARM/ARMBaseInstrInfo.h | 22 + lib/Target/ARM/ARMInstrThumb2.td | 25 +- lib/Target/ARM/ARMRegisterInfo.td | 12 +- lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 4 +- lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 39 +- test/MC/ARM/coprocessors.s | 74 ++ test/MC/ARM/diagnostics.s | 24 +- test/MC/ARM/mve-misc.s | 4 + test/MC/ARM/thumb2-diagnostics.s | 4 +- test/MC/ARM/thumbv8.1m.s | 20 + test/MC/ARM/v8_IT_manual.s | 928 ++++++++++++------------ test/MC/Disassembler/ARM/coprocessors-arm.txt | 68 ++ test/MC/Disassembler/ARM/coprocessors-thumb.txt | 70 ++ test/MC/Disassembler/ARM/mve-misc.txt | 46 +- test/MC/Disassembler/ARM/mve-qdest-rsrc.txt | 8 +- test/MC/Disassembler/ARM/mve-scalar-shift.txt | 2 +- test/MC/Disassembler/ARM/thumb2-v8.1m.txt | 18 + test/MC/Disassembler/ARM/thumbv8.1m.s | 16 +- 19 files changed, 849 insertions(+), 543 deletions(-) create mode 100644 test/MC/ARM/coprocessors.s create mode 100644 test/MC/Disassembler/ARM/coprocessors-arm.txt create mode 100644 test/MC/Disassembler/ARM/coprocessors-thumb.txt