[Tcwg-commits] [toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-next-allnoconfig updated (e403a898b5 -> 4001d90dde)

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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-next-allnoconfig in repository toolchain/ci/binutils-gdb.

from e403a898b5 Automatic date update in version.in adds 1368b914e9 sim: testsuite: flatten tree adds eb6e6af8c1 PR26002 undefined symbol VER_NDX_GLOBAL vs. VER_NDX_LOCAL adds ad92f33d38 Tidy inflateEnd calls adds 68b007788a ld/x86: Add -z report-relative-reloc adds 75a933f399 ld/elf/x86: Don't compare IFUNC address in the shared object adds 514fca98df Automatic date update in version.in adds edf0f284b1 PR binutils/23460: Increase the max number of open files to 20 adds d46153313b Automatic date update in version.in adds 25294ff049 gold: Remove the circular IFUNC dependency in ifuncmain6pie adds 994b251328 ld/elf: Ignore section symbols when matching linkonce with comdat adds 44365e88c0 PR27198, segv in S_IS_WEAK adds cecb191290 gdb: const-ify unpack_* functions in remote.c adds e3b2741b16 gdb: const-ify remote_target::add_current_inferior_and_threa [...] adds b5c8f22d28 gdb: move remote_target::start_remote variable to narrower scope adds aa2838ccc5 gdb: const-ify hostio methods parameter in remote.c adds d3d7d1ba3b [gdb/tdep] Handle si_addr_bnd in compat_siginfo_from_siginfo adds 326adec374 PR26378, sections initialised only by linker scripts are alw [...] adds 6a9ad81c44 gdb/riscv: use a single regset supply function for riscv fbs [...] adds 705989f19a as: Automatically enable DWARF5 support adds 02baa13385 gdb/testsuite: remove actual addresses from some test names adds 4cfcd3b333 sim: common: modernize gennltvals.sh adds 5e25901fcc sim: common: delete configure & Makefile adds f89f33e57c sim: common: simplify version script adds f0c1efa53d Automatic date update in version.in adds 85e963f185 ld: Just xfail riscv little endian targets for compressed1d.d test. adds 0e7620dcdc sim: bfin: delete accidental ADI copyright adds a75a6a4164 [GOLD] powerpc assertion failure adds 30845f113a PowerPC use_local_plt adds 0c4e2c6c88 [gdb/testsuite] Fix gdb.arch/i386-mpx.exp with -m32 adds 1485212328 [gdb/testsuite] Fix gdb.base/step-over-syscall.exp with -m32 adds c98de297b3 libctf, ld: fix data symbol test with newer GCC adds e05a3e5a49 libctf: lookup_by_name: do not return success for nonexisten [...] adds 26503e2f5e libctf, create: fix ctf_type_add of structs with unnamed members adds ccbe4c82d5 Use gdb::array_view for setting value bytes in trad-frame adds c65ca138c4 sim: ppc: update version script usage adds bdec2917b1 Convert some frame functions to use gdb::array_view. adds a9a87d3525 trad-frame cleanups adds 1c3b85ad28 use DISABLE_COPY_AND_ASSIGN in switch_thru_all_uis adds 11321a0505 Automatic date update in version.in adds 8bd10d6b16 PowerPC64 synthetic symbols adds 4bd7c90276 PowerPC: Don't generate unused section symbols adds 037e8112b9 [gdb/server] Don't overwrite fs/gs_base with -m32 adds 6f52fdf404 Fix a few stap parser issues and add a new test for probe ex [...] adds 1402665c8f [gdb/testsuite] Skip gdb.rust/*.exp for target board unix/-m32 adds 7c794afd54 [gdb/testsuite] Fix gdb.python/py-format-string.exp with -m32 adds 6571ffc620 gdb/testsuite: add links for handled control sequences in li [...] adds c3e96aa78f gdb/testsuite: rename _cur_x/_cur_y to _cur_col/_cur_row in [...] adds 3f0781f389 Automatic date update in version.in adds a6c11cbb14 gdb/remote.c: address conflicting enum and method name adds 6bd434d6ca gdb: make some variables static adds 17e593e966 gdb/dwarf: add some logging in dwarf2/read.c adds de53369b2e gdb/dwarf: add assertion in maybe_queue_comp_unit adds f9e9ba90b3 gdb/testsuite: use multi_line in gdb.base/skip.exp adds d4dd4fca16 gdb: change debug_bfd_cache to bool adds c78eec4424 mips XPASS pr26936 adds 498ff0328f PR27218, memory access violation in dwarf2dbg.c adds be07043ea8 PR27221, 058430b4a1 warnings while assembling the Linux kernel adds 7cb6d92a3f gdb: convert arm to new-style debug macros adds 325d39e4e0 Add Python support for hardware breakpoints adds a72d0f3d69 gdb/doc: reorder and group sections relating to aliases adds 730af66356 gdb/testsuite: improve logging in lib/tuiterm.exp adds 439706e6a9 gdb: use interruptible_select when connecting to a remote adds 1e15fcac94 gdb: convert bfd-cache to new-style debug macros adds d3abc0cee0 gdb: remove unused f77_array_offset_tbl from f-valprint.c adds a59902a7c1 gdb: convert auto-load to new-style debug macros adds d5d24e12f9 Fix build errors for armhf adds cd211c75cb Handle additional connection error adds e534c7e8c4 Automatic date update in version.in adds c651f0a614 MAINTAINERS: Update my e-mail address adds cc4bc93e52 gdb/doc: down case contents of @var adds fe461d2f70 gdb/doc: move @menu to the end of the node adds 5b7d941b90 gdb: add owner-related methods to struct type adds 3062502019 gdb: remove TYPE_OBJFILE_OWNED macro adds 344e9841d9 gdb: remove TYPE_OBJFILE macro adds baf2b57f18 gdb: move set remote commands to remote.c adds cda09ec9f9 gdb: move remote_debug to remote.{h,c} adds 02349803fc gdb: change remote_debug to bool adds 2189c31265 gdb: add remote_debug_printf adds d8c4766d31 gdb/doc: don't rely on @menu item within the docs adds e7b430724d gdb: don't print escape characters when a style is disabled adds 9d2d8a16e1 gdb: add new version style adds 0ac85db529 gdb/testsuite: eliminate gdb_suppress_tests mechanism adds 705646c074 Fix expected output of gdb.base/line65535.exp with dwarf-5 adds e753591581 Automatic date update in version.in adds 1af4c9c420 Disable bracketed paste mode in GDB tests adds ef45cb65a7 Use readline's variant of Windows patch adds d3ee35dbf7 Improve gdb_tilde_expand logic. adds dd5ca05f47 gdb: fix regression in copy_type_recursive adds c99d72de18 Automatic date update in version.in adds 9f7f6cb8d2 Remove call to reset from compile_to_object adds 18454c151f DWARF-5: Fix parsing DWARF-5 line number tables adds 3637a558a5 Use std::vector for "registers_used" in compile feature adds b10bae1875 Avoid crash when "compile" expression uses cooked register adds 68fcee4fa7 PR27228, .reloc wrong symbol emitted for undefined local symbol adds 9b351c9bc9 Minor updates to the 'how to make a release' document adds eea133e655 gas: Add a testcase for PR gas/27228 adds 940d0202fd DWARF-5: Ignore empty range in DWARF-5 line number tables adds 123b18bf62 Automatic date update in version.in adds b8df69003d Update linker scripts with the names of new DWARF-5 debug sections. adds 04de9f3e31 gdb/doc: move @menu blocks to the end of their enclosing @node adds 9e42b97628 Add some more DWARF-5 sections adds acd6125f01 Add test case for symbol menu for local enumerators adds 191849105b Specially handle array contexts in Ada expression resolution adds a625a8c9eb Fix fixed-point regression with recent GCC adds f3bdc2dbb9 gdb/docs: add parentheses in Python examples using print adds 9f6c202e57 [gdb/symtab] Handle DW_AT_ranges with DW_FORM_sec_off in par [...] adds 01a01e0ab3 Automatic date update in version.in adds d0021af39c [gdb/testsuite] Fix gdb.opt/solib-intra-step.exp with -m32 adds 4ca40594f9 [gdb/testsuite] Fix gdb.threads/killed-outside.exp with -m32 adds d56834cbfb arc: Log "pc" value in "arc_skip_prologue" adds e37709f090 Fix thinko in objcopy's memory freeing code. adds ac3571d941 Fix the date for the last entry in gdb/ChangeLog adds d0cc52bdf2 gdb: Add default reggroups for ARC adds 4287950e54 pr27228 testcase adds 9886ff0319 gas byte test adds a45ef9a30b gas testsuite tidy adds 1c9c9b9b55 PR27226, ld.bfd contains huge .rodata section adds c3ffb8f340 Segmentation fault i386-gen adds 4cb1265b3f bfd: add elfcore_write_file_note adds 4ef367bffd Use debug_prefixed_printf_cond in windows-nat.c adds 1f583bc2fc nios2: Don't disable relaxation with --gdwarf-N adds c22788d614 Automatic date update in version.in adds 2eda57ef61 ld: Fix a typo in testsuite/ld-x86-64/bnd-plt-1.d adds 67965ba289 Simplify the code at the end of objcopy's main() function. adds f04ce15e83 ld: depend on libctf adds bb3c2d4d94 Remove extra space after @pxref in gdb.texinfo adds 807f647cac GDB: aarch64: Add ability to displaced step over a BR/BLR in [...] adds 59b59f08f6 Avoid use after free with logging and debug redirect. adds 07b8b9e7c5 Automatic date update in version.in adds 22efa3d307 [gdb/testsuite] Fix ERROR in gdb.dwarf2/dw2-out-of-range-end [...] adds 2f985dd1ac [gdb/testsuite] Fix gdb.ada/out_of_line_in_inlined.exp with [...] adds def97fb945 PR27259, SHF_LINK_ORDER self-link adds 2a7f6487d0 [gdb/breakpoints] Fix longjmp master breakpoint with separat [...] adds 24cf63899b gdb: update comment for execute_command_to_string adds 47918cca26 gdb/testsuite: unset XDG_CONFIG_HOME adds 0318cca493 gold: Skip address size and segment selector for DWARF5 adds a7ad3cb1ff Fix binutils tools so that they can cope with the special /d [...] adds 53e556e5b4 ld: Add a test for PR ld/27259 adds cc3edc5274 Improve windres's handling of pathnames containing special c [...] adds 6ac373717c gdb: rename type::{arch,objfile} -> type::{arch_owner,objfil [...] adds 8ee511afd8 gdb: rename get_type_arch to type::arch adds c47b145e1a [gdb/testsuite] Fix g0 search in gdb.arch/i386-sse-stack-align.exp adds cdeba395cf [gdb/testsuite] Fix gdb.arch/i386-gnu-cfi.exp adds f237f998d1 gdb/tui: remove special handling of locator/status window adds 0f93c3a25b gdb: remove unneeded switch_to_thread from thr_try_catch_cmd adds 986dbd541a Automatic date update in version.in adds c4566785ac PR27271, c6x-uclinux-ld segfaults linking ld-uClibc-1.0.37.so adds 620ec3caae [gdb/testsuite] Fix gdb.opt/solib-intra-step.exp with -m32 a [...] adds ebde6f2ddc [gdb/breakpoint] Fix stepping past non-stmt line-table entries adds 6efcd6f329 Automatic date update in version.in adds 008a02e36d sim: readd myself as a maintainer adds 481fac96bd sim: common: sort nltvals.def adds f4dd74915b sim: hw: replace fgets with getline adds 88f68ee277 sim: m68hc11: stop making hardware conditional adds 18d4b488f4 sim: profile: fix bucketing with 64-bit targets adds d4e3adda12 sim: watchpoints: change sizeof_pc to sizeof(sim_cia) adds ee64caae5b sim: m68hc11: include stdlib.h for prototypes adds fb8d4e59af sim: m68hc11: tweak printf-style funcs adds b9e016f517 sim: m68hc11: localize a few functions adds 683b8d961e sim: m68hc11: fix printf size warnings adds ca51543cf5 Automatic date update in version.in adds 9a7ba4aa0e sim: common: change gennltvals helper to Python adds 3c811346e9 sim: moxie: cleanup build warnings adds 44b30b7f0e sim: v850: fix handling of SYS_times adds 5f05936d9b sim: v850: cleanup build warnings adds 5bc4f5ca15 sim: cgen-accfp: Fix pointer sign warnings adds ba2f0de216 sim: bpf/or1k: fix CGEN_TRACE_EXTRACT name adds bccec180ce sim: bpf: fix mainloop extract call adds 6451541244 sim: cgen-trace: tweak printf call adds 4ebf566ea5 Automatic date update in version.in adds 7bba67ec7c PR27283 gas for alpha fails to build with gcc 11 adds 49daa38f31 Re: ld: Add a test for PR ld/27259 adds a5f92c6756 ldgram.y low_level_library_NAME_list adds 82a1fd3a49 gdb: unify parts of the Linux and FreeBSD core dumping code adds 40726f16a8 ld script expression parsing adds fb6c220ebd ld --defsym adds 72a51a0603 Small updates to the 'how to make a release' document follow [...] adds 34c10233cd Wrong operand for SADDR (rl78) adds c39c86378f [gdb/testsuite] Fix gdb.dwarf2/fission-reread.exp with .gdb_index adds 1f568f9a0d Add Genode target support adds 82e3e87da4 Automatic date update in version.in adds 2bd3e4b8d2 [gdb/symtab] Fix assert in write_one_signatured_type adds 9918bff7cf PR27311, ld.bfd (symbol from plugin): undefined reference adds 5424d7ed94 readelf: Add 'R' and 'D' to "Key to Flags:" adds a0c1eeba9b gdb/dwarf: change read_loclist_index complaints into errors adds 5e4d9bbc4b gdb/dwarf: fix bound check in read_rnglist_index adds 05787bad36 gdb/dwarf: add missing bound check to read_loclist_index adds 0c800c6ebc gdb/dwarf: remove unnecessary check in read_{rng,loc}list_index adds b1829e1bf2 gdb/dwarf: few fixes for handling DW_FORM_{rng,loc}listx adds a1c4010369 gdb/dwarf: read correct rnglist/loclist header in read_{rng, [...] adds 962effa790 gdb/testsuite: add .debug_rnglists tests adds 6b0933da34 gdb/testsuite: DWARF assembler: add context parameters to _location adds ecfda20dcc gdb/testsuite: add .debug_loclists tests adds 2b0c7f41d1 gdb/dwarf: split dwarf2_cu::ranges_base in two adds e57933dc9c gdb/dwarf: make read_{loc,rng}list_index return sect_offset adds 9307efbe9e gdb/testsuite: add test for .debug_{rng,loc}lists section wi [...] adds e0bd9202fb gdb/testsuite: use proc_with_prefix in gdb.base/scope.exp adds 2e3773ff54 Inferior without argument prints detail of current inferior. adds 0e33957abf Automatic date update in version.in adds 2ab76a181f Fix attaching in non-stop mode (PR gdb/27055) adds 621cc31071 Fix "target extended-remote" + "maint set target-non-stop" + [...] adds 92234eb192 Testcase for attaching in non-stop mode adds b0083dd72f Fix a couple vStopped pending ack bugs adds 7e9cf1fe36 gdbserver: spurious SIGTRAP w/ detach while step-over in progress adds d758e62c0e Factor out after-stop event handling code from stop_all_threads adds 9147506842 prepare_for_detach: don't release scoped_restore at the end adds 8ff531399b prepare_for_detach and ongoing displaced stepping adds e87f0fe823 detach and breakpoint removal adds ac7d717c1e detach with in-line step over in progress adds 408f66864a detach in all-stop with threads running adds a71501e25f Testcase for detaching while stepping over breakpoint adds 6955136728 PR27311 again, ld.bfd (symbol from plugin): undefined reference adds 95b91a043a pr27270 and pr27284, ar segfaults and wrong file mode adds f01fb44c06 Re: PR27311, ld.bfd (symbol from plugin): undefined reference adds 61ecbbae8e IBM Z: Add missing vector formats to .insn docs adds 72d383bb08 gdb: infrun: move stop_soon variable to inner scoped in hand [...] adds e3714e037b Automatic date update in version.in adds 7d409ac001 PR27311, (symbol from plugin): undefined reference, hidden sym adds 24075dcc85 RISC-V: Removed the v0.93 bitmanip ZBA/ZBB/ZBC instructions. adds 37707bd822 ld: Restore PR ld/15146 tests adds 1a2f1b54a5 x86-64: Provide more info when failed to convert GOTPCREL adds 35a01a0454 libctf, ld: fix symtypetab and var section population under ld -r adds 78f28b89e8 libctf: rip out dead code handling typedefs with no name adds caa170493e libctf: prohibit nameless ints, floats, typedefs and forwards adds 5dacd11ddc libctf: fix uninitialized variable in symbol serialization e [...] adds ee87f50b8d libctf: always name nameless types "", never NULL adds 6b36ddeb1e gdb: make async event handlers clear themselves adds baa8575b29 gdb: make remote target clear its handler in remote_target::wait adds 85d3ad8e0b gdb: make record-btrace clear event handler in wait adds fdbc5215e7 gdb: make record-full clear async handler in wait adds 3eccb1c8bf gdb: Use correct feature in tdesc-regs for ARC adds 6ff267e186 gdb: make target_is_non_stop_p return bool adds a9ab6e2ea0 Automatic date update in version.in adds b9249c461c sim: riscv: new port adds 04b4939b03 gdb: riscv: enable sim integration adds c180f095f3 PR27345, binutils/arsup.c: lstat() not available on all targets adds cb4ff67af3 RISC-V: PR27348, Remove obsolete Xcustom support. adds 5f40035fb8 RISC-V: PR27348, Remove the obsolete OP_*CUSTOM_IMM. adds 554c30abef ld testsuite on x86_64 with --enable-shared adds 887854bae4 Fix typos in comments added in PR 27252 fix adds fc9a13fbdd [gdb/symtab] Fix indentation in create_cus_from_debug_names_list adds d3b54e63f4 [gdb/symtab] Fix duplicate CUs in create_cus_from_debug_names_list adds ae71049661 [gdb/exp] Fix assert when adding ptr to imaginary unit adds a22ec6e8a4 [gdb/testsuite] Add KFAILs for PR symtab/24549 adds e37d88e5e5 Remove Richard Henderson as the Alpha maintainer adds 1b30f42106 Extract symbol-writing function from parsers adds bdfea17ea9 Return unique_ptr from language_defn::get_compile_context adds 0e857c8288 [gdb/breakpoints] Fix segfault for catch syscall -1 adds e77b0004dd [gdb/symtab] Handle DW_TAG_type_unit in process_psymtab_comp_unit adds 7c6944ab9b [gdb/breakpoints] Handle glibc with debuginfo in create_exce [...] adds 0110ec824e gdb: symmisc.c: remove std_{in,out,err} adds 9c9d63b15a gnulib: update to 776af40e0 adds 51a2525281 PR27349, ar breaks symlinks adds 2c6f2aa664 Automatic date update in version.in adds aa09469fc6 sim: drop use of bfd/configure.host adds 7a36eeea26 sim: common: switch AC_CONFIG_HEADERS adds 8e25beb4af sim: igen: drop libiberty linkage adds cd89c53f6d sim: add ChangeLog entries for last commits adds 4c0d76b9c4 sim: watchpoints: use common sim_pc_get adds 7a9bd3b4e2 sim: erc32/m32c/rl78: add sim_memory_map stub for gdb adds c0e5674584 [gdb/testsuite] Fix gdb.tui/tui-layout-asm.exp with -m32 adds cca043e071 Automatic date update in version.in adds de8d420310 asan: unwind-ia64.c: stack buffer overflow adds 83962f8340 Also compare frame_id_is_next in frapy_richcompare adds 5fc2d6aa06 Refresh regs window in display_registers_from adds 3537bc23d9 Don't fill regs window with a negative number of spaces adds 4cf28e918a Don't draw register sub windows outside the visible area adds 38a143aa8c ld: Remove x86 ISA level run-time tests adds d6f2700b48 Automatic date update in version.in new 5fb9763991 gdb/testsuite: fix implementation of delete line in tuiterm.exp new cd074e0415 gdb/tui: fix issue with handling the return character new 0309f9549d sim/rx: define sim_memory_map new 93a01471f3 sim/rx: fix an issue where we try to modify a const string new 1c3e93a41f sim/rx: fill in missing 'void' for empty argument lists new 73d4725f21 sim/rx: mark some functions as static new 4b42639636 sim/rx: delete an unused function new b9fe995797 sim/rx: provide a format string for printf new 783a7b12d3 sim/rx: move some variable declarations to the start of the block new ae41b4ce9f sim/rx: use PRIx64 in printf format string new fab2b376e3 sim/rx: add some missing includes new da9ecd6085 sim/rx: avoid pointer arithmetic on void * pointers new 6bf99988c6 sim/rx: enable build with warnings new 2708dbbd58 gdb/python: reformat an error string new a53a265752 gdb/tui: restore delete of window objects new 1cf2399651 gdb/tui: don't add windows to global list from tui_layout:wi [...] new e0c23e11da gdb/python: don't allow the user to delete window title attributes new 29db1eb339 gdb: return true in TuiWindow.is_valid only if TUI is enabled new 9b3e4b5d74 gdb: Do not interrupt atomic sequences for ARC new 4001d90dde [gdb/testsuite] Use DW_FORM_ref_addr in gdb.dwarf2/enqueued- [...]

The 20 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.

Summary of changes: ChangeLog | 5 + Makefile.def | 1 + Makefile.in | 1 + bfd/ChangeLog | 144 + bfd/compress.c | 3 +- bfd/config.bfd | 6 +- bfd/dwarf2.c | 5 +- bfd/elf-bfd.h | 2 + bfd/elf-linker-x86.h | 3 + bfd/elf.c | 8 + bfd/elf32-ft32.c | 3 +- bfd/elf32-i386.c | 36 + bfd/elf32-ppc.c | 55 +- bfd/elf32-rl78.c | 2 +- bfd/elf64-ppc.c | 83 +- bfd/elf64-x86-64.c | 46 +- bfd/elflink.c | 36 +- bfd/elfxx-riscv.c | 2 +- bfd/elfxx-x86.c | 50 +- bfd/elfxx-x86.h | 4 + bfd/version.h | 2 +- binutils/ChangeLog | 87 + binutils/MAINTAINERS | 3 +- binutils/README-how-to-make-a-release | 64 +- binutils/ar.c | 13 +- binutils/arsup.c | 46 +- binutils/bucomm.c | 15 + binutils/elfedit.c | 14 + binutils/objcopy.c | 36 +- binutils/readelf.c | 16 +- binutils/rename.c | 17 +- binutils/testsuite/binutils-all/retain1a.d | 2 + binutils/unwind-ia64.c | 4 + binutils/windres.c | 31 +- gas/ChangeLog | 130 + gas/config/tc-alpha.c | 2 +- gas/config/tc-i386.c | 3 + gas/config/tc-nios2.c | 4 - gas/config/tc-riscv.c | 10 - gas/configure.tgt | 4 +- gas/doc/c-s390.texi | 50 +- gas/dwarf2dbg.c | 33 +- gas/testsuite/gas/all/byte.d | 4 - gas/testsuite/gas/all/byte.l | 3 - gas/testsuite/gas/all/byte.s | 2 - gas/testsuite/gas/all/gas.exp | 5 - gas/testsuite/gas/all/local-label-overflow.d | 5 +- gas/testsuite/gas/all/none.d | 2 +- gas/testsuite/gas/all/sleb128-2.d | 2 +- gas/testsuite/gas/all/sleb128-4.d | 3 +- gas/testsuite/gas/all/sleb128-5.d | 2 +- gas/testsuite/gas/all/sleb128-7.d | 2 +- gas/testsuite/gas/all/sleb128-9.d | 2 +- gas/testsuite/gas/all/string.d | 2 +- gas/testsuite/gas/elf/bignums.d | 2 +- gas/testsuite/gas/elf/dwarf-5-file0.d | 2 +- gas/testsuite/gas/elf/dwarf2-20.d | 4 - gas/testsuite/gas/elf/elf.exp | 6 +- gas/testsuite/gas/elf/group0c.d | 2 +- gas/testsuite/gas/elf/group1a.d | 2 +- gas/testsuite/gas/elf/missing-build-notes.d | 2 +- gas/testsuite/gas/elf/pr27228.d | 10 + gas/testsuite/gas/elf/pr27228.s | 5 + gas/testsuite/gas/elf/section-symbol-redef.d | 2 +- gas/testsuite/gas/elf/section0.d | 2 +- gas/testsuite/gas/elf/section1.d | 2 +- gas/testsuite/gas/elf/section10.d | 2 +- gas/testsuite/gas/elf/section11.d | 4 +- gas/testsuite/gas/elf/section15.d | 2 +- gas/testsuite/gas/elf/section4.d | 2 +- gas/testsuite/gas/elf/section6.d | 2 +- gas/testsuite/gas/elf/section7.d | 2 +- gas/testsuite/gas/elf/symtab.d | 4 +- gas/testsuite/gas/elf/symtab.s | 2 +- gas/testsuite/gas/elf/warn-2.s | 7 - gas/testsuite/gas/i386/i386.exp | 1 + gas/testsuite/gas/i386/pr27198.d | 2 + gas/testsuite/gas/i386/pr27198.err | 5 + gas/testsuite/gas/i386/pr27198.s | 1 + gas/testsuite/gas/lns/lns-diag-1.l | 2 - gas/testsuite/gas/m68hc11/indexed12.d | 4 - gas/testsuite/gas/macros/irp.d | 2 +- gas/testsuite/gas/macros/repeat.d | 2 +- gas/testsuite/gas/macros/rept.d | 2 +- gas/testsuite/gas/macros/test2.d | 2 +- gas/testsuite/gas/macros/test3.d | 1 - gas/testsuite/gas/macros/vararg.d | 2 +- gas/testsuite/gas/nios2/relax.d | 25 + gas/testsuite/gas/nios2/relax.s | 5 + gas/testsuite/gas/ppc/power4.d | 1 - gas/testsuite/gas/ppc/test1elf32.d | 1 - gas/testsuite/gas/ppc/test1elf64.d | 1 - gas/testsuite/gas/riscv/bitmanip-insns-32.d | 37 - gas/testsuite/gas/riscv/bitmanip-insns-64.d | 55 - gas/testsuite/gas/riscv/bitmanip-insns.s | 58 - gas/write.c | 4 +- gdb/ChangeLog | 941 ++ gdb/MAINTAINERS | 4 +- gdb/Makefile.in | 3 + gdb/NEWS | 11 + gdb/aarch64-linux-tdep.c | 16 +- gdb/aarch64-tdep.c | 73 +- gdb/ada-lang.c | 31 +- gdb/ada-valprint.c | 2 +- gdb/alpha-mdebug-tdep.c | 4 +- gdb/alpha-tdep.c | 8 +- gdb/amd64-fbsd-tdep.c | 2 +- gdb/amd64-linux-tdep.c | 4 +- gdb/amd64-obsd-tdep.c | 2 +- gdb/arc-linux-tdep.c | 81 +- gdb/arc-tdep.c | 24 +- gdb/arch/aarch64-insn.h | 9 + gdb/arm-linux-tdep.c | 2 +- gdb/arm-tdep.c | 50 +- gdb/async-event.c | 1 - gdb/async-event.h | 9 + gdb/auto-load.c | 148 +- gdb/auto-load.h | 13 +- gdb/avr-tdep.c | 6 +- gdb/break-catch-syscall.c | 2 + gdb/breakpoint.c | 193 +- gdb/c-exp.y | 26 +- gdb/c-lang.c | 15 +- gdb/c-lang.h | 18 +- gdb/c-typeprint.c | 2 +- gdb/c-valprint.c | 8 +- gdb/cli/cli-cmds.c | 36 - gdb/cli/cli-interp.c | 8 + gdb/cli/cli-style.c | 17 +- gdb/cli/cli-style.h | 6 +- gdb/coffread.c | 4 +- gdb/compile/compile-c-support.c | 16 +- gdb/compile/compile-c-symbols.c | 13 +- gdb/compile/compile-c-types.c | 12 +- gdb/compile/compile-c.h | 2 +- gdb/compile/compile-cplus-types.c | 6 +- gdb/compile/compile-internal.h | 3 +- gdb/compile/compile-loc2c.c | 30 +- gdb/compile/compile.c | 16 +- gdb/compile/compile.h | 4 +- gdb/configure.tgt | 1 + gdb/copyright.py | 2 +- gdb/cp-valprint.c | 2 +- gdb/cris-tdep.c | 11 +- gdb/csky-tdep.c | 4 +- gdb/d-exp.y | 45 +- gdb/doc/ChangeLog | 64 + gdb/doc/gdb.texinfo | 506 +- gdb/doc/python.texi | 27 +- gdb/dwarf2/attribute.c | 5 +- gdb/dwarf2/attribute.h | 1 + gdb/dwarf2/die.h | 36 +- gdb/dwarf2/index-write.c | 8 + gdb/dwarf2/loc.c | 12 +- gdb/dwarf2/loc.h | 2 +- gdb/dwarf2/read.c | 376 +- gdb/f-array-walker.h | 4 +- gdb/f-exp.y | 29 +- gdb/f-lang.c | 6 +- gdb/f-typeprint.c | 7 +- gdb/f-valprint.c | 7 +- gdb/fbsd-tdep.c | 135 +- gdb/findvar.c | 4 +- gdb/frame.c | 20 +- gdb/frame.h | 16 +- gdb/frv-tdep.c | 2 +- gdb/gcore.c | 136 + gdb/gcore.h | 20 + gdb/gdb_bfd.c | 70 +- gdb/gdbarch.c | 2 +- gdb/gdbcmd.h | 9 +- gdb/gdbtypes.c | 136 +- gdb/gdbtypes.h | 85 +- gdb/gnu-v2-abi.c | 2 +- gdb/gnu-v3-abi.c | 22 +- gdb/go-valprint.c | 2 +- gdb/guile/scm-pretty-print.c | 2 +- gdb/guile/scm-type.c | 4 +- gdb/guile/scm-value.c | 2 +- gdb/hppa-tdep.c | 26 +- gdb/i386-fbsd-tdep.c | 16 +- gdb/i386-gnu-tdep.c | 2 +- gdb/i386-linux-tdep.c | 10 +- gdb/i386-netbsd-tdep.c | 2 +- gdb/i386-obsd-tdep.c | 2 +- gdb/i386-tdep.c | 12 +- gdb/i387-tdep.c | 6 +- gdb/ia64-tdep.c | 6 +- gdb/infcall.c | 2 +- gdb/infcmd.c | 13 + gdb/inferior.c | 58 +- gdb/infrun.c | 803 +- gdb/infrun.h | 4 + gdb/language.c | 13 +- gdb/language.h | 20 +- gdb/linux-nat.c | 7 +- gdb/linux-tdep.c | 149 +- gdb/linux-thread-db.c | 11 +- gdb/lm32-tdep.c | 4 +- gdb/m2-exp.y | 30 +- gdb/m2-valprint.c | 4 +- gdb/m32r-linux-tdep.c | 10 +- gdb/m32r-tdep.c | 4 +- gdb/m68hc11-tdep.c | 4 +- gdb/m68k-linux-tdep.c | 2 +- gdb/m68k-tdep.c | 6 +- gdb/main.c | 16 +- gdb/maint-test-options.c | 2 +- gdb/mep-tdep.c | 2 +- gdb/mi/mi-cmds.c | 5 +- gdb/mips-tdep.c | 40 +- gdb/nat/amd64-linux-siginfo.c | 13 + gdb/nat/linux-osdata.c | 2 +- gdb/nat/windows-nat.c | 24 +- gdb/p-exp.y | 31 +- gdb/p-valprint.c | 2 +- gdb/parse.c | 33 +- gdb/parser-defs.h | 10 + gdb/ppc-fbsd-tdep.c | 4 +- gdb/ppc-netbsd-tdep.c | 2 +- gdb/ppc-obsd-tdep.c | 4 +- gdb/printcmd.c | 13 +- gdb/progspace.c | 2 +- gdb/python/py-breakpoint.c | 8 +- gdb/python/py-frame.c | 7 +- gdb/python/py-param.c | 7 +- gdb/python/py-prettyprint.c | 2 +- gdb/python/py-record-btrace.c | 2 +- gdb/python/py-record.c | 2 +- gdb/python/py-tui.c | 35 +- gdb/python/py-type.c | 10 +- gdb/python/python.c | 2 +- gdb/record-btrace.c | 3 + gdb/record-full.c | 2 + gdb/record.c | 2 +- gdb/regcache.c | 2 +- gdb/registry.h | 2 +- gdb/remote-notif.c | 4 +- gdb/remote-sim.c | 1 + gdb/remote.c | 411 +- gdb/remote.h | 20 + gdb/riscv-fbsd-tdep.c | 20 +- gdb/riscv-linux-tdep.c | 4 +- gdb/riscv-tdep.c | 59 +- gdb/riscv-tdep.h | 23 + gdb/rs6000-tdep.c | 18 +- gdb/rust-lang.c | 6 +- gdb/s390-tdep.c | 14 +- gdb/score-tdep.c | 18 +- gdb/ser-tcp.c | 2 +- gdb/sparc-netbsd-tdep.c | 2 +- gdb/sparc-sol2-tdep.c | 2 +- gdb/sparc64-netbsd-tdep.c | 2 +- gdb/sparc64-sol2-tdep.c | 2 +- gdb/stap-probe.c | 31 +- gdb/symmisc.c | 14 - gdb/symtab.h | 2 +- gdb/target.c | 13 +- gdb/target.h | 12 +- gdb/testsuite/ChangeLog | 344 + gdb/testsuite/gdb.ada/fixed_points.exp | 5 + .../gdb.ada/fixed_points/fixed_points.adb | 3 + gdb/testsuite/gdb.ada/fixed_points/pck.ads | 4 + gdb/testsuite/gdb.ada/local-enum.exp | 88 + gdb/testsuite/gdb.ada/local-enum/local.adb | 28 + gdb/testsuite/gdb.ada/out_of_line_in_inlined.exp | 3 +- gdb/testsuite/gdb.arch/amd64-stap-expressions.S | 43 + gdb/testsuite/gdb.arch/amd64-stap-expressions.exp | 68 + gdb/testsuite/gdb.arch/i386-gnu-cfi.exp | 26 +- gdb/testsuite/gdb.arch/i386-mpx.c | 2 +- gdb/testsuite/gdb.arch/i386-sse-stack-align.S | 40 +- gdb/testsuite/gdb.arch/i386-sse-stack-align.c | 13 +- gdb/testsuite/gdb.arch/i386-sse-stack-align.exp | 2 +- gdb/testsuite/gdb.arch/insn-reloc.c | 81 + gdb/testsuite/gdb.base/bitfields.exp | 137 +- gdb/testsuite/gdb.base/bitfields2.exp | 81 +- gdb/testsuite/gdb.base/break.exp | 23 +- gdb/testsuite/gdb.base/call-sc.exp | 2 +- gdb/testsuite/gdb.base/callfuncs.exp | 2 +- gdb/testsuite/gdb.base/catch-syscall.exp | 3 + gdb/testsuite/gdb.base/complex-parts.exp | 11 + gdb/testsuite/gdb.base/dfp-test.exp | 48 +- gdb/testsuite/gdb.base/endian.exp | 36 +- gdb/testsuite/gdb.base/exprs.exp | 9 +- gdb/testsuite/gdb.base/funcargs.exp | 156 +- gdb/testsuite/gdb.base/hbreak2.exp | 27 +- gdb/testsuite/gdb.base/inferior-noarg.c | 22 + gdb/testsuite/gdb.base/inferior-noarg.exp | 36 + gdb/testsuite/gdb.base/line65535.exp | 2 +- gdb/testsuite/gdb.base/recurse.exp | 37 +- gdb/testsuite/gdb.base/scope.exp | 294 +- gdb/testsuite/gdb.base/sepdebug.exp | 23 +- gdb/testsuite/gdb.base/skip.exp | 60 +- gdb/testsuite/gdb.base/step-over-syscall.exp | 23 + gdb/testsuite/gdb.base/structs.exp | 2 +- gdb/testsuite/gdb.base/style.exp | 437 +- gdb/testsuite/gdb.base/ui-redirect.exp | 8 + gdb/testsuite/gdb.base/until.exp | 10 +- gdb/testsuite/gdb.cp/misc.exp | 10 +- gdb/testsuite/gdb.dwarf2/clang-debug-names.exp | 16 + .../gdb.dwarf2/dw2-out-of-range-end-of-seq.exp | 7 +- gdb/testsuite/gdb.dwarf2/dw2-ranges-psym.exp | 5 +- .../gdb.dwarf2/dw2-step-out-of-function-no-stmt.c | 44 + .../dw2-step-out-of-function-no-stmt.exp | 126 + gdb/testsuite/gdb.dwarf2/enqueued-cu-base-addr.exp | 2 +- gdb/testsuite/gdb.dwarf2/fission-base.S | 5 +- gdb/testsuite/gdb.dwarf2/fission-base.exp | 14 +- gdb/testsuite/gdb.dwarf2/fission-loclists-pie.S | 4 +- gdb/testsuite/gdb.dwarf2/fission-loclists-pie.exp | 13 +- gdb/testsuite/gdb.dwarf2/fission-loclists.S | 5 +- gdb/testsuite/gdb.dwarf2/fission-loclists.exp | 14 +- gdb/testsuite/gdb.dwarf2/fission-multi-cu.S | 6 +- gdb/testsuite/gdb.dwarf2/fission-multi-cu.exp | 14 +- gdb/testsuite/gdb.dwarf2/fission-reread.S | 7 +- gdb/testsuite/gdb.dwarf2/fission-reread.exp | 36 +- gdb/testsuite/gdb.dwarf2/loclists-multiple-cus.c | 37 + gdb/testsuite/gdb.dwarf2/loclists-multiple-cus.exp | 146 + gdb/testsuite/gdb.dwarf2/loclists-sec-offset.c | 69 + gdb/testsuite/gdb.dwarf2/loclists-sec-offset.exp | 261 + gdb/testsuite/gdb.dwarf2/main-subprogram.exp | 14 +- gdb/testsuite/gdb.dwarf2/rnglists-multiple-cus.exp | 102 + gdb/testsuite/gdb.dwarf2/rnglists-sec-offset.exp | 143 + gdb/testsuite/gdb.fortran/array-slices.exp | 3 +- gdb/testsuite/gdb.fortran/mixed-lang-stack.exp | 21 +- gdb/testsuite/gdb.opt/solib-intra-step.exp | 35 +- gdb/testsuite/gdb.python/py-breakpoint.exp | 24 + gdb/testsuite/gdb.python/py-format-string.exp | 6 +- gdb/testsuite/gdb.python/py-framefilter.exp | 2 +- gdb/testsuite/gdb.python/python.exp | 2 +- gdb/testsuite/gdb.python/tui-window-disabled.c | 43 + gdb/testsuite/gdb.python/tui-window-disabled.exp | 189 + gdb/testsuite/gdb.python/tui-window-disabled.py | 89 + gdb/testsuite/gdb.python/tui-window.exp | 6 + gdb/testsuite/gdb.python/tui-window.py | 10 +- gdb/testsuite/gdb.threads/attach-non-stop.c | 58 + gdb/testsuite/gdb.threads/attach-non-stop.exp | 148 + gdb/testsuite/gdb.threads/detach-step-over.c | 112 + gdb/testsuite/gdb.threads/detach-step-over.exp | 290 + gdb/testsuite/gdb.threads/killed-outside.exp | 3 + gdb/testsuite/gdb.tui/scroll.exp | 72 + .../gdb.tui/tui-layout-asm-short-prog.exp | 4 +- gdb/testsuite/gdb.tui/tui-layout-asm.exp | 7 +- gdb/testsuite/gdb.tui/winheight.exp | 14 + gdb/testsuite/gdb.xml/tdesc-regs.exp | 3 +- gdb/testsuite/lib/dwarf.exp | 451 +- gdb/testsuite/lib/gdb-utils.exp | 1 + gdb/testsuite/lib/gdb.exp | 177 +- gdb/testsuite/lib/gdbserver-support.exp | 3 + gdb/testsuite/lib/mi-support.exp | 41 +- gdb/testsuite/lib/prompt.exp | 2 - gdb/testsuite/lib/range-stepping-support.exp | 8 +- gdb/testsuite/lib/tuiterm.exp | 573 +- gdb/thread.c | 7 +- gdb/tilegx-tdep.c | 18 +- gdb/top.c | 21 +- gdb/top.h | 7 +- gdb/tracepoint.c | 6 +- gdb/trad-frame.c | 98 +- gdb/trad-frame.h | 50 +- gdb/tramp-frame.c | 7 +- gdb/tui/tui-data.h | 4 +- gdb/tui/tui-disasm.c | 13 +- gdb/tui/tui-interp.c | 23 +- gdb/tui/tui-io.c | 73 +- gdb/tui/tui-io.h | 5 + gdb/tui/tui-layout.c | 44 +- gdb/tui/tui-layout.h | 16 + gdb/tui/tui-location.c | 81 + gdb/tui/tui-location.h | 93 + gdb/tui/tui-regs.c | 19 +- gdb/tui/tui-source.c | 9 +- gdb/tui/tui-stack.c | 114 +- gdb/tui/tui-stack.h | 19 - gdb/tui/tui-wingeneral.c | 4 - gdb/tui/tui-winsource.c | 3 +- gdb/tui/tui.c | 22 +- gdb/tui/tui.h | 1 + gdb/unittests/command-def-selftests.c | 6 +- gdb/unittests/gdb_tilde_expand-selftests.c | 94 + gdb/unittests/observable-selftests.c | 2 +- gdb/unittests/optional/assignment/1.cc | 2 +- gdb/unittests/optional/assignment/2.cc | 2 +- gdb/unittests/optional/assignment/3.cc | 2 +- gdb/unittests/optional/assignment/4.cc | 2 +- gdb/unittests/optional/assignment/5.cc | 2 +- gdb/unittests/optional/assignment/6.cc | 2 +- gdb/utils.c | 73 +- gdb/v850-tdep.c | 5 +- gdb/valarith.c | 11 +- gdb/valops.c | 18 +- gdb/valprint.c | 12 +- gdb/value.c | 11 +- gdb/varobj.c | 2 +- gdb/vax-tdep.c | 2 +- gdb/windows-nat.c | 118 +- gdbserver/ChangeLog | 34 + gdbserver/Makefile.in | 2 +- gdbserver/ax.cc | 2 +- gdbserver/debug.cc | 2 +- gdbserver/linux-low.cc | 33 +- gdbserver/linux-x86-low.cc | 59 +- gdbserver/remote-utils.cc | 4 + gdbserver/server.cc | 9 + gdbserver/tracepoint.cc | 18 +- gdbsupport/ChangeLog | 20 + gdbsupport/common-debug.cc | 6 +- gdbsupport/common-debug.h | 8 + gdbsupport/common-defs.h | 4 +- gdbsupport/common-utils.h | 6 +- gdbsupport/gdb_tilde_expand.cc | 46 +- gdbsupport/gdb_tilde_expand.h | 3 +- gnulib/ChangeLog | 6 + gnulib/Makefile.in | 108 +- gnulib/aclocal.m4 | 7 +- gnulib/config.in | 180 +- gnulib/configure | 2721 ++-- gnulib/import/Makefile.am | 183 +- gnulib/import/Makefile.in | 312 +- gnulib/import/_Noreturn.h | 2 +- gnulib/import/alloca.c | 286 +- gnulib/import/alloca.in.h | 4 +- gnulib/import/arg-nonnull.h | 4 +- gnulib/import/arpa_inet.in.h | 2 +- gnulib/import/assure.h | 2 +- gnulib/import/at-func.c | 2 +- gnulib/import/attribute.h | 25 +- gnulib/import/basename-lgpl.c | 22 +- gnulib/import/basename-lgpl.h | 78 + gnulib/import/btowc.c | 2 +- gnulib/import/c++defs.h | 26 +- gnulib/import/canonicalize-lgpl.c | 495 +- gnulib/import/cdefs.h | 207 +- gnulib/import/chdir-long.c | 2 +- gnulib/import/chdir-long.h | 2 +- gnulib/import/cloexec.c | 2 +- gnulib/import/cloexec.h | 2 +- gnulib/import/close.c | 10 +- gnulib/import/closedir.c | 2 +- gnulib/import/count-one-bits.h | 5 +- gnulib/import/ctype.in.h | 2 +- gnulib/import/dirent-private.h | 2 +- gnulib/import/dirent.in.h | 4 +- gnulib/import/dirfd.c | 2 +- gnulib/import/dirname-lgpl.c | 2 +- gnulib/import/dirname.h | 9 +- gnulib/import/dup-safer-flag.c | 2 +- gnulib/import/dup-safer.c | 2 +- gnulib/import/dup.c | 10 +- gnulib/import/dup2.c | 104 +- gnulib/import/eloop-threshold.h | 83 + gnulib/import/errno.in.h | 2 +- gnulib/import/error.c | 6 +- gnulib/import/error.h | 27 +- gnulib/import/exitfail.c | 2 +- gnulib/import/exitfail.h | 2 +- gnulib/import/extra/update-copyright | 2 +- gnulib/import/fchdir.c | 2 +- gnulib/import/fcntl.c | 10 +- gnulib/import/fcntl.in.h | 45 +- gnulib/import/fd-hook.c | 2 +- gnulib/import/fd-hook.h | 2 +- gnulib/import/fd-safer-flag.c | 2 +- gnulib/import/fd-safer.c | 2 +- gnulib/import/fdopendir.c | 2 +- gnulib/import/filename.h | 22 +- gnulib/import/filenamecat-lgpl.c | 5 +- gnulib/import/filenamecat.h | 2 +- gnulib/import/flexmember.h | 2 +- gnulib/import/float+.h | 2 +- gnulib/import/float.c | 2 +- gnulib/import/float.in.h | 8 +- gnulib/import/fnmatch.c | 14 +- gnulib/import/fnmatch.in.h | 2 +- gnulib/import/fnmatch_loop.c | 19 +- gnulib/import/fpucw.h | 6 +- gnulib/import/free.c | 47 + gnulib/import/frexp.c | 2 +- gnulib/import/frexpl.c | 2 +- gnulib/import/fstat.c | 2 +- gnulib/import/fstatat.c | 2 +- gnulib/import/getcwd-lgpl.c | 6 +- gnulib/import/getcwd.c | 86 +- gnulib/import/getdtablesize.c | 2 +- gnulib/import/getlogin_r.c | 2 +- gnulib/import/getprogname.c | 42 +- gnulib/import/getprogname.h | 2 +- gnulib/import/getrandom.c | 4 +- gnulib/import/gettext.h | 2 +- gnulib/import/gettimeofday.c | 13 +- gnulib/import/glob-libc.h | 2 +- gnulib/import/glob.c | 14 +- gnulib/import/glob.in.h | 6 +- gnulib/import/glob_internal.h | 2 +- gnulib/import/glob_pattern_p.c | 2 +- gnulib/import/globfree.c | 2 +- gnulib/import/glthread/lock.c | 2 +- gnulib/import/glthread/lock.h | 2 +- gnulib/import/glthread/threadlib.c | 37 +- gnulib/import/hard-locale.c | 2 +- gnulib/import/hard-locale.h | 2 +- gnulib/import/idx.h | 114 + gnulib/import/inet_ntop.c | 2 +- gnulib/import/intprops.h | 72 +- gnulib/import/inttypes.in.h | 464 +- gnulib/import/isblank.c | 2 +- gnulib/import/isnan.c | 2 +- gnulib/import/isnand-nolibm.h | 6 +- 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sim/rx/ChangeLog | 69 + sim/rx/configure | 22 +- sim/rx/configure.ac | 1 - sim/rx/cpu.h | 2 +- sim/rx/err.c | 11 +- sim/rx/fpu.c | 2 +- sim/rx/gdb-if.c | 14 +- sim/rx/load.c | 3 +- sim/rx/mem.c | 18 +- sim/rx/mem.h | 4 +- sim/rx/reg.c | 14 +- sim/rx/rx.c | 6 +- sim/rx/syscalls.c | 7 +- sim/rx/trace.c | 4 +- sim/sh/ChangeLog | 4 + sim/sh/configure | 19 +- sim/testsuite/ChangeLog | 9 + sim/testsuite/Makefile.in | 1 - sim/testsuite/{sim => }/aarch64/ChangeLog | 0 sim/testsuite/{sim => }/aarch64/adds.s | 0 sim/testsuite/{sim => }/aarch64/addv.s | 0 sim/testsuite/{sim => }/aarch64/allinsn.exp | 0 sim/testsuite/{sim => }/aarch64/bit.s | 0 sim/testsuite/{sim => }/aarch64/cmtst.s | 0 sim/testsuite/{sim => }/aarch64/cnt.s | 0 sim/testsuite/{sim => }/aarch64/fcmXX.s | 0 sim/testsuite/{sim => }/aarch64/fcmp.s | 0 sim/testsuite/{sim => }/aarch64/fcsel.s | 0 sim/testsuite/{sim => }/aarch64/fcvtl.s | 0 sim/testsuite/{sim => }/aarch64/fcvtz.s | 0 sim/testsuite/{sim => }/aarch64/fminnm.s | 0 sim/testsuite/{sim => }/aarch64/fstur.s | 0 sim/testsuite/{sim => }/aarch64/ldn_multiple.s | 0 sim/testsuite/{sim => }/aarch64/ldn_single.s | 0 sim/testsuite/{sim => }/aarch64/ldnr.s | 0 sim/testsuite/{sim => }/aarch64/mla.s | 0 sim/testsuite/{sim => }/aarch64/mls.s | 0 sim/testsuite/{sim => }/aarch64/mul.s | 0 sim/testsuite/{sim => }/aarch64/pass.s | 0 sim/testsuite/{sim => }/aarch64/stn_multiple.s | 0 sim/testsuite/{sim => }/aarch64/stn_single.s | 0 sim/testsuite/{sim => }/aarch64/sumov.s | 0 sim/testsuite/{sim => }/aarch64/sumulh.s | 0 sim/testsuite/{sim => }/aarch64/tbnz.s | 0 sim/testsuite/{sim => }/aarch64/testutils.inc | 0 sim/testsuite/{sim => }/aarch64/uzp.s | 0 sim/testsuite/{sim => }/aarch64/xtl.s | 0 sim/testsuite/{sim => }/aarch64/xtn.s | 0 sim/testsuite/{sim => }/arm/ChangeLog | 0 sim/testsuite/{sim => }/arm/adc.cgs | 0 sim/testsuite/{sim => }/arm/add.cgs | 0 sim/testsuite/{sim => }/arm/allinsn.exp | 0 sim/testsuite/{sim => }/arm/and.cgs | 0 sim/testsuite/{sim => }/arm/b.cgs | 0 sim/testsuite/{sim => }/arm/bic.cgs | 0 sim/testsuite/{sim => }/arm/bl.cgs | 0 sim/testsuite/{sim => }/arm/bx.cgs | 0 sim/testsuite/{sim => }/arm/cmn.cgs | 0 sim/testsuite/{sim => }/arm/cmp.cgs | 0 sim/testsuite/{sim => }/arm/eor.cgs | 0 sim/testsuite/{sim => }/arm/hello.ms | 0 sim/testsuite/{sim => }/arm/iwmmxt/iwmmxt.exp | 0 sim/testsuite/{sim => }/arm/iwmmxt/tbcst.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/testutils.inc | 0 sim/testsuite/{sim => }/arm/iwmmxt/textrm.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/tinsr.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/tmia.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/tmiaph.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/tmiaxy.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/tmovmsk.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wacc.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wadd.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/waligni.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/walignr.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wand.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wandn.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wavg2.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wcmpeq.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wcmpgt.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wmac.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wmadd.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wmax.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wmin.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wmov.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wmul.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wor.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wpack.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wror.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wsad.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wshufh.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wsll.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wsra.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wsrl.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wsub.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wunpckeh.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wunpckel.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wunpckih.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wunpckil.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wxor.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wzero.cgs | 0 sim/testsuite/{sim => }/arm/ldm.cgs | 0 sim/testsuite/{sim => }/arm/ldr.cgs | 0 sim/testsuite/{sim => }/arm/ldrb.cgs | 0 sim/testsuite/{sim => }/arm/ldrh.cgs | 0 sim/testsuite/{sim => }/arm/ldrsb.cgs | 0 sim/testsuite/{sim => }/arm/ldrsh.cgs | 0 sim/testsuite/{sim => }/arm/misaligned1.ms | 0 sim/testsuite/{sim => }/arm/misaligned2.ms | 0 sim/testsuite/{sim => }/arm/misaligned3.ms | 0 sim/testsuite/{sim => }/arm/misc.exp | 0 sim/testsuite/{sim => }/arm/mla.cgs | 0 sim/testsuite/{sim => }/arm/mov.cgs | 0 sim/testsuite/{sim => }/arm/movw-movt.ms | 0 sim/testsuite/{sim => }/arm/mrs.cgs | 0 sim/testsuite/{sim => }/arm/msr.cgs | 0 sim/testsuite/{sim => }/arm/mul.cgs | 0 sim/testsuite/{sim => }/arm/mvn.cgs | 0 sim/testsuite/{sim => }/arm/orr.cgs | 0 sim/testsuite/{sim => }/arm/rsb.cgs | 0 sim/testsuite/{sim => }/arm/rsc.cgs | 0 sim/testsuite/{sim => }/arm/sbc.cgs | 0 sim/testsuite/{sim => }/arm/smlal.cgs | 0 sim/testsuite/{sim => }/arm/smull.cgs | 0 sim/testsuite/{sim => }/arm/stm.cgs | 0 sim/testsuite/{sim => }/arm/str.cgs | 0 sim/testsuite/{sim => }/arm/strb.cgs | 0 sim/testsuite/{sim => }/arm/strh.cgs | 0 sim/testsuite/{sim => }/arm/sub.cgs | 0 sim/testsuite/{sim => }/arm/swi.cgs | 0 sim/testsuite/{sim => }/arm/swp.cgs | 0 sim/testsuite/{sim => }/arm/swpb.cgs | 0 sim/testsuite/{sim => }/arm/teq.cgs | 0 sim/testsuite/{sim => }/arm/testutils.inc | 0 sim/testsuite/{sim => }/arm/thumb/adc.cgs | 0 sim/testsuite/{sim => }/arm/thumb/add-hd-hs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/add-hd-rs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/add-rd-hs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/add-sp.cgs | 0 sim/testsuite/{sim => }/arm/thumb/add.cgs | 0 sim/testsuite/{sim => }/arm/thumb/addi.cgs | 0 sim/testsuite/{sim => }/arm/thumb/addi8.cgs | 0 sim/testsuite/{sim => }/arm/thumb/allthumb.exp | 0 sim/testsuite/{sim => }/arm/thumb/and.cgs | 0 sim/testsuite/{sim => }/arm/thumb/asr.cgs | 0 sim/testsuite/{sim => }/arm/thumb/b.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bcc.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bcs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/beq.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bge.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bgt.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bhi.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bic.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bl-hi.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bl-lo.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ble.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bls.cgs | 0 sim/testsuite/{sim => }/arm/thumb/blt.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bmi.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bne.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bpl.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bvc.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bvs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bx-hs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/bx-rs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/cmn.cgs | 0 sim/testsuite/{sim => }/arm/thumb/cmp-hd-hs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/cmp-hd-rs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/cmp-rd-hs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/cmp.cgs | 0 sim/testsuite/{sim => }/arm/thumb/eor.cgs | 0 sim/testsuite/{sim => }/arm/thumb/lda-pc.cgs | 0 sim/testsuite/{sim => }/arm/thumb/lda-sp.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldmia.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldr-imm.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldr-pc.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldr-sprel.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldr.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldrb-imm.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldrb.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldrh-imm.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldrh.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldsb.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ldsh.cgs | 0 sim/testsuite/{sim => }/arm/thumb/lsl.cgs | 0 sim/testsuite/{sim => }/arm/thumb/lsr.cgs | 0 sim/testsuite/{sim => }/arm/thumb/mov-hd-hs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/mov-hd-rs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/mov-rd-hs.cgs | 0 sim/testsuite/{sim => }/arm/thumb/mov.cgs | 0 sim/testsuite/{sim => }/arm/thumb/mul.cgs | 0 sim/testsuite/{sim => }/arm/thumb/mvn.cgs | 0 sim/testsuite/{sim => }/arm/thumb/neg.cgs | 0 sim/testsuite/{sim => }/arm/thumb/orr.cgs | 0 sim/testsuite/{sim => }/arm/thumb/pop-pc.cgs | 0 sim/testsuite/{sim => }/arm/thumb/pop.cgs | 0 sim/testsuite/{sim => }/arm/thumb/push-lr.cgs | 0 sim/testsuite/{sim => }/arm/thumb/push.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ror.cgs | 0 sim/testsuite/{sim => }/arm/thumb/sbc.cgs | 0 sim/testsuite/{sim => }/arm/thumb/stmia.cgs | 0 sim/testsuite/{sim => }/arm/thumb/str-imm.cgs | 0 sim/testsuite/{sim => }/arm/thumb/str-sprel.cgs | 0 sim/testsuite/{sim => }/arm/thumb/str.cgs | 0 sim/testsuite/{sim => }/arm/thumb/strb-imm.cgs | 0 sim/testsuite/{sim => }/arm/thumb/strb.cgs | 0 sim/testsuite/{sim => }/arm/thumb/strh-imm.cgs | 0 sim/testsuite/{sim => }/arm/thumb/strh.cgs | 0 sim/testsuite/{sim => }/arm/thumb/sub-sp.cgs | 0 sim/testsuite/{sim => }/arm/thumb/sub.cgs | 0 sim/testsuite/{sim => }/arm/thumb/subi.cgs | 0 sim/testsuite/{sim => }/arm/thumb/subi8.cgs | 0 sim/testsuite/{sim => }/arm/thumb/swi.cgs | 0 sim/testsuite/{sim => }/arm/thumb/testutils.inc | 0 sim/testsuite/{sim => }/arm/thumb/tst.cgs | 0 sim/testsuite/{sim => }/arm/tst.cgs | 0 sim/testsuite/{sim => }/arm/umlal.cgs | 0 sim/testsuite/{sim => }/arm/umull.cgs | 0 sim/testsuite/{sim => }/arm/xscale/blx.cgs | 0 sim/testsuite/{sim => }/arm/xscale/mia.cgs | 0 sim/testsuite/{sim => }/arm/xscale/miaph.cgs | 0 sim/testsuite/{sim => }/arm/xscale/miaxy.cgs | 0 sim/testsuite/{sim => }/arm/xscale/mra.cgs | 0 sim/testsuite/{sim => }/arm/xscale/testutils.inc | 0 sim/testsuite/{sim => }/arm/xscale/xscale.exp | 0 sim/testsuite/{sim => }/avr/ChangeLog | 0 sim/testsuite/{sim => }/avr/allinsn.exp | 0 sim/testsuite/{sim => }/avr/pass.s | 0 sim/testsuite/{sim => }/avr/testutils.inc | 0 sim/testsuite/{sim => }/bfin/.gitignore | 0 sim/testsuite/{sim => }/bfin/10272_small.s | 0 sim/testsuite/{sim => }/bfin/10436.s | 0 sim/testsuite/{sim => }/bfin/10622.s | 0 sim/testsuite/{sim => }/bfin/10742.s | 0 sim/testsuite/{sim => }/bfin/10799.s | 0 sim/testsuite/{sim => }/bfin/11080.s | 0 sim/testsuite/{sim => }/bfin/7641.s | 0 sim/testsuite/bfin/ChangeLog | 374 + sim/testsuite/{sim => }/bfin/PN_generator.s | 0 sim/testsuite/{sim => }/bfin/a0.s | 0 sim/testsuite/{sim => }/bfin/a0shift.S | 0 sim/testsuite/{sim => }/bfin/a1.s | 0 sim/testsuite/{sim => }/bfin/a10.s | 0 sim/testsuite/{sim => }/bfin/a11.S | 0 sim/testsuite/{sim => }/bfin/a12.s | 0 sim/testsuite/{sim => }/bfin/a2.s | 0 sim/testsuite/{sim => }/bfin/a20.S | 0 sim/testsuite/{sim => }/bfin/a21.s | 0 sim/testsuite/{sim => }/bfin/a22.s | 0 sim/testsuite/{sim => }/bfin/a23.s | 0 sim/testsuite/{sim => }/bfin/a24.s | 0 sim/testsuite/{sim => }/bfin/a25.s | 0 sim/testsuite/{sim => }/bfin/a26.s | 0 sim/testsuite/{sim => }/bfin/a3.s | 0 sim/testsuite/{sim => }/bfin/a30.s | 0 sim/testsuite/{sim => }/bfin/a4.s | 0 sim/testsuite/{sim => }/bfin/a5.s | 0 sim/testsuite/{sim => }/bfin/a6.s | 0 sim/testsuite/{sim => }/bfin/a7.s | 0 sim/testsuite/{sim => }/bfin/a8.s | 0 sim/testsuite/{sim => }/bfin/a9.s | 0 sim/testsuite/{sim => }/bfin/abs-2.S | 0 sim/testsuite/{sim => }/bfin/abs-3.S | 0 sim/testsuite/{sim => }/bfin/abs-4.S | 0 sim/testsuite/{sim => }/bfin/abs.S | 0 sim/testsuite/{sim => }/bfin/abs_acc.s | 0 sim/testsuite/{sim => }/bfin/acc-rot.s | 0 sim/testsuite/{sim => }/bfin/acp5_19.s | 0 sim/testsuite/{sim => }/bfin/acp5_4.s | 0 sim/testsuite/{sim => }/bfin/add_imm7.s | 0 sim/testsuite/{sim => }/bfin/add_shift.S | 0 sim/testsuite/{sim => }/bfin/add_sub_acc.s | 0 sim/testsuite/{sim => }/bfin/addsub_flags.S | 0 sim/testsuite/{sim => }/bfin/algnbug1.s | 0 sim/testsuite/{sim => }/bfin/algnbug2.s | 0 sim/testsuite/{sim => }/bfin/allinsn.exp | 0 sim/testsuite/{sim => }/bfin/argc.c | 0 sim/testsuite/{sim => }/bfin/ashift.s | 0 sim/testsuite/{sim => }/bfin/ashift_flags.s | 0 sim/testsuite/{sim => }/bfin/ashift_left.s | 0 sim/testsuite/{sim => }/bfin/b0.S | 0 sim/testsuite/{sim => }/bfin/b1.s | 0 sim/testsuite/{sim => }/bfin/b2.S | 0 sim/testsuite/{sim => }/bfin/brcc.s | 0 sim/testsuite/{sim => }/bfin/brevadd.s | 0 sim/testsuite/{sim => }/bfin/byteop16m.s | 0 sim/testsuite/{sim => }/bfin/byteop16p.s | 0 sim/testsuite/{sim => }/bfin/byteop1p.s | 0 sim/testsuite/{sim => }/bfin/byteop2p.s | 0 sim/testsuite/{sim => }/bfin/byteop3p.s | 0 sim/testsuite/{sim => }/bfin/byteunpack.s | 0 .../{sim => }/bfin/c_alu2op_arith_r_sft.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_conv_b.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_conv_h.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_conv_mix.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_conv_neg.s | 0 .../{sim => }/bfin/c_alu2op_conv_toggle.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_conv_xb.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_conv_xh.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_divq.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_divs.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_log_l_sft.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_log_r_sft.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_shadd_1.s | 0 sim/testsuite/{sim => }/bfin/c_alu2op_shadd_2.s | 0 sim/testsuite/{sim => }/bfin/c_br_preg_killed_ac.s | 0 .../{sim => }/bfin/c_br_preg_killed_ex1.s | 0 sim/testsuite/{sim => }/bfin/c_br_preg_stall_ac.s | 0 sim/testsuite/{sim => }/bfin/c_br_preg_stall_ex1.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_bp1.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_bp2.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_bp3.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_bp4.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_brf_bp.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_brf_brt_bp.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_brf_brt_nbp.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_brf_fbkwd.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_brf_nbp.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_brt_bp.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_brt_nbp.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_kills_dhits.s | 0 sim/testsuite/{sim => }/bfin/c_brcc_kills_dmiss.s | 0 sim/testsuite/{sim => }/bfin/c_cactrl_iflush_pr.s | 0 .../{sim => }/bfin/c_cactrl_iflush_pr_pp.s | 0 sim/testsuite/{sim => }/bfin/c_calla_ljump.s | 0 sim/testsuite/{sim => }/bfin/c_calla_subr.s | 0 sim/testsuite/{sim => }/bfin/c_cc2dreg.s | 0 sim/testsuite/{sim => }/bfin/c_cc2stat_cc_ac.S | 0 sim/testsuite/{sim => }/bfin/c_cc2stat_cc_an.s | 0 sim/testsuite/{sim => }/bfin/c_cc2stat_cc_aq.s | 0 sim/testsuite/{sim => }/bfin/c_cc2stat_cc_av0.S | 0 sim/testsuite/{sim => }/bfin/c_cc2stat_cc_av1.S | 0 sim/testsuite/{sim => }/bfin/c_cc2stat_cc_az.s | 0 .../{sim => }/bfin/c_cc_flag_ccmv_depend.S | 0 .../{sim => }/bfin/c_cc_flagdreg_mvbrsft.s | 0 .../{sim => }/bfin/c_cc_flagdreg_mvbrsft_s1.s | 0 .../{sim => }/bfin/c_cc_flagdreg_mvbrsft_sn.s | 0 .../{sim => }/bfin/c_cc_regmvlogi_mvbrsft.s | 0 .../{sim => }/bfin/c_cc_regmvlogi_mvbrsft_s1.s | 0 .../{sim => }/bfin/c_cc_regmvlogi_mvbrsft_sn.S | 0 sim/testsuite/{sim => }/bfin/c_ccflag_a0a1.S | 0 sim/testsuite/{sim => }/bfin/c_ccflag_dr_dr.s | 0 sim/testsuite/{sim => }/bfin/c_ccflag_dr_dr_uu.s | 0 sim/testsuite/{sim => }/bfin/c_ccflag_dr_imm3.s | 0 sim/testsuite/{sim => }/bfin/c_ccflag_dr_imm3_uu.s | 0 sim/testsuite/{sim => }/bfin/c_ccflag_pr_imm3.s | 0 sim/testsuite/{sim => }/bfin/c_ccflag_pr_imm3_uu.s | 0 sim/testsuite/{sim => }/bfin/c_ccflag_pr_pr.s | 0 sim/testsuite/{sim => }/bfin/c_ccflag_pr_pr_uu.s | 0 sim/testsuite/{sim => }/bfin/c_ccmv_cc_dr_dr.s | 0 sim/testsuite/{sim => }/bfin/c_ccmv_cc_dr_pr.s | 0 sim/testsuite/{sim => }/bfin/c_ccmv_cc_pr_pr.s | 0 sim/testsuite/{sim => }/bfin/c_ccmv_ncc_dr_dr.s | 0 sim/testsuite/{sim => }/bfin/c_ccmv_ncc_dr_pr.s | 0 sim/testsuite/{sim => }/bfin/c_ccmv_ncc_pr_pr.s | 0 sim/testsuite/{sim => }/bfin/c_comp3op_dr_and_dr.s | 0 .../{sim => }/bfin/c_comp3op_dr_minus_dr.s | 0 sim/testsuite/{sim => }/bfin/c_comp3op_dr_mix.s | 0 sim/testsuite/{sim => }/bfin/c_comp3op_dr_or_dr.s | 0 .../{sim => }/bfin/c_comp3op_dr_plus_dr.s | 0 sim/testsuite/{sim => }/bfin/c_comp3op_dr_xor_dr.s | 0 .../{sim => }/bfin/c_comp3op_pr_plus_pr_sh1.s | 0 .../{sim => }/bfin/c_comp3op_pr_plus_pr_sh2.s | 0 .../{sim => }/bfin/c_compi2opd_dr_add_i7_n.s | 0 .../{sim => }/bfin/c_compi2opd_dr_add_i7_p.s | 0 .../{sim => }/bfin/c_compi2opd_dr_eq_i7_n.s | 0 .../{sim => }/bfin/c_compi2opd_dr_eq_i7_p.s | 0 sim/testsuite/{sim => }/bfin/c_compi2opd_flags.S | 0 sim/testsuite/{sim => }/bfin/c_compi2opd_flags_2.S | 0 .../{sim => }/bfin/c_compi2opp_pr_add_i7_n.s | 0 .../{sim => }/bfin/c_compi2opp_pr_add_i7_p.s | 0 .../{sim => }/bfin/c_compi2opp_pr_eq_i7_n.s | 0 .../{sim => }/bfin/c_compi2opp_pr_eq_i7_p.s | 0 .../{sim => }/bfin/c_dagmodik_lnz_imgebl.s | 0 .../{sim => }/bfin/c_dagmodik_lnz_imltbl.s | 0 .../{sim => }/bfin/c_dagmodik_lz_inc_dec.s | 0 .../{sim => }/bfin/c_dagmodim_lnz_imgebl.s | 0 .../{sim => }/bfin/c_dagmodim_lnz_imltbl.s | 0 .../{sim => }/bfin/c_dagmodim_lz_inc_dec.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_a0_pm_a1.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_a0a1s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_a_abs_a.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_a_neg_a.s | 0 .../{sim => }/bfin/c_dsp32alu_aa_absabs.s | 0 .../{sim => }/bfin/c_dsp32alu_aa_negneg.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_abs.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_absabs.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_alhwx.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_awx.s | 0 .../{sim => }/bfin/c_dsp32alu_byteop1ew.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_byteop2.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_byteop3.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_bytepack.s | 0 .../{sim => }/bfin/c_dsp32alu_byteunpack.s | 0 .../{sim => }/bfin/c_dsp32alu_disalnexcpt.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_max.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_maxmax.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_min.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_minmin.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_mix.s | 0 .../{sim => }/bfin/c_dsp32alu_r_lh_a0pa1.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_r_negneg.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_m.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_p.s | 0 .../{sim => }/bfin/c_dsp32alu_rh_rnd12_m.s | 0 .../{sim => }/bfin/c_dsp32alu_rh_rnd12_p.s | 0 .../{sim => }/bfin/c_dsp32alu_rh_rnd20_m.s | 0 .../{sim => }/bfin/c_dsp32alu_rh_rnd20_p.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_m.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_p.s | 0 .../{sim => }/bfin/c_dsp32alu_rl_rnd12_m.s | 0 .../{sim => }/bfin/c_dsp32alu_rl_rnd12_p.s | 0 .../{sim => }/bfin/c_dsp32alu_rl_rnd20_m.s | 0 .../{sim => }/bfin/c_dsp32alu_rl_rnd20_p.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rlh_rnd.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rm.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rmm.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rmp.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rp.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rpm.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rpp.s | 0 .../{sim => }/bfin/c_dsp32alu_rr_lph_a1a0.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpm.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpm_aa.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpmmp.s | 0 .../{sim => }/bfin/c_dsp32alu_rrpmmp_sft.s | 0 .../{sim => }/bfin/c_dsp32alu_rrpmmp_sft_x.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_rrppmm.s | 0 .../{sim => }/bfin/c_dsp32alu_rrppmm_sft.s | 0 .../{sim => }/bfin/c_dsp32alu_rrppmm_sft_x.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_saa.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_sat_aa.S | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_search.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32alu_sgn.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_a1a0.s | 0 .../{sim => }/bfin/c_dsp32mac_a1a0_iuw32.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_a1a0_m.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_i.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_ih.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_is.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_iu.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_m.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_t.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_tu.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_u.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_i.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_ih.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_is.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_iu.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_m.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_t.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_tu.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_u.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1a0.s | 0 .../{sim => }/bfin/c_dsp32mac_dr_a1a0_iutsh.s | 0 .../{sim => }/bfin/c_dsp32mac_dr_a1a0_m.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_mix.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a0_i.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a0_is.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a0_m.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a0_s.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a0_u.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1_i.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1_is.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1_m.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1_s.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1_u.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1a0.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1a0_i.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1a0_is.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1a0_m.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1a0_s.s | 0 .../{sim => }/bfin/c_dsp32mac_pair_a1a0_u.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_mix.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_i.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_ih.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_is.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_iu.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_i.s | 0 .../{sim => }/bfin/c_dsp32mult_dr_m_iutsh.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_t.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_u.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_mix.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_t.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_tu.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_u.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_pair.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_i.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_is.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m.s | 0 .../{sim => }/bfin/c_dsp32mult_pair_m_i.s | 0 .../{sim => }/bfin/c_dsp32mult_pair_m_is.s | 0 .../{sim => }/bfin/c_dsp32mult_pair_m_s.s | 0 .../{sim => }/bfin/c_dsp32mult_pair_m_u.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_u.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_a0alr.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_af.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_af_s.s | 0 .../{sim => }/bfin/c_dsp32shift_ahalf_ln.s | 0 .../{sim => }/bfin/c_dsp32shift_ahalf_ln_s.s | 0 .../{sim => }/bfin/c_dsp32shift_ahalf_lp.s | 0 .../{sim => }/bfin/c_dsp32shift_ahalf_lp_s.s | 0 .../{sim => }/bfin/c_dsp32shift_ahalf_rn.s | 0 .../{sim => }/bfin/c_dsp32shift_ahalf_rn_s.s | 0 .../{sim => }/bfin/c_dsp32shift_ahalf_rp.s | 0 .../{sim => }/bfin/c_dsp32shift_ahalf_rp_s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_ahh.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_ahh_s.s | 0 .../{sim => }/bfin/c_dsp32shift_align16.s | 0 .../{sim => }/bfin/c_dsp32shift_align24.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_align8.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_amix.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_bitmux.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_bxor.s | 0 .../{sim => }/bfin/c_dsp32shift_expadj_h.s | 0 .../{sim => }/bfin/c_dsp32shift_expadj_l.s | 0 .../{sim => }/bfin/c_dsp32shift_expadj_r.s | 0 .../{sim => }/bfin/c_dsp32shift_expexp_r.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_fdepx.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_fextx.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_lf.s | 0 .../{sim => }/bfin/c_dsp32shift_lhalf_ln.s | 0 .../{sim => }/bfin/c_dsp32shift_lhalf_lp.s | 0 .../{sim => }/bfin/c_dsp32shift_lhalf_rn.s | 0 .../{sim => }/bfin/c_dsp32shift_lhalf_rp.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_lhh.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_lmix.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_ones.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_pack.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_rot.s | 0 .../{sim => }/bfin/c_dsp32shift_rot_mix.s | 0 .../{sim => }/bfin/c_dsp32shift_signbits_r.s | 0 .../{sim => }/bfin/c_dsp32shift_signbits_rh.s | 0 .../{sim => }/bfin/c_dsp32shift_signbits_rl.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_vmax.s | 0 .../{sim => }/bfin/c_dsp32shift_vmaxvmax.s | 0 .../{sim => }/bfin/c_dsp32shiftim_a0alr.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shiftim_af.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shiftim_af_s.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahalf_ln.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahalf_ln_s.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahalf_lp.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahalf_lp_s.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahalf_rn.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahalf_rn_s.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahalf_rp.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahalf_rp_s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahh.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahh_s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shiftim_amix.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lf.s | 0 .../{sim => }/bfin/c_dsp32shiftim_lhalf_ln.s | 0 .../{sim => }/bfin/c_dsp32shiftim_lhalf_lp.s | 0 .../{sim => }/bfin/c_dsp32shiftim_lhalf_rn.s | 0 .../{sim => }/bfin/c_dsp32shiftim_lhalf_rp.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhh.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lmix.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shiftim_rot.s | 0 sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_i.s | 0 sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_ipp.s | 0 .../{sim => }/bfin/c_dspldst_ld_dr_ippm.s | 0 sim/testsuite/{sim => }/bfin/c_dspldst_ld_drhi_i.s | 0 .../{sim => }/bfin/c_dspldst_ld_drhi_ipp.s | 0 sim/testsuite/{sim => }/bfin/c_dspldst_ld_drlo_i.s | 0 .../{sim => }/bfin/c_dspldst_ld_drlo_ipp.s | 0 sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_i.s | 0 sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_ipp.s | 0 .../{sim => }/bfin/c_dspldst_st_dr_ippm.s | 0 sim/testsuite/{sim => }/bfin/c_dspldst_st_drhi_i.s | 0 .../{sim => }/bfin/c_dspldst_st_drhi_ipp.s | 0 sim/testsuite/{sim => }/bfin/c_dspldst_st_drlo_i.s | 0 .../{sim => }/bfin/c_dspldst_st_drlo_ipp.s | 0 sim/testsuite/{sim => }/bfin/c_except_illopcode.S | 0 sim/testsuite/{sim => }/bfin/c_except_sys_sstep.S | 0 sim/testsuite/{sim => }/bfin/c_except_user_mode.S | 0 sim/testsuite/{sim => }/bfin/c_interr_disable.S | 0 .../{sim => }/bfin/c_interr_disable_enable.S | 0 sim/testsuite/{sim => }/bfin/c_interr_excpt.S | 0 .../{sim => }/bfin/c_interr_loopsetup_stld.S | 0 sim/testsuite/{sim => }/bfin/c_interr_nested.S | 0 sim/testsuite/{sim => }/bfin/c_interr_nmi.S | 0 sim/testsuite/{sim => }/bfin/c_interr_pending.S | 0 sim/testsuite/{sim => }/bfin/c_interr_pending_2.S | 0 sim/testsuite/{sim => }/bfin/c_interr_timer.S | 0 .../{sim => }/bfin/c_interr_timer_reload.S | 0 .../{sim => }/bfin/c_interr_timer_tcount.S | 0 .../{sim => }/bfin/c_interr_timer_tscale.S | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_drhi.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_drlo.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_dr.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_ibml.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_pr.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_dr.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_ibml.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_pr.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_dr.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_ibml.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_pr.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_lzhi_dr.s | 0 .../{sim => }/bfin/c_ldimmhalf_lzhi_ibml.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_lzhi_pr.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_pibml.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_b.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_b.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_xb.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_xh.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_b.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_xb.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_xh.s | 0 .../{sim => }/bfin/c_ldst_ld_d_p_ppmm_hbx.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_xb.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_xh.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_p_p.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_p_p_mm.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_p_p_pp.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_b.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_mm.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_mm_b.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_mm_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_pp.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_pp_b.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_pp_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_p.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_p_mm.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_p_pp.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_b.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_xb.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_xh.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_preg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dr_b.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dr_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_st_preg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstii_ld_dr_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldstii_ld_dr_xh.s | 0 sim/testsuite/{sim => }/bfin/c_ldstii_ld_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstii_ld_preg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstii_st_dr_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldstii_st_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstii_st_preg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstiifp_ld_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstiifp_ld_preg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstiifp_st_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstiifp_st_preg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_dr_hi.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_dr_lo.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_h_xh.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_lohi.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_st_dr_hi.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_st_dr_lo.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_st_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_st_lohi.s | 0 sim/testsuite/{sim => }/bfin/c_linkage.s | 0 .../{sim => }/bfin/c_logi2op_alshft_mix.s | 0 .../{sim => }/bfin/c_logi2op_arith_shft.s | 0 sim/testsuite/{sim => }/bfin/c_logi2op_bitclr.s | 0 sim/testsuite/{sim => }/bfin/c_logi2op_bitset.s | 0 sim/testsuite/{sim => }/bfin/c_logi2op_bittgl.s | 0 sim/testsuite/{sim => }/bfin/c_logi2op_bittst.s | 0 .../{sim => }/bfin/c_logi2op_log_l_shft.s | 0 .../{sim => }/bfin/c_logi2op_log_l_shft_astat.S | 0 .../{sim => }/bfin/c_logi2op_log_r_shft.s | 0 .../{sim => }/bfin/c_logi2op_log_r_shft_astat.S | 0 sim/testsuite/{sim => }/bfin/c_logi2op_nbittst.s | 0 sim/testsuite/{sim => }/bfin/c_loopsetup_nested.s | 0 .../{sim => }/bfin/c_loopsetup_nested_bot.s | 0 .../{sim => }/bfin/c_loopsetup_nested_prelc.s | 0 .../{sim => }/bfin/c_loopsetup_nested_top.s | 0 sim/testsuite/{sim => }/bfin/c_loopsetup_overlap.s | 0 .../{sim => }/bfin/c_loopsetup_preg_div2_lc0.s | 0 .../{sim => }/bfin/c_loopsetup_preg_div2_lc1.s | 0 .../{sim => }/bfin/c_loopsetup_preg_lc0.s | 0 .../{sim => }/bfin/c_loopsetup_preg_lc1.s | 0 .../{sim => }/bfin/c_loopsetup_preg_stld.s | 0 sim/testsuite/{sim => }/bfin/c_loopsetup_prelc.s | 0 .../{sim => }/bfin/c_loopsetup_topbotcntr.s | 0 sim/testsuite/{sim => }/bfin/c_mmr_interr_ctl.s | 0 sim/testsuite/{sim => }/bfin/c_mmr_loop.S | 0 .../{sim => }/bfin/c_mmr_loop_user_except.S | 0 .../{sim => }/bfin/c_mmr_ppop_illegal_adr.S | 0 .../{sim => }/bfin/c_mmr_ppopm_illegal_adr.S | 0 sim/testsuite/{sim => }/bfin/c_mmr_timer.S | 0 sim/testsuite/{sim => }/bfin/c_mode_supervisor.S | 0 sim/testsuite/{sim => }/bfin/c_mode_user.S | 0 .../{sim => }/bfin/c_mode_user_superivsor.S | 0 .../{sim => }/bfin/c_multi_issue_dsp_ld_ld.s | 0 .../{sim => }/bfin/c_multi_issue_dsp_ldst_1.s | 0 .../{sim => }/bfin/c_multi_issue_dsp_ldst_2.s | 0 .../{sim => }/bfin/c_progctrl_call_pcpr.s | 0 sim/testsuite/{sim => }/bfin/c_progctrl_call_pr.s | 0 .../{sim => }/bfin/c_progctrl_clisti_interr.S | 0 .../{sim => }/bfin/c_progctrl_csync_mmr.S | 0 .../{sim => }/bfin/c_progctrl_except_rtx.S | 0 sim/testsuite/{sim => }/bfin/c_progctrl_excpt.S | 0 .../{sim => }/bfin/c_progctrl_jump_pcpr.s | 0 sim/testsuite/{sim => }/bfin/c_progctrl_jump_pr.s | 0 sim/testsuite/{sim => }/bfin/c_progctrl_nop.s | 0 .../{sim => }/bfin/c_progctrl_raise_rt_i_n.S | 0 sim/testsuite/{sim => }/bfin/c_progctrl_rts.s | 0 sim/testsuite/{sim => }/bfin/c_ptr2op_pr_neg_pr.s | 0 sim/testsuite/{sim => }/bfin/c_ptr2op_pr_sft_2_1.s | 0 .../{sim => }/bfin/c_ptr2op_pr_shadd_1_2.s | 0 .../{sim => }/bfin/c_pushpopmultiple_dp.s | 0 .../{sim => }/bfin/c_pushpopmultiple_dp_pair.s | 0 .../{sim => }/bfin/c_pushpopmultiple_dreg.s | 0 .../{sim => }/bfin/c_pushpopmultiple_preg.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_acc_acc.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_dag_lz_dep.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_dr_acc_acc.s | 0 .../{sim => }/bfin/c_regmv_dr_dep_nostall.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_dr_dr.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_dr_imlb.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_dr_pr.s | 0 .../{sim => }/bfin/c_regmv_imlb_dep_nostall.s | 0 .../{sim => }/bfin/c_regmv_imlb_dep_stall.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_imlb_dr.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_imlb_imlb.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_imlb_pr.s | 0 .../{sim => }/bfin/c_regmv_pr_dep_nostall.s | 0 .../{sim => }/bfin/c_regmv_pr_dep_stall.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_pr_dr.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_pr_imlb.s | 0 sim/testsuite/{sim => }/bfin/c_regmv_pr_pr.s | 0 sim/testsuite/{sim => }/bfin/c_seq_ac_raise_mv.S | 0 .../{sim => }/bfin/c_seq_ac_raise_mv_ppop.S | 0 .../{sim => }/bfin/c_seq_ac_regmv_pushpop.S | 0 .../{sim => }/bfin/c_seq_dec_raise_pushpop.S | 0 .../{sim => }/bfin/c_seq_ex1_brcc_mv_pop.S | 0 .../{sim => }/bfin/c_seq_ex1_call_mv_pop.S | 0 sim/testsuite/{sim => }/bfin/c_seq_ex1_j_mv_pop.S | 0 .../{sim => }/bfin/c_seq_ex1_raise_brcc_mv_pop.S | 0 .../{sim => }/bfin/c_seq_ex1_raise_call_mv_pop.S | 0 .../{sim => }/bfin/c_seq_ex1_raise_j_mv_pop.S | 0 .../{sim => }/bfin/c_seq_ex2_brcc_mp_mv_pop.S | 0 sim/testsuite/{sim => }/bfin/c_seq_ex2_mmr_mvpop.S | 0 .../{sim => }/bfin/c_seq_ex2_mmrj_mvpop.S | 0 .../{sim => }/bfin/c_seq_ex2_raise_mmr_mvpop.S | 0 .../{sim => }/bfin/c_seq_ex2_raise_mmrj_mvpop.S | 0 .../{sim => }/bfin/c_seq_ex3_ls_brcc_mvp.S | 0 .../{sim => }/bfin/c_seq_ex3_ls_mmr_mvp.S | 0 .../{sim => }/bfin/c_seq_ex3_ls_mmrj_mvp.S | 0 .../{sim => }/bfin/c_seq_ex3_raise_ls_mmrj_mvp.S | 0 .../{sim => }/bfin/c_seq_wb_cs_lsmmrj_mvp.S | 0 .../{sim => }/bfin/c_seq_wb_raisecs_lsmmrj_mvp.S | 0 .../{sim => }/bfin/c_seq_wb_rti_lsmmrj_mvp.S | 0 .../{sim => }/bfin/c_seq_wb_rtn_lsmmrj_mvp.S | 0 .../{sim => }/bfin/c_seq_wb_rtx_lsmmrj_mvp.S | 0 sim/testsuite/{sim => }/bfin/c_ujump.s | 0 sim/testsuite/{sim => }/bfin/cc-alu.S | 0 sim/testsuite/{sim => }/bfin/cc-astat-bits.s | 0 sim/testsuite/{sim => }/bfin/cc0.s | 0 sim/testsuite/{sim => }/bfin/cc1.s | 0 sim/testsuite/{sim => }/bfin/cc5.S | 0 sim/testsuite/{sim => }/bfin/cec-exact-exception.S | 0 sim/testsuite/{sim => }/bfin/cec-ifetch.S | 0 sim/testsuite/{sim => }/bfin/cec-multi-pending.S | 0 sim/testsuite/{sim => }/bfin/cec-no-snen-reti.S | 0 .../{sim => }/bfin/cec-non-operating-env.s | 0 sim/testsuite/{sim => }/bfin/cec-raise-reti.S | 0 sim/testsuite/{sim => }/bfin/cec-snen-reti.S | 0 sim/testsuite/{sim => }/bfin/cec-syscfg-ssstep.S | 0 sim/testsuite/{sim => }/bfin/cec-system-call.S | 0 sim/testsuite/{sim => }/bfin/cir.s | 0 sim/testsuite/{sim => }/bfin/cir1.s | 0 sim/testsuite/{sim => }/bfin/cli-sti.s | 0 sim/testsuite/{sim => }/bfin/cmpacc.s | 0 sim/testsuite/{sim => }/bfin/cmpdreg.S | 0 sim/testsuite/{sim => }/bfin/compare.s | 0 sim/testsuite/{sim => }/bfin/conv_enc_gen.s | 0 sim/testsuite/{sim => }/bfin/cycles.s | 0 sim/testsuite/{sim => }/bfin/d0.s | 0 sim/testsuite/{sim => }/bfin/d1.s | 0 sim/testsuite/{sim => }/bfin/d2.s | 0 .../{sim => }/bfin/dbg_brprd_ntkn_src_kill.S | 0 .../{sim => }/bfin/dbg_brtkn_nprd_src_kill.S | 0 sim/testsuite/{sim => }/bfin/dbg_jmp_src_kill.S | 0 sim/testsuite/{sim => }/bfin/dbg_tr_basic.S | 0 sim/testsuite/{sim => }/bfin/dbg_tr_simplejp.S | 0 sim/testsuite/{sim => }/bfin/dbg_tr_tbuf0.S | 0 sim/testsuite/{sim => }/bfin/dbg_tr_umode.S | 0 .../{sim => }/bfin/disalnexcpt_implicit.S | 0 sim/testsuite/{sim => }/bfin/div0.s | 0 sim/testsuite/{sim => }/bfin/divq.s | 0 sim/testsuite/{sim => }/bfin/dotproduct.s | 0 sim/testsuite/{sim => }/bfin/dotproduct2.s | 0 sim/testsuite/{sim => }/bfin/double_prec_mult.s | 0 sim/testsuite/{sim => }/bfin/dsp_a4.s | 0 sim/testsuite/{sim => }/bfin/dsp_a7.s | 0 sim/testsuite/{sim => }/bfin/dsp_a8.s | 0 sim/testsuite/{sim => }/bfin/dsp_d0.s | 0 sim/testsuite/{sim => }/bfin/dsp_d1.s | 0 sim/testsuite/{sim => }/bfin/dsp_neg.S | 0 sim/testsuite/{sim => }/bfin/dsp_s1.s | 0 sim/testsuite/{sim => }/bfin/e0.s | 0 sim/testsuite/{sim => }/bfin/edn_snafu.s | 0 sim/testsuite/{sim => }/bfin/eu_dsp32mac_s.s | 0 sim/testsuite/{sim => }/bfin/events.s | 0 sim/testsuite/{sim => }/bfin/f221.s | 0 sim/testsuite/{sim => }/bfin/fact.s | 0 sim/testsuite/{sim => }/bfin/fir.s | 0 sim/testsuite/{sim => }/bfin/fsm.s | 0 sim/testsuite/{sim => }/bfin/greg2.s | 0 sim/testsuite/{sim => }/bfin/hwloop-bits.S | 0 sim/testsuite/{sim => }/bfin/hwloop-branch-in.s | 0 sim/testsuite/{sim => }/bfin/hwloop-branch-out.s | 0 sim/testsuite/{sim => }/bfin/hwloop-lt-bits.s | 0 sim/testsuite/{sim => }/bfin/hwloop-nested.s | 0 sim/testsuite/{sim => }/bfin/i0.s | 0 sim/testsuite/{sim => }/bfin/iir.s | 0 sim/testsuite/{sim => }/bfin/issue103.s | 0 sim/testsuite/{sim => }/bfin/issue109.s | 0 sim/testsuite/{sim => }/bfin/issue112.s | 0 sim/testsuite/{sim => }/bfin/issue113.s | 0 sim/testsuite/{sim => }/bfin/issue117.s | 0 sim/testsuite/{sim => }/bfin/issue118.s | 0 sim/testsuite/{sim => }/bfin/issue119.s | 0 sim/testsuite/{sim => }/bfin/issue121.s | 0 sim/testsuite/{sim => }/bfin/issue123.s | 0 sim/testsuite/{sim => }/bfin/issue124.s | 0 sim/testsuite/{sim => }/bfin/issue125.s | 0 sim/testsuite/{sim => }/bfin/issue126.s | 0 sim/testsuite/{sim => }/bfin/issue127.s | 0 sim/testsuite/{sim => }/bfin/issue129.s | 0 sim/testsuite/{sim => }/bfin/issue139.S | 0 sim/testsuite/{sim => }/bfin/issue140.S | 0 sim/testsuite/{sim => }/bfin/issue142.s | 0 sim/testsuite/{sim => }/bfin/issue144.s | 0 sim/testsuite/{sim => }/bfin/issue146.S | 0 sim/testsuite/{sim => }/bfin/issue175.s | 0 sim/testsuite/{sim => }/bfin/issue205.s | 0 sim/testsuite/{sim => }/bfin/issue257.s | 0 sim/testsuite/{sim => }/bfin/issue272.S | 0 sim/testsuite/{sim => }/bfin/issue83.s | 0 sim/testsuite/{sim => }/bfin/issue89.s | 0 sim/testsuite/{sim => }/bfin/l0.s | 0 sim/testsuite/{sim => }/bfin/l0shift.s | 0 sim/testsuite/{sim => }/bfin/l2_loop.s | 0 sim/testsuite/{sim => }/bfin/link-2.s | 0 sim/testsuite/{sim => }/bfin/link.s | 0 sim/testsuite/{sim => }/bfin/lmu_cplb_multiple0.S | 0 sim/testsuite/{sim => }/bfin/lmu_cplb_multiple1.S | 0 sim/testsuite/{sim => }/bfin/lmu_excpt_align.S | 0 sim/testsuite/{sim => }/bfin/lmu_excpt_default.S | 0 sim/testsuite/{sim => }/bfin/lmu_excpt_illaddr.S | 0 sim/testsuite/{sim => }/bfin/lmu_excpt_prot0.S | 0 sim/testsuite/{sim => }/bfin/lmu_excpt_prot1.S | 0 sim/testsuite/{sim => }/bfin/load.s | 0 sim/testsuite/{sim => }/bfin/logic.s | 0 sim/testsuite/{sim => }/bfin/loop_snafu.s | 0 sim/testsuite/{sim => }/bfin/loop_strncpy.s | 0 sim/testsuite/{sim => }/bfin/lp0.s | 0 sim/testsuite/{sim => }/bfin/lp1.s | 0 sim/testsuite/{sim => }/bfin/lsetup.s | 0 sim/testsuite/{sim => }/bfin/m0boundary.s | 0 sim/testsuite/{sim => }/bfin/m1.S | 0 sim/testsuite/{sim => }/bfin/m10.s | 0 sim/testsuite/{sim => }/bfin/m11.s | 0 sim/testsuite/{sim => }/bfin/m12.s | 0 sim/testsuite/{sim => }/bfin/m13.s | 0 sim/testsuite/{sim => }/bfin/m14.s | 0 sim/testsuite/{sim => }/bfin/m15.s | 0 sim/testsuite/{sim => }/bfin/m16.s | 0 sim/testsuite/{sim => }/bfin/m17.s | 0 sim/testsuite/{sim => }/bfin/m2.s | 0 sim/testsuite/{sim => }/bfin/m3.s | 0 sim/testsuite/{sim => }/bfin/m4.s | 0 sim/testsuite/{sim => }/bfin/m5.s | 0 sim/testsuite/{sim => }/bfin/m6.s | 0 sim/testsuite/{sim => }/bfin/m7.s | 0 sim/testsuite/{sim => }/bfin/m8.s | 0 sim/testsuite/{sim => }/bfin/m9.s | 0 sim/testsuite/{sim => }/bfin/mac2halfreg.S | 0 sim/testsuite/{sim => }/bfin/math.s | 0 sim/testsuite/{sim => }/bfin/max_min_flags.s | 0 sim/testsuite/{sim => }/bfin/mc_s2.s | 0 .../{sim => }/bfin/mdma-32bit-1d-neg-count.c | 0 sim/testsuite/{sim => }/bfin/mdma-32bit-1d.c | 0 .../{sim => }/bfin/mdma-8bit-1d-neg-count.c | 0 sim/testsuite/{sim => }/bfin/mdma-8bit-1d.c | 0 sim/testsuite/{sim => }/bfin/mdma-skel.h | 0 sim/testsuite/{sim => }/bfin/mem3.s | 0 sim/testsuite/{sim => }/bfin/mmr-exception.s | 0 sim/testsuite/{sim => }/bfin/move.s | 0 sim/testsuite/{sim => }/bfin/msa_acp_5.10.S | 0 sim/testsuite/{sim => }/bfin/msa_acp_5.12_1.S | 0 sim/testsuite/{sim => }/bfin/msa_acp_5.12_2.S | 0 sim/testsuite/{sim => }/bfin/msa_acp_5_10.s | 0 sim/testsuite/{sim => }/bfin/mult.s | 0 sim/testsuite/{sim => }/bfin/neg-2.S | 0 sim/testsuite/{sim => }/bfin/neg-3.S | 0 sim/testsuite/{sim => }/bfin/neg.S | 0 sim/testsuite/{sim => }/bfin/nshift.s | 0 sim/testsuite/{sim => }/bfin/pr.s | 0 sim/testsuite/{sim => }/bfin/push-pop-multiple.s | 0 sim/testsuite/{sim => }/bfin/push-pop.s | 0 sim/testsuite/{sim => }/bfin/pushpopreg_1.s | 0 sim/testsuite/{sim => }/bfin/quadaddsub.s | 0 sim/testsuite/{sim => }/bfin/random_0001.s | 0 sim/testsuite/{sim => }/bfin/random_0002.S | 0 sim/testsuite/{sim => }/bfin/random_0003.S | 0 sim/testsuite/{sim => }/bfin/random_0004.S | 0 sim/testsuite/{sim => }/bfin/random_0005.S | 0 sim/testsuite/{sim => }/bfin/random_0006.S | 0 sim/testsuite/{sim => }/bfin/random_0007.S | 0 sim/testsuite/{sim => }/bfin/random_0008.S | 0 sim/testsuite/{sim => }/bfin/random_0009.S | 0 sim/testsuite/{sim => }/bfin/random_0010.S | 0 sim/testsuite/{sim => }/bfin/random_0011.S | 0 sim/testsuite/{sim => }/bfin/random_0012.S | 0 sim/testsuite/{sim => }/bfin/random_0013.S | 0 sim/testsuite/{sim => }/bfin/random_0014.S | 0 sim/testsuite/{sim => }/bfin/random_0015.S | 0 sim/testsuite/{sim => }/bfin/random_0016.S | 0 sim/testsuite/{sim => }/bfin/random_0017.S | 0 sim/testsuite/{sim => }/bfin/random_0018.S | 0 sim/testsuite/{sim => }/bfin/random_0019.S | 0 sim/testsuite/{sim => }/bfin/random_0020.S | 0 sim/testsuite/{sim => }/bfin/random_0021.S | 0 sim/testsuite/{sim => }/bfin/random_0022.S | 0 sim/testsuite/{sim => }/bfin/random_0023.S | 0 sim/testsuite/{sim => }/bfin/random_0024.S | 0 sim/testsuite/{sim => }/bfin/random_0025.S | 0 sim/testsuite/{sim => }/bfin/random_0026.S | 0 sim/testsuite/{sim => }/bfin/random_0027.S | 0 sim/testsuite/{sim => }/bfin/random_0028.S | 0 sim/testsuite/{sim => }/bfin/random_0029.S | 0 sim/testsuite/{sim => }/bfin/random_0030.S | 0 sim/testsuite/{sim => }/bfin/random_0031.S | 0 sim/testsuite/{sim => }/bfin/random_0032.S | 0 sim/testsuite/{sim => }/bfin/random_0033.S | 0 sim/testsuite/{sim => }/bfin/random_0034.S | 0 sim/testsuite/{sim => }/bfin/random_0035.S | 0 sim/testsuite/{sim => }/bfin/random_0036.S | 0 sim/testsuite/{sim => }/bfin/random_0037.S | 0 sim/testsuite/{sim => }/bfin/run-tests.sh | 0 sim/testsuite/{sim => }/bfin/s0.s | 0 sim/testsuite/{sim => }/bfin/s1.s | 0 sim/testsuite/{sim => }/bfin/s10.s | 0 sim/testsuite/{sim => }/bfin/s11.s | 0 sim/testsuite/{sim => }/bfin/s12.s | 0 sim/testsuite/{sim => }/bfin/s13.s | 0 sim/testsuite/{sim => }/bfin/s14.s | 0 sim/testsuite/{sim => }/bfin/s15.s | 0 sim/testsuite/{sim => }/bfin/s16.s | 0 sim/testsuite/{sim => }/bfin/s17.s | 0 sim/testsuite/{sim => }/bfin/s18.s | 0 sim/testsuite/{sim => }/bfin/s19.s | 0 sim/testsuite/{sim => }/bfin/s2.s | 0 sim/testsuite/{sim => }/bfin/s20.s | 0 sim/testsuite/bfin/s21.s | 297 + sim/testsuite/{sim => }/bfin/s3.s | 0 sim/testsuite/{sim => }/bfin/s30.s | 0 sim/testsuite/{sim => }/bfin/s4.s | 0 sim/testsuite/{sim => }/bfin/s5.s | 0 sim/testsuite/{sim => }/bfin/s6.s | 0 sim/testsuite/{sim => }/bfin/s7.s | 0 sim/testsuite/{sim => }/bfin/s8.s | 0 sim/testsuite/{sim => }/bfin/s9.s | 0 sim/testsuite/{sim => }/bfin/saatest.s | 0 sim/testsuite/{sim => }/bfin/se_all16bitopcodes.S | 0 sim/testsuite/{sim => }/bfin/se_all32bitopcodes.S | 0 .../{sim => }/bfin/se_all32bitopcodes.lds | 0 .../{sim => }/bfin/se_all64bitg0opcodes.S | 0 .../{sim => }/bfin/se_all64bitg1opcodes.S | 0 .../{sim => }/bfin/se_all64bitg2opcodes.S | 0 sim/testsuite/{sim => }/bfin/se_allopcodes.h | 0 sim/testsuite/{sim => }/bfin/se_brtarget_stall.S | 0 sim/testsuite/{sim => }/bfin/se_bug_ui.S | 0 sim/testsuite/{sim => }/bfin/se_bug_ui2.S | 0 sim/testsuite/{sim => }/bfin/se_bug_ui3.S | 0 sim/testsuite/{sim => }/bfin/se_cc2stat_haz.S | 0 sim/testsuite/{sim => }/bfin/se_cc_kill.S | 0 sim/testsuite/{sim => }/bfin/se_cof.S | 0 sim/testsuite/{sim => }/bfin/se_event_quad.S | 0 .../{sim => }/bfin/se_excpt_dagprotviol.S | 0 sim/testsuite/{sim => }/bfin/se_excpt_ifprotviol.S | 0 sim/testsuite/{sim => }/bfin/se_excpt_ssstep.S | 0 .../{sim => }/bfin/se_illegalcombination.S | 0 sim/testsuite/{sim => }/bfin/se_kill_wbbr.S | 0 sim/testsuite/{sim => }/bfin/se_kills2.S | 0 sim/testsuite/{sim => }/bfin/se_loop_disable.S | 0 sim/testsuite/{sim => }/bfin/se_loop_kill.S | 0 sim/testsuite/{sim => }/bfin/se_loop_kill_01.S | 0 sim/testsuite/{sim => }/bfin/se_loop_kill_dcr.S | 0 sim/testsuite/{sim => }/bfin/se_loop_kill_dcr_01.S | 0 sim/testsuite/{sim => }/bfin/se_loop_lr.S | 0 sim/testsuite/{sim => }/bfin/se_loop_mv2lb_stall.S | 0 sim/testsuite/{sim => }/bfin/se_loop_mv2lc.S | 0 sim/testsuite/{sim => }/bfin/se_loop_mv2lc_stall.S | 0 sim/testsuite/{sim => }/bfin/se_loop_mv2lt_stall.S | 0 sim/testsuite/{sim => }/bfin/se_loop_nest_ppm.S | 0 sim/testsuite/{sim => }/bfin/se_loop_nest_ppm_1.S | 0 sim/testsuite/{sim => }/bfin/se_loop_nest_ppm_2.S | 0 sim/testsuite/{sim => }/bfin/se_loop_ppm.S | 0 sim/testsuite/{sim => }/bfin/se_loop_ppm_1.S | 0 sim/testsuite/{sim => }/bfin/se_loop_ppm_int.S | 0 sim/testsuite/{sim => }/bfin/se_lsetup_kill.S | 0 sim/testsuite/{sim => }/bfin/se_misaligned_fetch.S | 0 sim/testsuite/{sim => }/bfin/se_more_ret_haz.S | 0 sim/testsuite/{sim => }/bfin/se_mv2lp.S | 0 sim/testsuite/{sim => }/bfin/se_oneins_zoff.S | 0 sim/testsuite/{sim => }/bfin/se_popkill.S | 0 sim/testsuite/{sim => }/bfin/se_regmv_usp_sysreg.S | 0 sim/testsuite/{sim => }/bfin/se_rets_hazard.s | 0 sim/testsuite/{sim => }/bfin/se_rts_rti.S | 0 .../{sim => }/bfin/se_ssstep_dagprotviol.S | 0 sim/testsuite/{sim => }/bfin/se_ssync.S | 0 sim/testsuite/{sim => }/bfin/se_stall_if2.S | 0 .../{sim => }/bfin/se_undefinedinstruction1.S | 0 .../{sim => }/bfin/se_undefinedinstruction2.S | 0 .../{sim => }/bfin/se_undefinedinstruction3.S | 0 .../{sim => }/bfin/se_undefinedinstruction4.S | 0 .../{sim => }/bfin/se_usermode_protviol.S | 0 sim/testsuite/{sim => }/bfin/seqstat.s | 0 sim/testsuite/{sim => }/bfin/sign.s | 0 sim/testsuite/{sim => }/bfin/simple0.s | 0 sim/testsuite/{sim => }/bfin/sri.s | 0 sim/testsuite/{sim => }/bfin/stk.s | 0 sim/testsuite/{sim => }/bfin/stk2.s | 0 sim/testsuite/{sim => }/bfin/stk3.s | 0 sim/testsuite/{sim => }/bfin/stk4.s | 0 sim/testsuite/{sim => }/bfin/stk5.s | 0 sim/testsuite/{sim => }/bfin/stk6.s | 0 sim/testsuite/{sim => }/bfin/syscfg.s | 0 sim/testsuite/{sim => }/bfin/tar10622.s | 0 sim/testsuite/{sim => }/bfin/test-dma.h | 0 sim/testsuite/{sim => }/bfin/test.h | 0 sim/testsuite/{sim => }/bfin/testset.s | 0 sim/testsuite/{sim => }/bfin/testset2.s | 0 sim/testsuite/{sim => }/bfin/testutils.inc | 0 sim/testsuite/{sim => }/bfin/unlink.S | 0 sim/testsuite/{sim => }/bfin/up0.s | 0 sim/testsuite/{sim => }/bfin/usp.S | 0 sim/testsuite/{sim => }/bfin/vec-abs-2.S | 0 sim/testsuite/{sim => }/bfin/vec-abs-3.S | 0 sim/testsuite/{sim => }/bfin/vec-abs.S | 0 sim/testsuite/{sim => }/bfin/vec-neg-2.S | 0 sim/testsuite/{sim => }/bfin/vec-neg-3.S | 0 sim/testsuite/{sim => }/bfin/vec-neg.S | 0 sim/testsuite/{sim => }/bfin/vecadd.s | 0 sim/testsuite/{sim => }/bfin/vit_max.s | 0 sim/testsuite/{sim => }/bfin/vit_max2.s | 0 sim/testsuite/{sim => }/bfin/viterbi2.s | 0 sim/testsuite/{sim => }/bfin/wtf.s | 0 sim/testsuite/{sim => }/bfin/x1.s | 0 sim/testsuite/{sim => }/bfin/zcall.s | 0 sim/testsuite/{sim => }/bfin/zeroflagrnd.s | 0 sim/testsuite/{sim => }/bpf/ChangeLog | 0 sim/testsuite/{sim => }/bpf/allinsn.exp | 0 sim/testsuite/{sim => }/bpf/alu.s | 0 sim/testsuite/{sim => }/bpf/alu32.s | 0 sim/testsuite/{sim => }/bpf/endbe.s | 0 sim/testsuite/{sim => }/bpf/endle.s | 0 sim/testsuite/{sim => }/bpf/jmp.s | 0 sim/testsuite/{sim => }/bpf/jmp32.s | 0 sim/testsuite/{sim => }/bpf/ldabs.s | 0 sim/testsuite/{sim => }/bpf/mem.s | 0 sim/testsuite/{sim => }/bpf/mov.s | 0 sim/testsuite/{sim => }/bpf/testutils.inc | 0 sim/testsuite/{sim => }/bpf/xadd.s | 0 sim/testsuite/{sim => }/cr16/ChangeLog | 0 sim/testsuite/{sim => }/cr16/addb.cgs | 0 sim/testsuite/{sim => }/cr16/addd.cgs | 0 sim/testsuite/{sim => }/cr16/addi.cgs | 0 sim/testsuite/{sim => }/cr16/addw.cgs | 0 sim/testsuite/{sim => }/cr16/allinsn.exp | 0 sim/testsuite/{sim => }/cr16/andb.cgs | 0 sim/testsuite/{sim => }/cr16/andd.cgs | 0 sim/testsuite/{sim => }/cr16/andw.cgs | 0 sim/testsuite/{sim => }/cr16/ashub.cgs | 0 sim/testsuite/{sim => }/cr16/ashub_i.cgs | 0 sim/testsuite/{sim => }/cr16/ashud.cgs | 0 sim/testsuite/{sim => }/cr16/ashud_i.cgs | 0 sim/testsuite/{sim => }/cr16/ashuw.cgs | 0 sim/testsuite/{sim => }/cr16/ashuw_i.cgs | 0 sim/testsuite/{sim => }/cr16/bal1_24.cgs | 0 sim/testsuite/{sim => }/cr16/bal2_24.cgs | 0 sim/testsuite/{sim => }/cr16/bcc.cgs | 0 sim/testsuite/{sim => }/cr16/bcs.cgs | 0 sim/testsuite/{sim => }/cr16/beq.cgs | 0 sim/testsuite/{sim => }/cr16/beq0b.cgs | 0 sim/testsuite/{sim => }/cr16/beq0w.cgs | 0 sim/testsuite/{sim => }/cr16/bge.cgs | 0 sim/testsuite/{sim => }/cr16/bgt.cgs | 0 sim/testsuite/{sim => }/cr16/bhi.cgs | 0 sim/testsuite/{sim => }/cr16/bhs.cgs | 0 sim/testsuite/{sim => }/cr16/bht.cgs | 0 sim/testsuite/{sim => }/cr16/blo.cgs | 0 sim/testsuite/{sim => }/cr16/bls.cgs | 0 sim/testsuite/{sim => }/cr16/blt.cgs | 0 sim/testsuite/{sim => }/cr16/bne.cgs | 0 sim/testsuite/{sim => }/cr16/bne0b.cgs | 0 sim/testsuite/{sim => }/cr16/bne0w.cgs | 0 sim/testsuite/{sim => }/cr16/br.cgs | 0 sim/testsuite/{sim => }/cr16/cbitb.cgs | 0 sim/testsuite/{sim => }/cr16/cbitw.cgs | 0 sim/testsuite/{sim => }/cr16/cmpb.cgs | 0 sim/testsuite/{sim => }/cr16/cmpb_i.cgs | 0 sim/testsuite/{sim => }/cr16/cmpd.cgs | 0 sim/testsuite/{sim => }/cr16/cmpd_i.cgs | 0 sim/testsuite/{sim => }/cr16/cmpi.cgs | 0 sim/testsuite/{sim => }/cr16/cmpw.cgs | 0 sim/testsuite/{sim => }/cr16/cmpw_i.cgs | 0 sim/testsuite/{sim => }/cr16/excp.cgs | 0 sim/testsuite/{sim => }/cr16/hello.ms | 0 sim/testsuite/{sim => }/cr16/hw-trap.ms | 0 sim/testsuite/{sim => }/cr16/jal.cgs | 0 sim/testsuite/{sim => }/cr16/jcc.cgs | 0 sim/testsuite/{sim => }/cr16/jcs.cgs | 0 sim/testsuite/{sim => }/cr16/jeq.cgs | 0 sim/testsuite/{sim => }/cr16/jfc.cgs | 0 sim/testsuite/{sim => }/cr16/jfs.cgs | 0 sim/testsuite/{sim => }/cr16/jge.cgs | 0 sim/testsuite/{sim => }/cr16/jgt.cgs | 0 sim/testsuite/{sim => }/cr16/jhi.cgs | 0 sim/testsuite/{sim => }/cr16/jhs.cgs | 0 sim/testsuite/{sim => }/cr16/jlo.cgs | 0 sim/testsuite/{sim => }/cr16/jls.cgs | 0 sim/testsuite/{sim => }/cr16/jlt.cgs | 0 sim/testsuite/{sim => }/cr16/jne.cgs | 0 sim/testsuite/{sim => }/cr16/jump.cgs | 0 sim/testsuite/{sim => }/cr16/loadb.cgs | 0 sim/testsuite/{sim => }/cr16/loadd.cgs | 0 sim/testsuite/{sim => }/cr16/loadm.cgs | 0 sim/testsuite/{sim => }/cr16/loadmp.cgs | 0 sim/testsuite/{sim => }/cr16/loadw.cgs | 0 sim/testsuite/{sim => }/cr16/lpr-spr.cgs | 0 sim/testsuite/{sim => }/cr16/lprd-sprd.cgs | 0 sim/testsuite/{sim => }/cr16/lshb.cgs | 0 sim/testsuite/{sim => }/cr16/lshb_i.cgs | 0 sim/testsuite/{sim => }/cr16/lshd.cgs | 0 sim/testsuite/{sim => }/cr16/lshd_i.cgs | 0 sim/testsuite/{sim => }/cr16/lshw.cgs | 0 sim/testsuite/{sim => }/cr16/lshw_i.cgs | 0 sim/testsuite/{sim => }/cr16/macqw.cgs | 0 sim/testsuite/{sim => }/cr16/macsw.cgs | 0 sim/testsuite/{sim => }/cr16/macuw.cgs | 0 sim/testsuite/{sim => }/cr16/misc.exp | 0 sim/testsuite/{sim => }/cr16/movb.cgs | 0 sim/testsuite/{sim => }/cr16/movd.cgs | 0 sim/testsuite/{sim => }/cr16/movw.cgs | 0 sim/testsuite/{sim => }/cr16/movxb.cgs | 0 sim/testsuite/{sim => }/cr16/movxw.cgs | 0 sim/testsuite/{sim => }/cr16/movzb.cgs | 0 sim/testsuite/{sim => }/cr16/movzw.cgs | 0 sim/testsuite/{sim => }/cr16/mulb.cgs | 0 sim/testsuite/{sim => }/cr16/mulsb.cgs | 0 sim/testsuite/{sim => }/cr16/mulsw.cgs | 0 sim/testsuite/{sim => }/cr16/muluw.cgs | 0 sim/testsuite/{sim => }/cr16/mulw.cgs | 0 sim/testsuite/{sim => }/cr16/nop.cgs | 0 sim/testsuite/{sim => }/cr16/orb.cgs | 0 sim/testsuite/{sim => }/cr16/ord.cgs | 0 sim/testsuite/{sim => }/cr16/orw.cgs | 0 sim/testsuite/{sim => }/cr16/pop1.cgs | 0 sim/testsuite/{sim => }/cr16/pop2.cgs | 0 sim/testsuite/{sim => }/cr16/pop3.cgs | 0 sim/testsuite/{sim => }/cr16/popret1.cgs | 0 sim/testsuite/{sim => }/cr16/popret2.cgs | 0 sim/testsuite/{sim => }/cr16/popret3.cgs | 0 sim/testsuite/{sim => }/cr16/push1.cgs | 0 sim/testsuite/{sim => }/cr16/push2.cgs | 0 sim/testsuite/{sim => }/cr16/push3.cgs | 0 sim/testsuite/{sim => }/cr16/sbitb.cgs | 0 sim/testsuite/{sim => }/cr16/sbitw.cgs | 0 sim/testsuite/{sim => }/cr16/scc.cgs | 0 sim/testsuite/{sim => }/cr16/scs.cgs | 0 sim/testsuite/{sim => }/cr16/seq.cgs | 0 sim/testsuite/{sim => }/cr16/sfc.cgs | 0 sim/testsuite/{sim => }/cr16/sfs.cgs | 0 sim/testsuite/{sim => }/cr16/sge.cgs | 0 sim/testsuite/{sim => }/cr16/sgt.cgs | 0 sim/testsuite/{sim => }/cr16/shi.cgs | 0 sim/testsuite/{sim => }/cr16/shs.cgs | 0 sim/testsuite/{sim => }/cr16/slo.cgs | 0 sim/testsuite/{sim => }/cr16/sls.cgs | 0 sim/testsuite/{sim => }/cr16/slt.cgs | 0 sim/testsuite/{sim => }/cr16/sne.cgs | 0 sim/testsuite/{sim => }/cr16/storb.cgs | 0 sim/testsuite/{sim => }/cr16/stord.cgs | 0 sim/testsuite/{sim => }/cr16/storw.cgs | 0 sim/testsuite/{sim => }/cr16/subb.cgs | 0 sim/testsuite/{sim => }/cr16/subd.cgs | 0 sim/testsuite/{sim => }/cr16/subi.cgs | 0 sim/testsuite/{sim => }/cr16/subw.cgs | 0 sim/testsuite/{sim => }/cr16/tbit.cgs | 0 sim/testsuite/{sim => }/cr16/tbitb.cgs | 0 sim/testsuite/{sim => }/cr16/tbitw.cgs | 0 sim/testsuite/{sim => }/cr16/testutils.inc | 0 sim/testsuite/{sim => }/cr16/uread16.ms | 0 sim/testsuite/{sim => }/cr16/uread32.ms | 0 sim/testsuite/{sim => }/cr16/xorb.cgs | 0 sim/testsuite/{sim => }/cr16/xord.cgs | 0 sim/testsuite/{sim => }/cr16/xorw.cgs | 0 sim/testsuite/{sim => }/cris/ChangeLog | 0 sim/testsuite/{sim => }/cris/asm/abs.ms | 0 sim/testsuite/{sim => }/cris/asm/addc.ms | 0 sim/testsuite/{sim => }/cris/asm/addcpc.ms | 0 sim/testsuite/{sim => }/cris/asm/addcv32c.ms | 0 sim/testsuite/{sim => }/cris/asm/addcv32m.ms | 0 sim/testsuite/{sim => }/cris/asm/addcv32r.ms | 0 sim/testsuite/{sim => }/cris/asm/addi.ms | 0 sim/testsuite/{sim => }/cris/asm/addiv32.ms | 0 sim/testsuite/{sim => }/cris/asm/addm.ms | 0 sim/testsuite/{sim => }/cris/asm/addoc.ms | 0 sim/testsuite/{sim => }/cris/asm/addom.ms | 0 sim/testsuite/{sim => }/cris/asm/addoq.ms | 0 sim/testsuite/{sim => }/cris/asm/addq.ms | 0 sim/testsuite/{sim => }/cris/asm/addqpc.ms | 0 sim/testsuite/{sim => }/cris/asm/addr.ms | 0 sim/testsuite/{sim => }/cris/asm/addswpc.ms | 0 sim/testsuite/{sim => }/cris/asm/addxc.ms | 0 sim/testsuite/{sim => }/cris/asm/addxm.ms | 0 sim/testsuite/{sim => }/cris/asm/addxr.ms | 0 sim/testsuite/{sim => }/cris/asm/andc.ms | 0 sim/testsuite/{sim => }/cris/asm/andm.ms | 0 sim/testsuite/{sim => }/cris/asm/andq.ms | 0 sim/testsuite/{sim => }/cris/asm/andr.ms | 0 sim/testsuite/{sim => }/cris/asm/asm.exp | 0 sim/testsuite/{sim => }/cris/asm/asr.ms | 0 sim/testsuite/{sim => }/cris/asm/ba.ms | 0 sim/testsuite/{sim => }/cris/asm/badarch1.ms | 0 sim/testsuite/{sim => }/cris/asm/bare1.ms | 0 sim/testsuite/{sim => }/cris/asm/bare2.ms | 0 sim/testsuite/{sim => }/cris/asm/bare3.ms | 0 sim/testsuite/{sim => }/cris/asm/bas.ms | 0 sim/testsuite/{sim => }/cris/asm/bccb.ms | 0 sim/testsuite/{sim => }/cris/asm/bdapc.ms | 0 sim/testsuite/{sim => }/cris/asm/bdapm.ms | 0 sim/testsuite/{sim => }/cris/asm/bdapq.ms | 0 sim/testsuite/{sim => }/cris/asm/bdapqpc.ms | 0 sim/testsuite/{sim => }/cris/asm/biap.ms | 0 sim/testsuite/{sim => }/cris/asm/boundc.ms | 0 sim/testsuite/{sim => }/cris/asm/boundm.ms | 0 sim/testsuite/{sim => }/cris/asm/boundmv32.ms | 0 sim/testsuite/{sim => }/cris/asm/boundr.ms | 0 sim/testsuite/{sim => }/cris/asm/break.ms | 0 sim/testsuite/{sim => }/cris/asm/btst.ms | 0 sim/testsuite/{sim => }/cris/asm/ccr-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/ccs-v32.ms | 0 sim/testsuite/{sim => }/cris/asm/clearfv10.ms | 0 sim/testsuite/{sim => }/cris/asm/clearfv32.ms | 0 sim/testsuite/{sim => }/cris/asm/clrjmp1.ms | 0 sim/testsuite/{sim => }/cris/asm/cmpc.ms | 0 sim/testsuite/{sim => }/cris/asm/cmpm.ms | 0 sim/testsuite/{sim => }/cris/asm/cmpq.ms | 0 sim/testsuite/{sim => }/cris/asm/cmpr.ms | 0 sim/testsuite/{sim => }/cris/asm/cmpxc.ms | 0 sim/testsuite/{sim => }/cris/asm/cmpxm.ms | 0 sim/testsuite/{sim => }/cris/asm/dflags.ms | 0 sim/testsuite/{sim => }/cris/asm/dip.ms | 0 sim/testsuite/{sim => }/cris/asm/dstep.ms | 0 sim/testsuite/{sim => }/cris/asm/fidxd.ms | 0 sim/testsuite/{sim => }/cris/asm/fidxi.ms | 0 sim/testsuite/{sim => }/cris/asm/ftagd.ms | 0 sim/testsuite/{sim => }/cris/asm/ftagi.ms | 0 sim/testsuite/{sim => }/cris/asm/halt.ms | 0 sim/testsuite/{sim => }/cris/asm/io1.ms | 0 sim/testsuite/{sim => }/cris/asm/io2.ms | 0 sim/testsuite/{sim => }/cris/asm/io3.ms | 0 sim/testsuite/{sim => }/cris/asm/io4.ms | 0 sim/testsuite/{sim => }/cris/asm/io5.ms | 0 sim/testsuite/{sim => }/cris/asm/io6.ms | 0 sim/testsuite/{sim => }/cris/asm/io7.ms | 0 sim/testsuite/{sim => }/cris/asm/io8.ms | 0 sim/testsuite/{sim => }/cris/asm/io9.ms | 0 sim/testsuite/{sim => }/cris/asm/jsr.ms | 0 sim/testsuite/{sim => }/cris/asm/jsrmv10.ms | 0 sim/testsuite/{sim => }/cris/asm/jumpmp.ms | 0 sim/testsuite/{sim => }/cris/asm/jumppv32.ms | 0 sim/testsuite/{sim => }/cris/asm/lapc.ms | 0 sim/testsuite/{sim => }/cris/asm/lsl.ms | 0 sim/testsuite/{sim => }/cris/asm/lsr.ms | 0 sim/testsuite/{sim => }/cris/asm/lz.ms | 0 sim/testsuite/{sim => }/cris/asm/mcp.ms | 0 sim/testsuite/{sim => }/cris/asm/movdelsr1.ms | 0 sim/testsuite/{sim => }/cris/asm/movecpc.ms | 0 sim/testsuite/{sim => }/cris/asm/movecr.ms | 0 sim/testsuite/{sim => }/cris/asm/movecrt10.ms | 0 sim/testsuite/{sim => }/cris/asm/movecrt32.ms | 0 sim/testsuite/{sim => }/cris/asm/movect10.ms | 0 sim/testsuite/{sim => }/cris/asm/movei.ms | 0 sim/testsuite/{sim => }/cris/asm/movempc.ms | 0 sim/testsuite/{sim => }/cris/asm/movemr.ms | 0 sim/testsuite/{sim => }/cris/asm/movemrv10.ms | 0 sim/testsuite/{sim => }/cris/asm/movemrv32.ms | 0 sim/testsuite/{sim => }/cris/asm/movepcb.ms | 0 sim/testsuite/{sim => }/cris/asm/movepcd.ms | 0 sim/testsuite/{sim => }/cris/asm/movepcw.ms | 0 sim/testsuite/{sim => }/cris/asm/moveq.ms | 0 sim/testsuite/{sim => }/cris/asm/moveqpc.ms | 0 sim/testsuite/{sim => }/cris/asm/mover.ms | 0 sim/testsuite/{sim => }/cris/asm/moverbpc.ms | 0 sim/testsuite/{sim => }/cris/asm/moverdpc.ms | 0 sim/testsuite/{sim => }/cris/asm/moverm.ms | 0 sim/testsuite/{sim => }/cris/asm/moverpcb.ms | 0 sim/testsuite/{sim => }/cris/asm/moverpcd.ms | 0 sim/testsuite/{sim => }/cris/asm/moverpcw.ms | 0 sim/testsuite/{sim => }/cris/asm/moverwpc.ms | 0 sim/testsuite/{sim => }/cris/asm/movesmp.ms | 0 sim/testsuite/{sim => }/cris/asm/movmp.ms | 0 sim/testsuite/{sim => }/cris/asm/movmp8.ms | 0 sim/testsuite/{sim => }/cris/asm/movpmv10.ms | 0 sim/testsuite/{sim => }/cris/asm/movpmv32.ms | 0 sim/testsuite/{sim => }/cris/asm/movppc.ms | 0 sim/testsuite/{sim => }/cris/asm/movpr.ms | 0 sim/testsuite/{sim => }/cris/asm/movprv10.ms | 0 sim/testsuite/{sim => }/cris/asm/movprv32.ms | 0 sim/testsuite/{sim => }/cris/asm/movrss.ms | 0 sim/testsuite/{sim => }/cris/asm/movscpc.ms | 0 sim/testsuite/{sim => }/cris/asm/movscr.ms | 0 sim/testsuite/{sim => }/cris/asm/movsm.ms | 0 sim/testsuite/{sim => }/cris/asm/movsmpc.ms | 0 sim/testsuite/{sim => }/cris/asm/movsr.ms | 0 sim/testsuite/{sim => }/cris/asm/movsrpc.ms | 0 sim/testsuite/{sim => }/cris/asm/movssr.ms | 0 sim/testsuite/{sim => }/cris/asm/movucpc.ms | 0 sim/testsuite/{sim => }/cris/asm/movucr.ms | 0 sim/testsuite/{sim => }/cris/asm/movum.ms | 0 sim/testsuite/{sim => }/cris/asm/movumpc.ms | 0 sim/testsuite/{sim => }/cris/asm/movur.ms | 0 sim/testsuite/{sim => }/cris/asm/movurpc.ms | 0 sim/testsuite/{sim => }/cris/asm/mstep.ms | 0 sim/testsuite/{sim => }/cris/asm/msteppc1.ms | 0 sim/testsuite/{sim => }/cris/asm/msteppc2.ms | 0 sim/testsuite/{sim => }/cris/asm/msteppc3.ms | 0 sim/testsuite/{sim => }/cris/asm/mulv10.ms | 0 sim/testsuite/{sim => }/cris/asm/mulv32.ms | 0 sim/testsuite/{sim => }/cris/asm/mulx.ms | 0 sim/testsuite/{sim => }/cris/asm/neg.ms | 0 sim/testsuite/{sim => }/cris/asm/nonvcv32.ms | 0 sim/testsuite/{sim => }/cris/asm/nopv10t.ms | 0 sim/testsuite/{sim => }/cris/asm/nopv32t.ms | 0 sim/testsuite/{sim => }/cris/asm/nopv32t2.ms | 0 sim/testsuite/{sim => }/cris/asm/nopv32t3.ms | 0 sim/testsuite/{sim => }/cris/asm/nopv32t4.ms | 0 sim/testsuite/{sim => }/cris/asm/not.ms | 0 sim/testsuite/{sim => }/cris/asm/op3.ms | 0 sim/testsuite/{sim => }/cris/asm/opterr1.ms | 0 sim/testsuite/{sim => }/cris/asm/opterr2.ms | 0 sim/testsuite/{sim => }/cris/asm/opterr3.ms | 0 sim/testsuite/{sim => }/cris/asm/opterr4.ms | 0 sim/testsuite/{sim => }/cris/asm/opterr5.ms | 0 sim/testsuite/{sim => }/cris/asm/option1.ms | 0 sim/testsuite/{sim => }/cris/asm/option2.ms | 0 sim/testsuite/{sim => }/cris/asm/option3.ms | 0 sim/testsuite/{sim => }/cris/asm/option4.ms | 0 sim/testsuite/{sim => }/cris/asm/orc.ms | 0 sim/testsuite/{sim => }/cris/asm/orm.ms | 0 sim/testsuite/{sim => }/cris/asm/orq.ms | 0 sim/testsuite/{sim => }/cris/asm/orr.ms | 0 sim/testsuite/{sim => }/cris/asm/pcplus.ms | 0 sim/testsuite/{sim => }/cris/asm/pid1.ms | 0 sim/testsuite/{sim => }/cris/asm/raw1.ms | 0 sim/testsuite/{sim => }/cris/asm/raw10.ms | 0 sim/testsuite/{sim => }/cris/asm/raw11.ms | 0 sim/testsuite/{sim => }/cris/asm/raw12.ms | 0 sim/testsuite/{sim => }/cris/asm/raw13.ms | 0 sim/testsuite/{sim => }/cris/asm/raw14.ms | 0 sim/testsuite/{sim => }/cris/asm/raw15.ms | 0 sim/testsuite/{sim => }/cris/asm/raw16.ms | 0 sim/testsuite/{sim => }/cris/asm/raw17.ms | 0 sim/testsuite/{sim => }/cris/asm/raw2.ms | 0 sim/testsuite/{sim => }/cris/asm/raw3.ms | 0 sim/testsuite/{sim => }/cris/asm/raw4.ms | 0 sim/testsuite/{sim => }/cris/asm/raw5.ms | 0 sim/testsuite/{sim => }/cris/asm/raw6.ms | 0 sim/testsuite/{sim => }/cris/asm/raw7.ms | 0 sim/testsuite/{sim => }/cris/asm/raw8.ms | 0 sim/testsuite/{sim => }/cris/asm/raw9.ms | 0 sim/testsuite/{sim => }/cris/asm/ret.ms | 0 sim/testsuite/{sim => }/cris/asm/rfe.ms | 0 sim/testsuite/{sim => }/cris/asm/rfg.ms | 0 sim/testsuite/{sim => }/cris/asm/rfn.ms | 0 sim/testsuite/{sim => }/cris/asm/sbfs.ms | 0 sim/testsuite/{sim => }/cris/asm/scc.ms | 0 sim/testsuite/{sim => }/cris/asm/sfe.ms | 0 sim/testsuite/{sim => }/cris/asm/subc.ms | 0 sim/testsuite/{sim => }/cris/asm/subm.ms | 0 sim/testsuite/{sim => }/cris/asm/subq.ms | 0 sim/testsuite/{sim => }/cris/asm/subqpc.ms | 0 sim/testsuite/{sim => }/cris/asm/subr.ms | 0 sim/testsuite/{sim => }/cris/asm/subxc.ms | 0 sim/testsuite/{sim => }/cris/asm/subxm.ms | 0 sim/testsuite/{sim => }/cris/asm/subxr.ms | 0 sim/testsuite/{sim => }/cris/asm/swap.ms | 0 sim/testsuite/{sim => }/cris/asm/tb.ms | 0 sim/testsuite/{sim => }/cris/asm/test.ms | 0 sim/testsuite/{sim => }/cris/asm/testutils.inc | 0 sim/testsuite/{sim => }/cris/asm/tjmpsrv32-2.ms | 0 sim/testsuite/{sim => }/cris/asm/tjmpsrv32.ms | 0 sim/testsuite/{sim => }/cris/asm/tjsrcv10.ms | 0 sim/testsuite/{sim => }/cris/asm/tjsrcv32.ms | 0 sim/testsuite/{sim => }/cris/asm/tmemv10.ms | 0 sim/testsuite/{sim => }/cris/asm/tmemv32.ms | 0 sim/testsuite/{sim => }/cris/asm/tmulv10.ms | 0 sim/testsuite/{sim => }/cris/asm/tmulv32.ms | 0 sim/testsuite/{sim => }/cris/asm/tmvm1.ms | 0 sim/testsuite/{sim => }/cris/asm/tmvm2.ms | 0 sim/testsuite/{sim => }/cris/asm/tmvmrv10.ms | 0 sim/testsuite/{sim => }/cris/asm/tmvmrv32.ms | 0 sim/testsuite/{sim => }/cris/asm/tmvrmv10.ms | 0 sim/testsuite/{sim => }/cris/asm/tmvrmv32.ms | 0 sim/testsuite/{sim => }/cris/asm/user.ms | 0 sim/testsuite/{sim => }/cris/asm/x0-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/x0-v32.ms | 0 sim/testsuite/{sim => }/cris/asm/x1-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/x1-v32.ms | 0 sim/testsuite/{sim => }/cris/asm/x10-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/x2-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/x2-v32.ms | 0 sim/testsuite/{sim => }/cris/asm/x3-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/x3-v32.ms | 0 sim/testsuite/{sim => }/cris/asm/x4-v32.ms | 0 sim/testsuite/{sim => }/cris/asm/x5-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/x5-v32.ms | 0 sim/testsuite/{sim => }/cris/asm/x6-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/x6-v32.ms | 0 sim/testsuite/{sim => }/cris/asm/x7-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/x7-v32.ms | 0 sim/testsuite/{sim => }/cris/asm/x8-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/x9-v10.ms | 0 sim/testsuite/{sim => }/cris/asm/xor.ms | 0 sim/testsuite/{sim => }/cris/c/access1.c | 0 sim/testsuite/{sim => }/cris/c/append1.c | 0 sim/testsuite/{sim => }/cris/c/badldso1.c | 0 sim/testsuite/{sim => }/cris/c/badldso2.c | 0 sim/testsuite/{sim => }/cris/c/badldso3.c | 0 sim/testsuite/{sim => }/cris/c/c.exp | 0 sim/testsuite/{sim => }/cris/c/clone1.c | 0 sim/testsuite/{sim => }/cris/c/clone2.c | 0 sim/testsuite/{sim => }/cris/c/clone3.c | 0 sim/testsuite/{sim => }/cris/c/clone4.c | 0 sim/testsuite/{sim => }/cris/c/clone5.c | 0 sim/testsuite/{sim => }/cris/c/clone6.c | 0 sim/testsuite/{sim => }/cris/c/ex1.c | 0 sim/testsuite/{sim => }/cris/c/exitg1.c | 0 sim/testsuite/{sim => }/cris/c/exitg2.c | 0 sim/testsuite/{sim => }/cris/c/fcntl1.c | 0 sim/testsuite/{sim => }/cris/c/fcntl2.c | 0 sim/testsuite/{sim => }/cris/c/fdopen1.c | 0 sim/testsuite/{sim => }/cris/c/fdopen2.c | 0 sim/testsuite/{sim => }/cris/c/freopen1.c | 0 sim/testsuite/{sim => }/cris/c/freopen2.c | 0 sim/testsuite/{sim => }/cris/c/ftruncate1.c | 0 sim/testsuite/{sim => }/cris/c/ftruncate2.c | 0 sim/testsuite/{sim => }/cris/c/getcwd1.c | 0 sim/testsuite/{sim => }/cris/c/gettod.c | 0 sim/testsuite/{sim => }/cris/c/hello.c | 0 sim/testsuite/{sim => }/cris/c/helloaout.c | 0 sim/testsuite/{sim => }/cris/c/hellodyn.c | 0 sim/testsuite/{sim => }/cris/c/hellodyn2.c | 0 sim/testsuite/{sim => }/cris/c/hellodyn3.c | 0 sim/testsuite/{sim => }/cris/c/kill1.c | 0 sim/testsuite/{sim => }/cris/c/kill2.c | 0 sim/testsuite/{sim => }/cris/c/kill3.c | 0 sim/testsuite/{sim => }/cris/c/mapbrk.c | 0 sim/testsuite/{sim => }/cris/c/mmap1.c | 0 sim/testsuite/{sim => }/cris/c/mmap2.c | 0 sim/testsuite/{sim => }/cris/c/mmap3.c | 0 sim/testsuite/{sim => }/cris/c/mmap4.c | 0 sim/testsuite/{sim => }/cris/c/mmap5.c | 0 sim/testsuite/{sim => }/cris/c/mmap6.c | 0 sim/testsuite/{sim => }/cris/c/mmap7.c | 0 sim/testsuite/{sim => }/cris/c/mmap8.c | 0 sim/testsuite/{sim => }/cris/c/mprotect1.c | 0 sim/testsuite/{sim => }/cris/c/mprotect2.c | 0 sim/testsuite/{sim => }/cris/c/mremap.c | 0 sim/testsuite/{sim => }/cris/c/openpf1.c | 0 sim/testsuite/{sim => }/cris/c/openpf2.c | 0 sim/testsuite/{sim => }/cris/c/openpf3.c | 0 sim/testsuite/{sim => }/cris/c/openpf4.c | 0 sim/testsuite/{sim => }/cris/c/openpf5.c | 0 sim/testsuite/{sim => }/cris/c/pipe1.c | 0 sim/testsuite/{sim => }/cris/c/pipe2.c | 0 sim/testsuite/{sim => }/cris/c/pipe3.c | 0 sim/testsuite/{sim => }/cris/c/pipe4.c | 0 sim/testsuite/{sim => }/cris/c/pipe5.c | 0 sim/testsuite/{sim => }/cris/c/pipe6.c | 0 sim/testsuite/{sim => }/cris/c/pipe7.c | 0 sim/testsuite/{sim => }/cris/c/readlink1.c | 0 sim/testsuite/{sim => }/cris/c/readlink10.c | 0 sim/testsuite/{sim => }/cris/c/readlink11.c | 0 sim/testsuite/{sim => }/cris/c/readlink2.c | 0 sim/testsuite/{sim => }/cris/c/readlink3.c | 0 sim/testsuite/{sim => }/cris/c/readlink4.c | 0 sim/testsuite/{sim => }/cris/c/readlink5.c | 0 sim/testsuite/{sim => }/cris/c/readlink6.c | 0 sim/testsuite/{sim => }/cris/c/readlink7.c | 0 sim/testsuite/{sim => }/cris/c/readlink8.c | 0 sim/testsuite/{sim => }/cris/c/readlink9.c | 0 sim/testsuite/{sim => }/cris/c/rename2.c | 0 sim/testsuite/{sim => }/cris/c/rtsigprocmask1.c | 0 sim/testsuite/{sim => }/cris/c/rtsigprocmask2.c | 0 sim/testsuite/{sim => }/cris/c/rtsigsuspend1.c | 0 sim/testsuite/{sim => }/cris/c/rtsigsuspend2.c | 0 sim/testsuite/{sim => }/cris/c/sched1.c | 0 sim/testsuite/{sim => }/cris/c/sched2.c | 0 sim/testsuite/{sim => }/cris/c/sched3.c | 0 sim/testsuite/{sim => }/cris/c/sched4.c | 0 sim/testsuite/{sim => }/cris/c/sched5.c | 0 sim/testsuite/{sim => }/cris/c/sched6.c | 0 sim/testsuite/{sim => }/cris/c/sched7.c | 0 sim/testsuite/{sim => }/cris/c/sched8.c | 0 sim/testsuite/{sim => }/cris/c/sched9.c | 0 sim/testsuite/{sim => }/cris/c/seek1.c | 0 sim/testsuite/{sim => }/cris/c/seek2.c | 0 sim/testsuite/{sim => }/cris/c/seek3.c | 0 sim/testsuite/{sim => }/cris/c/seek4.c | 0 sim/testsuite/{sim => }/cris/c/setrlimit1.c | 0 sim/testsuite/{sim => }/cris/c/settls1.c | 0 sim/testsuite/{sim => }/cris/c/sig1.c | 0 sim/testsuite/{sim => }/cris/c/sig10.c | 0 sim/testsuite/{sim => }/cris/c/sig11.c | 0 sim/testsuite/{sim => }/cris/c/sig12.c | 0 sim/testsuite/{sim => }/cris/c/sig13.c | 0 sim/testsuite/{sim => }/cris/c/sig2.c | 0 sim/testsuite/{sim => }/cris/c/sig3.c | 0 sim/testsuite/{sim => }/cris/c/sig4.c | 0 sim/testsuite/{sim => }/cris/c/sig5.c | 0 sim/testsuite/{sim => }/cris/c/sig6.c | 0 sim/testsuite/{sim => }/cris/c/sig7.c | 0 sim/testsuite/{sim => }/cris/c/sig8.c | 0 sim/testsuite/{sim => }/cris/c/sig9.c | 0 sim/testsuite/{sim => }/cris/c/sigreturn1.c | 0 sim/testsuite/{sim => }/cris/c/sigreturn2.c | 0 sim/testsuite/{sim => }/cris/c/sigreturn3.c | 0 sim/testsuite/{sim => }/cris/c/sigreturn4.c | 0 sim/testsuite/{sim => }/cris/c/sjlj.c | 0 sim/testsuite/{sim => }/cris/c/sock1.c | 0 sim/testsuite/{sim => }/cris/c/stat1.c | 0 sim/testsuite/{sim => }/cris/c/stat2.c | 0 sim/testsuite/{sim => }/cris/c/stat3.c | 0 sim/testsuite/{sim => }/cris/c/stat4.c | 0 sim/testsuite/{sim => }/cris/c/stat5.c | 0 sim/testsuite/{sim => }/cris/c/stat7.c | 0 sim/testsuite/{sim => }/cris/c/stat8.c | 0 sim/testsuite/{sim => }/cris/c/syscall1.c | 0 sim/testsuite/{sim => }/cris/c/syscall2.c | 0 sim/testsuite/{sim => }/cris/c/syscall3.c | 0 sim/testsuite/{sim => }/cris/c/syscall4.c | 0 sim/testsuite/{sim => }/cris/c/syscall5.c | 0 sim/testsuite/{sim => }/cris/c/syscall6.c | 0 sim/testsuite/{sim => }/cris/c/syscall7.c | 0 sim/testsuite/{sim => }/cris/c/syscall8.c | 0 sim/testsuite/{sim => }/cris/c/sysctl1.c | 0 sim/testsuite/{sim => }/cris/c/sysctl2.c | 0 sim/testsuite/{sim => }/cris/c/sysctl3.c | 0 sim/testsuite/{sim => }/cris/c/thread2.c | 0 sim/testsuite/{sim => }/cris/c/thread3.c | 0 sim/testsuite/{sim => }/cris/c/thread4.c | 0 sim/testsuite/{sim => }/cris/c/thread5.c | 0 sim/testsuite/{sim => }/cris/c/time1.c | 0 sim/testsuite/{sim => }/cris/c/time2.c | 0 sim/testsuite/{sim => }/cris/c/truncate1.c | 0 sim/testsuite/{sim => }/cris/c/truncate2.c | 0 sim/testsuite/{sim => }/cris/c/ugetrlimit1.c | 0 sim/testsuite/{sim => }/cris/c/uname1.c | 0 sim/testsuite/{sim => }/cris/c/writev1.c | 0 sim/testsuite/{sim => }/cris/c/writev2.c | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/host1.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq1.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq2.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq3.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq4.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq5.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq6.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/mbox1.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/mem1.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/mem2.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/poll1.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/quit.s | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/rvc.exp | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/std.dev | 0 .../{sim => }/cris/hw/rv-n-cris/testutils.inc | 0 .../{sim => }/cris/hw/rv-n-cris/trivial1.ms | 0 .../{sim => }/cris/hw/rv-n-cris/trivial2.ms | 0 .../{sim => }/cris/hw/rv-n-cris/trivial3.ms | 0 .../{sim => }/cris/hw/rv-n-cris/trivial4.ms | 0 .../{sim => }/cris/hw/rv-n-cris/trivial4.r | 0 .../{sim => }/cris/hw/rv-n-cris/trivial5.ms | 0 sim/testsuite/{sim => }/cris/hw/rv-n-cris/wd1.ms | 0 sim/testsuite/{sim => }/d10v/ChangeLog | 0 sim/testsuite/{sim => }/d10v/allinsn.exp | 0 sim/testsuite/{sim => }/d10v/exit47.s | 0 sim/testsuite/{sim => }/d10v/hello.s | 0 sim/testsuite/{sim => }/d10v/t-ae-ld-d.s | 0 sim/testsuite/{sim => }/d10v/t-ae-ld-i.s | 0 sim/testsuite/{sim => }/d10v/t-ae-ld-id.s | 0 sim/testsuite/{sim => }/d10v/t-ae-ld-im.s | 0 sim/testsuite/{sim => }/d10v/t-ae-ld-ip.s | 0 sim/testsuite/{sim => }/d10v/t-ae-ld2w-d.s | 0 sim/testsuite/{sim => }/d10v/t-ae-ld2w-i.s | 0 sim/testsuite/{sim => }/d10v/t-ae-ld2w-id.s | 0 sim/testsuite/{sim => }/d10v/t-ae-ld2w-im.s | 0 sim/testsuite/{sim => }/d10v/t-ae-ld2w-ip.s | 0 sim/testsuite/{sim => }/d10v/t-ae-st-d.s | 0 sim/testsuite/{sim => }/d10v/t-ae-st-i.s | 0 sim/testsuite/{sim => }/d10v/t-ae-st-id.s | 0 sim/testsuite/{sim => }/d10v/t-ae-st-im.s | 0 sim/testsuite/{sim => }/d10v/t-ae-st-ip.s | 0 sim/testsuite/{sim => }/d10v/t-ae-st-is.s | 0 sim/testsuite/{sim => }/d10v/t-ae-st2w-d.s | 0 sim/testsuite/{sim => }/d10v/t-ae-st2w-i.s | 0 sim/testsuite/{sim => }/d10v/t-ae-st2w-id.s | 0 sim/testsuite/{sim => }/d10v/t-ae-st2w-im.s | 0 sim/testsuite/{sim => }/d10v/t-ae-st2w-ip.s | 0 sim/testsuite/{sim => }/d10v/t-ae-st2w-is.s | 0 sim/testsuite/{sim => }/d10v/t-dbt.s | 0 sim/testsuite/{sim => }/d10v/t-ld-st.s | 0 sim/testsuite/{sim => }/d10v/t-mac.s | 0 sim/testsuite/{sim => }/d10v/t-macros.i | 0 sim/testsuite/{sim => }/d10v/t-mod-ld-pre.s | 0 sim/testsuite/{sim => }/d10v/t-msbu.s | 0 sim/testsuite/{sim => }/d10v/t-mulxu.s | 0 sim/testsuite/{sim => }/d10v/t-mvtac.s | 0 sim/testsuite/{sim => }/d10v/t-mvtc.s | 0 sim/testsuite/{sim => }/d10v/t-rac.s | 0 sim/testsuite/{sim => }/d10v/t-rachi.s | 0 sim/testsuite/{sim => }/d10v/t-rdt.s | 0 sim/testsuite/{sim => }/d10v/t-rep.s | 0 sim/testsuite/{sim => }/d10v/t-rie-xx.s | 0 sim/testsuite/{sim => }/d10v/t-rte.s | 0 sim/testsuite/{sim => }/d10v/t-sac.s | 0 sim/testsuite/{sim => }/d10v/t-sachi.s | 0 sim/testsuite/{sim => }/d10v/t-sadd.s | 0 sim/testsuite/{sim => }/d10v/t-slae.s | 0 sim/testsuite/{sim => }/d10v/t-sp.s | 0 sim/testsuite/{sim => }/d10v/t-sub.s | 0 sim/testsuite/{sim => }/d10v/t-sub2w.s | 0 sim/testsuite/{sim => }/d10v/t-subi.s | 0 sim/testsuite/{sim => }/d10v/t-trap.s | 0 sim/testsuite/{sim => }/frv/ChangeLog | 0 sim/testsuite/{sim => }/frv/add.cgs | 0 sim/testsuite/{sim => }/frv/add.pcgs | 0 sim/testsuite/{sim => }/frv/addcc.cgs | 0 sim/testsuite/{sim => }/frv/addi.cgs | 0 sim/testsuite/{sim => }/frv/addicc.cgs | 0 sim/testsuite/{sim => }/frv/addx.cgs | 0 sim/testsuite/{sim => }/frv/addxcc.cgs | 0 sim/testsuite/{sim => }/frv/addxi.cgs | 0 sim/testsuite/{sim => }/frv/addxicc.cgs | 0 sim/testsuite/{sim => }/frv/allinsn.exp | 0 sim/testsuite/{sim => }/frv/and.cgs | 0 sim/testsuite/{sim => }/frv/andcc.cgs | 0 sim/testsuite/{sim => }/frv/andcr.cgs | 0 sim/testsuite/{sim => }/frv/andi.cgs | 0 sim/testsuite/{sim => }/frv/andicc.cgs | 0 sim/testsuite/{sim => }/frv/andncr.cgs | 0 sim/testsuite/{sim => }/frv/bar.cgs | 0 sim/testsuite/{sim => }/frv/bc.cgs | 0 sim/testsuite/{sim => }/frv/bcclr.cgs | 0 sim/testsuite/{sim => }/frv/bceqlr.cgs | 0 sim/testsuite/{sim => }/frv/bcgelr.cgs | 0 sim/testsuite/{sim => }/frv/bcgtlr.cgs | 0 sim/testsuite/{sim => }/frv/bchilr.cgs | 0 sim/testsuite/{sim => }/frv/bclelr.cgs | 0 sim/testsuite/{sim => }/frv/bclr.cgs | 0 sim/testsuite/{sim => }/frv/bclslr.cgs | 0 sim/testsuite/{sim => }/frv/bcltlr.cgs | 0 sim/testsuite/{sim => }/frv/bcnclr.cgs | 0 sim/testsuite/{sim => }/frv/bcnelr.cgs | 0 sim/testsuite/{sim => }/frv/bcnlr.cgs | 0 sim/testsuite/{sim => }/frv/bcnolr.cgs | 0 sim/testsuite/{sim => }/frv/bcnvlr.cgs | 0 sim/testsuite/{sim => }/frv/bcplr.cgs | 0 sim/testsuite/{sim => }/frv/bcralr.cgs | 0 sim/testsuite/{sim => }/frv/bctrlr.cgs | 0 sim/testsuite/{sim => }/frv/bcvlr.cgs | 0 sim/testsuite/{sim => }/frv/beq.cgs | 0 sim/testsuite/{sim => }/frv/beqlr.cgs | 0 sim/testsuite/{sim => }/frv/bge.cgs | 0 sim/testsuite/{sim => }/frv/bgelr.cgs | 0 sim/testsuite/{sim => }/frv/bgt.cgs | 0 sim/testsuite/{sim => }/frv/bgtlr.cgs | 0 sim/testsuite/{sim => }/frv/bhi.cgs | 0 sim/testsuite/{sim => }/frv/bhilr.cgs | 0 sim/testsuite/{sim => }/frv/ble.cgs | 0 sim/testsuite/{sim => }/frv/blelr.cgs | 0 sim/testsuite/{sim => }/frv/bls.cgs | 0 sim/testsuite/{sim => }/frv/blslr.cgs | 0 sim/testsuite/{sim => }/frv/blt.cgs | 0 sim/testsuite/{sim => }/frv/bltlr.cgs | 0 sim/testsuite/{sim => }/frv/bn.cgs | 0 sim/testsuite/{sim => }/frv/bnc.cgs | 0 sim/testsuite/{sim => }/frv/bnclr.cgs | 0 sim/testsuite/{sim => }/frv/bne.cgs | 0 sim/testsuite/{sim => }/frv/bnelr.cgs | 0 sim/testsuite/{sim => }/frv/bnlr.cgs | 0 sim/testsuite/{sim => }/frv/bno.cgs | 0 sim/testsuite/{sim => }/frv/bnolr.cgs | 0 sim/testsuite/{sim => }/frv/bnv.cgs | 0 sim/testsuite/{sim => }/frv/bnvlr.cgs | 0 sim/testsuite/{sim => }/frv/bp.cgs | 0 sim/testsuite/{sim => }/frv/bplr.cgs | 0 sim/testsuite/{sim => }/frv/bra.cgs | 0 sim/testsuite/{sim => }/frv/bralr.cgs | 0 sim/testsuite/{sim => }/frv/branch.pcgs | 0 sim/testsuite/{sim => }/frv/break.cgs | 0 sim/testsuite/{sim => }/frv/bv.cgs | 0 sim/testsuite/{sim => }/frv/bvlr.cgs | 0 sim/testsuite/{sim => }/frv/cache.ms | 0 sim/testsuite/{sim => }/frv/cadd.cgs | 0 sim/testsuite/{sim => }/frv/caddcc.cgs | 0 sim/testsuite/{sim => }/frv/call.cgs | 0 sim/testsuite/{sim => }/frv/call.pcgs | 0 sim/testsuite/{sim => }/frv/callil.cgs | 0 sim/testsuite/{sim => }/frv/calll.cgs | 0 sim/testsuite/{sim => }/frv/cand.cgs | 0 sim/testsuite/{sim => }/frv/candcc.cgs | 0 sim/testsuite/{sim => }/frv/ccalll.cgs | 0 sim/testsuite/{sim => }/frv/cckc.cgs | 0 sim/testsuite/{sim => }/frv/cckeq.cgs | 0 sim/testsuite/{sim => }/frv/cckge.cgs | 0 sim/testsuite/{sim => }/frv/cckgt.cgs | 0 sim/testsuite/{sim => }/frv/cckhi.cgs | 0 sim/testsuite/{sim => }/frv/cckle.cgs | 0 sim/testsuite/{sim => }/frv/cckls.cgs | 0 sim/testsuite/{sim => }/frv/ccklt.cgs | 0 sim/testsuite/{sim => }/frv/cckn.cgs | 0 sim/testsuite/{sim => }/frv/ccknc.cgs | 0 sim/testsuite/{sim => }/frv/cckne.cgs | 0 sim/testsuite/{sim => }/frv/cckno.cgs | 0 sim/testsuite/{sim => }/frv/ccknv.cgs | 0 sim/testsuite/{sim => }/frv/cckp.cgs | 0 sim/testsuite/{sim => }/frv/cckra.cgs | 0 sim/testsuite/{sim => }/frv/cckv.cgs | 0 sim/testsuite/{sim => }/frv/ccmp.cgs | 0 sim/testsuite/{sim => }/frv/cfabss.cgs | 0 sim/testsuite/{sim => }/frv/cfadds.cgs | 0 sim/testsuite/{sim => }/frv/cfckeq.cgs | 0 sim/testsuite/{sim => }/frv/cfckge.cgs | 0 sim/testsuite/{sim => }/frv/cfckgt.cgs | 0 sim/testsuite/{sim => }/frv/cfckle.cgs | 0 sim/testsuite/{sim => }/frv/cfcklg.cgs | 0 sim/testsuite/{sim => }/frv/cfcklt.cgs | 0 sim/testsuite/{sim => }/frv/cfckne.cgs | 0 sim/testsuite/{sim => }/frv/cfckno.cgs | 0 sim/testsuite/{sim => }/frv/cfcko.cgs | 0 sim/testsuite/{sim => }/frv/cfckra.cgs | 0 sim/testsuite/{sim => }/frv/cfcku.cgs | 0 sim/testsuite/{sim => }/frv/cfckue.cgs | 0 sim/testsuite/{sim => }/frv/cfckug.cgs | 0 sim/testsuite/{sim => }/frv/cfckuge.cgs | 0 sim/testsuite/{sim => }/frv/cfckul.cgs | 0 sim/testsuite/{sim => }/frv/cfckule.cgs | 0 sim/testsuite/{sim => }/frv/cfcmps.cgs | 0 sim/testsuite/{sim => }/frv/cfdivs.cgs | 0 sim/testsuite/{sim => }/frv/cfitos.cgs | 0 sim/testsuite/{sim => }/frv/cfmadds.cgs | 0 sim/testsuite/{sim => }/frv/cfmas.cgs | 0 sim/testsuite/{sim => }/frv/cfmovs.cgs | 0 sim/testsuite/{sim => }/frv/cfmss.cgs | 0 sim/testsuite/{sim => }/frv/cfmsubs.cgs | 0 sim/testsuite/{sim => }/frv/cfmuls.cgs | 0 sim/testsuite/{sim => }/frv/cfnegs.cgs | 0 sim/testsuite/{sim => }/frv/cfsqrts.cgs | 0 sim/testsuite/{sim => }/frv/cfstoi.cgs | 0 sim/testsuite/{sim => }/frv/cfsubs.cgs | 0 sim/testsuite/{sim => }/frv/cjmpl.cgs | 0 sim/testsuite/{sim => }/frv/ckc.cgs | 0 sim/testsuite/{sim => }/frv/ckeq.cgs | 0 sim/testsuite/{sim => }/frv/ckge.cgs | 0 sim/testsuite/{sim => }/frv/ckgt.cgs | 0 sim/testsuite/{sim => }/frv/ckhi.cgs | 0 sim/testsuite/{sim => }/frv/ckle.cgs | 0 sim/testsuite/{sim => }/frv/ckls.cgs | 0 sim/testsuite/{sim => }/frv/cklt.cgs | 0 sim/testsuite/{sim => }/frv/ckn.cgs | 0 sim/testsuite/{sim => }/frv/cknc.cgs | 0 sim/testsuite/{sim => }/frv/ckne.cgs | 0 sim/testsuite/{sim => }/frv/ckno.cgs | 0 sim/testsuite/{sim => }/frv/cknv.cgs | 0 sim/testsuite/{sim => }/frv/ckp.cgs | 0 sim/testsuite/{sim => }/frv/ckra.cgs | 0 sim/testsuite/{sim => }/frv/ckv.cgs | 0 sim/testsuite/{sim => }/frv/cld.cgs | 0 sim/testsuite/{sim => }/frv/cldbf.cgs | 0 sim/testsuite/{sim => }/frv/cldbfu.cgs | 0 sim/testsuite/{sim => }/frv/cldd.cgs | 0 sim/testsuite/{sim => }/frv/clddf.cgs | 0 sim/testsuite/{sim => }/frv/clddfu.cgs | 0 sim/testsuite/{sim => }/frv/clddu.cgs | 0 sim/testsuite/{sim => }/frv/cldf.cgs | 0 sim/testsuite/{sim => }/frv/cldfu.cgs | 0 sim/testsuite/{sim => }/frv/cldhf.cgs | 0 sim/testsuite/{sim => }/frv/cldhfu.cgs | 0 sim/testsuite/{sim => }/frv/cldq.cgs | 0 sim/testsuite/{sim => }/frv/cldqu.cgs | 0 sim/testsuite/{sim => }/frv/cldsb.cgs | 0 sim/testsuite/{sim => }/frv/cldsbu.cgs | 0 sim/testsuite/{sim => }/frv/cldsh.cgs | 0 sim/testsuite/{sim => }/frv/cldshu.cgs | 0 sim/testsuite/{sim => }/frv/cldu.cgs | 0 sim/testsuite/{sim => }/frv/cldub.cgs | 0 sim/testsuite/{sim => }/frv/cldubu.cgs | 0 sim/testsuite/{sim => }/frv/clduh.cgs | 0 sim/testsuite/{sim => }/frv/clduhu.cgs | 0 sim/testsuite/{sim => }/frv/clrfa.cgs | 0 sim/testsuite/{sim => }/frv/clrfr.cgs | 0 sim/testsuite/{sim => }/frv/clrga.cgs | 0 sim/testsuite/{sim => }/frv/clrgr.cgs | 0 sim/testsuite/{sim => }/frv/cmaddhss.cgs | 0 sim/testsuite/{sim => }/frv/cmaddhus.cgs | 0 sim/testsuite/{sim => }/frv/cmand.cgs | 0 sim/testsuite/{sim => }/frv/cmbtoh.cgs | 0 sim/testsuite/{sim => }/frv/cmbtohe.cgs | 0 sim/testsuite/{sim => }/frv/cmcpxis.cgs | 0 sim/testsuite/{sim => }/frv/cmcpxiu.cgs | 0 sim/testsuite/{sim => }/frv/cmcpxrs.cgs | 0 sim/testsuite/{sim => }/frv/cmcpxru.cgs | 0 sim/testsuite/{sim => }/frv/cmexpdhd.cgs | 0 sim/testsuite/{sim => }/frv/cmexpdhw.cgs | 0 sim/testsuite/{sim => }/frv/cmhtob.cgs | 0 sim/testsuite/{sim => }/frv/cmmachs.cgs | 0 sim/testsuite/{sim => }/frv/cmmachu.cgs | 0 sim/testsuite/{sim => }/frv/cmmulhs.cgs | 0 sim/testsuite/{sim => }/frv/cmmulhu.cgs | 0 sim/testsuite/{sim => }/frv/cmnot.cgs | 0 sim/testsuite/{sim => }/frv/cmor.cgs | 0 sim/testsuite/{sim => }/frv/cmov.cgs | 0 sim/testsuite/{sim => }/frv/cmovfg.cgs | 0 sim/testsuite/{sim => }/frv/cmovfgd.cgs | 0 sim/testsuite/{sim => }/frv/cmovgf.cgs | 0 sim/testsuite/{sim => }/frv/cmovgfd.cgs | 0 sim/testsuite/{sim => }/frv/cmp.cgs | 0 sim/testsuite/{sim => }/frv/cmpb.cgs | 0 sim/testsuite/{sim => }/frv/cmpba.cgs | 0 sim/testsuite/{sim => }/frv/cmpi.cgs | 0 sim/testsuite/{sim => }/frv/cmqmachs.cgs | 0 sim/testsuite/{sim => }/frv/cmqmachu.cgs | 0 sim/testsuite/{sim => }/frv/cmqmulhs.cgs | 0 sim/testsuite/{sim => }/frv/cmqmulhu.cgs | 0 sim/testsuite/{sim => }/frv/cmsubhss.cgs | 0 sim/testsuite/{sim => }/frv/cmsubhus.cgs | 0 sim/testsuite/{sim => }/frv/cmxor.cgs | 0 sim/testsuite/{sim => }/frv/cnot.cgs | 0 sim/testsuite/{sim => }/frv/commitfa.cgs | 0 sim/testsuite/{sim => }/frv/commitfr.cgs | 0 sim/testsuite/{sim => }/frv/commitga.cgs | 0 sim/testsuite/{sim => }/frv/commitgr.cgs | 0 sim/testsuite/{sim => }/frv/cop1.cgs | 0 sim/testsuite/{sim => }/frv/cop2.cgs | 0 sim/testsuite/{sim => }/frv/cor.cgs | 0 sim/testsuite/{sim => }/frv/corcc.cgs | 0 sim/testsuite/{sim => }/frv/cscan.cgs | 0 sim/testsuite/{sim => }/frv/csdiv.cgs | 0 sim/testsuite/{sim => }/frv/csll.cgs | 0 sim/testsuite/{sim => }/frv/csllcc.cgs | 0 sim/testsuite/{sim => }/frv/csmul.cgs | 0 sim/testsuite/{sim => }/frv/csmulcc.cgs | 0 sim/testsuite/{sim => }/frv/csra.cgs | 0 sim/testsuite/{sim => }/frv/csracc.cgs | 0 sim/testsuite/{sim => }/frv/csrl.cgs | 0 sim/testsuite/{sim => }/frv/csrlcc.cgs | 0 sim/testsuite/{sim => }/frv/cst.cgs | 0 sim/testsuite/{sim => }/frv/cstb.cgs | 0 sim/testsuite/{sim => }/frv/cstbf.cgs | 0 sim/testsuite/{sim => }/frv/cstbfu.cgs | 0 sim/testsuite/{sim => }/frv/cstbu.cgs | 0 sim/testsuite/{sim => }/frv/cstd.cgs | 0 sim/testsuite/{sim => }/frv/cstdf.cgs | 0 sim/testsuite/{sim => }/frv/cstdfu.cgs | 0 sim/testsuite/{sim => }/frv/cstdu.cgs | 0 sim/testsuite/{sim => }/frv/cstf.cgs | 0 sim/testsuite/{sim => }/frv/cstfu.cgs | 0 sim/testsuite/{sim => }/frv/csth.cgs | 0 sim/testsuite/{sim => }/frv/csthf.cgs | 0 sim/testsuite/{sim => }/frv/csthfu.cgs | 0 sim/testsuite/{sim => }/frv/csthu.cgs | 0 sim/testsuite/{sim => }/frv/cstq.cgs | 0 sim/testsuite/{sim => }/frv/cstu.cgs | 0 sim/testsuite/{sim => }/frv/csub.cgs | 0 sim/testsuite/{sim => }/frv/csubcc.cgs | 0 sim/testsuite/{sim => }/frv/cswap.cgs | 0 sim/testsuite/{sim => }/frv/cudiv.cgs | 0 sim/testsuite/{sim => }/frv/cxor.cgs | 0 sim/testsuite/{sim => }/frv/cxorcc.cgs | 0 sim/testsuite/{sim => }/frv/dcef.cgs | 0 sim/testsuite/{sim => }/frv/dcei.cgs | 0 sim/testsuite/{sim => }/frv/dcf.cgs | 0 sim/testsuite/{sim => }/frv/dci.cgs | 0 sim/testsuite/{sim => }/frv/exit47.ms | 0 sim/testsuite/{sim => }/frv/fabsd.cgs | 0 sim/testsuite/{sim => }/frv/fabss.cgs | 0 sim/testsuite/{sim => }/frv/faddd.cgs | 0 sim/testsuite/{sim => }/frv/fadds.cgs | 0 sim/testsuite/{sim => }/frv/fbeq.cgs | 0 sim/testsuite/{sim => }/frv/fbeqlr.cgs | 0 sim/testsuite/{sim => }/frv/fbge.cgs | 0 sim/testsuite/{sim => }/frv/fbgelr.cgs | 0 sim/testsuite/{sim => }/frv/fbgt.cgs | 0 sim/testsuite/{sim => }/frv/fbgtlr.cgs | 0 sim/testsuite/{sim => }/frv/fble.cgs | 0 sim/testsuite/{sim => }/frv/fblelr.cgs | 0 sim/testsuite/{sim => }/frv/fblg.cgs | 0 sim/testsuite/{sim => }/frv/fblglr.cgs | 0 sim/testsuite/{sim => }/frv/fblt.cgs | 0 sim/testsuite/{sim => }/frv/fbltlr.cgs | 0 sim/testsuite/{sim => }/frv/fbne.cgs | 0 sim/testsuite/{sim => }/frv/fbnelr.cgs | 0 sim/testsuite/{sim => }/frv/fbno.cgs | 0 sim/testsuite/{sim => }/frv/fbnolr.cgs | 0 sim/testsuite/{sim => }/frv/fbo.cgs | 0 sim/testsuite/{sim => }/frv/fbolr.cgs | 0 sim/testsuite/{sim => }/frv/fbra.cgs | 0 sim/testsuite/{sim => }/frv/fbralr.cgs | 0 sim/testsuite/{sim => }/frv/fbu.cgs | 0 sim/testsuite/{sim => }/frv/fbue.cgs | 0 sim/testsuite/{sim => }/frv/fbuelr.cgs | 0 sim/testsuite/{sim => }/frv/fbug.cgs | 0 sim/testsuite/{sim => }/frv/fbuge.cgs | 0 sim/testsuite/{sim => }/frv/fbugelr.cgs | 0 sim/testsuite/{sim => }/frv/fbuglr.cgs | 0 sim/testsuite/{sim => }/frv/fbul.cgs | 0 sim/testsuite/{sim => }/frv/fbule.cgs | 0 sim/testsuite/{sim => }/frv/fbulelr.cgs | 0 sim/testsuite/{sim => }/frv/fbullr.cgs | 0 sim/testsuite/{sim => }/frv/fbulr.cgs | 0 sim/testsuite/{sim => }/frv/fcbeqlr.cgs | 0 sim/testsuite/{sim => }/frv/fcbgelr.cgs | 0 sim/testsuite/{sim => }/frv/fcbgtlr.cgs | 0 sim/testsuite/{sim => }/frv/fcblelr.cgs | 0 sim/testsuite/{sim => }/frv/fcblglr.cgs | 0 sim/testsuite/{sim => }/frv/fcbltlr.cgs | 0 sim/testsuite/{sim => }/frv/fcbnelr.cgs | 0 sim/testsuite/{sim => }/frv/fcbnolr.cgs | 0 sim/testsuite/{sim => }/frv/fcbolr.cgs | 0 sim/testsuite/{sim => }/frv/fcbralr.cgs | 0 sim/testsuite/{sim => }/frv/fcbuelr.cgs | 0 sim/testsuite/{sim => }/frv/fcbugelr.cgs | 0 sim/testsuite/{sim => }/frv/fcbuglr.cgs | 0 sim/testsuite/{sim => }/frv/fcbulelr.cgs | 0 sim/testsuite/{sim => }/frv/fcbullr.cgs | 0 sim/testsuite/{sim => }/frv/fcbulr.cgs | 0 sim/testsuite/{sim => }/frv/fckeq.cgs | 0 sim/testsuite/{sim => }/frv/fckge.cgs | 0 sim/testsuite/{sim => }/frv/fckgt.cgs | 0 sim/testsuite/{sim => }/frv/fckle.cgs | 0 sim/testsuite/{sim => }/frv/fcklg.cgs | 0 sim/testsuite/{sim => }/frv/fcklt.cgs | 0 sim/testsuite/{sim => }/frv/fckne.cgs | 0 sim/testsuite/{sim => }/frv/fckno.cgs | 0 sim/testsuite/{sim => }/frv/fcko.cgs | 0 sim/testsuite/{sim => }/frv/fckra.cgs | 0 sim/testsuite/{sim => }/frv/fcku.cgs | 0 sim/testsuite/{sim => }/frv/fckue.cgs | 0 sim/testsuite/{sim => }/frv/fckug.cgs | 0 sim/testsuite/{sim => }/frv/fckuge.cgs | 0 sim/testsuite/{sim => }/frv/fckul.cgs | 0 sim/testsuite/{sim => }/frv/fckule.cgs | 0 sim/testsuite/{sim => }/frv/fcmpd.cgs | 0 sim/testsuite/{sim => }/frv/fcmps.cgs | 0 sim/testsuite/{sim => }/frv/fdabss.cgs | 0 sim/testsuite/{sim => }/frv/fdadds.cgs | 0 sim/testsuite/{sim => }/frv/fdcmps.cgs | 0 sim/testsuite/{sim => }/frv/fddivs.cgs | 0 sim/testsuite/{sim => }/frv/fditos.cgs | 0 sim/testsuite/{sim => }/frv/fdivd.cgs | 0 sim/testsuite/{sim => }/frv/fdivs.cgs | 0 sim/testsuite/{sim => }/frv/fdmadds.cgs | 0 sim/testsuite/{sim => }/frv/fdmas.cgs | 0 sim/testsuite/{sim => }/frv/fdmovs.cgs | 0 sim/testsuite/{sim => }/frv/fdmss.cgs | 0 sim/testsuite/{sim => }/frv/fdmulcs.cgs | 0 sim/testsuite/{sim => }/frv/fdmuls.cgs | 0 sim/testsuite/{sim => }/frv/fdnegs.cgs | 0 sim/testsuite/{sim => }/frv/fdsads.cgs | 0 sim/testsuite/{sim => }/frv/fdsqrts.cgs | 0 sim/testsuite/{sim => }/frv/fdstoi.cgs | 0 sim/testsuite/{sim => }/frv/fdsubs.cgs | 0 sim/testsuite/{sim => }/frv/fdtoi.cgs | 0 sim/testsuite/{sim => }/frv/fitod.cgs | 0 sim/testsuite/{sim => }/frv/fitos.cgs | 0 sim/testsuite/{sim => }/frv/fmad.cgs | 0 sim/testsuite/{sim => }/frv/fmaddd.cgs | 0 sim/testsuite/{sim => }/frv/fmadds.cgs | 0 sim/testsuite/{sim => }/frv/fmas.cgs | 0 sim/testsuite/{sim => }/frv/fmovd.cgs | 0 sim/testsuite/{sim => }/frv/fmovs.cgs | 0 sim/testsuite/{sim => }/frv/fmsd.cgs | 0 sim/testsuite/{sim => }/frv/fmss.cgs | 0 sim/testsuite/{sim => }/frv/fmsubd.cgs | 0 sim/testsuite/{sim => }/frv/fmsubs.cgs | 0 sim/testsuite/{sim => }/frv/fmuld.cgs | 0 sim/testsuite/{sim => }/frv/fmuls.cgs | 0 sim/testsuite/{sim => }/frv/fnegd.cgs | 0 sim/testsuite/{sim => }/frv/fnegs.cgs | 0 sim/testsuite/{sim => }/frv/fnop.cgs | 0 sim/testsuite/{sim => }/frv/fr400/addss.cgs | 0 sim/testsuite/{sim => }/frv/fr400/allinsn.exp | 0 sim/testsuite/{sim => }/frv/fr400/csdiv.cgs | 0 sim/testsuite/{sim => }/frv/fr400/maddaccs.cgs | 0 sim/testsuite/{sim => }/frv/fr400/masaccs.cgs | 0 sim/testsuite/{sim => }/frv/fr400/maveh.cgs | 0 sim/testsuite/{sim => }/frv/fr400/mclracc.cgs | 0 sim/testsuite/{sim => }/frv/fr400/mhdseth.cgs | 0 sim/testsuite/{sim => }/frv/fr400/mhdsets.cgs | 0 sim/testsuite/{sim => }/frv/fr400/mhsethih.cgs | 0 sim/testsuite/{sim => }/frv/fr400/mhsethis.cgs | 0 sim/testsuite/{sim => }/frv/fr400/mhsetloh.cgs | 0 sim/testsuite/{sim => }/frv/fr400/mhsetlos.cgs | 0 sim/testsuite/{sim => }/frv/fr400/movgs.cgs | 0 sim/testsuite/{sim => }/frv/fr400/movsg.cgs | 0 sim/testsuite/{sim => }/frv/fr400/msubaccs.cgs | 0 sim/testsuite/{sim => }/frv/fr400/scutss.cgs | 0 sim/testsuite/{sim => }/frv/fr400/sdiv.cgs | 0 sim/testsuite/{sim => }/frv/fr400/sdivi.cgs | 0 sim/testsuite/{sim => }/frv/fr400/slass.cgs | 0 sim/testsuite/{sim => }/frv/fr400/smass.cgs | 0 sim/testsuite/{sim => }/frv/fr400/smsss.cgs | 0 sim/testsuite/{sim => }/frv/fr400/smu.cgs | 0 sim/testsuite/{sim => }/frv/fr400/subss.cgs | 0 sim/testsuite/{sim => }/frv/fr400/udiv.cgs | 0 sim/testsuite/{sim => }/frv/fr400/udivi.cgs | 0 sim/testsuite/{sim => }/frv/fr500/allinsn.exp | 0 sim/testsuite/{sim => }/frv/fr500/cmqaddhss.cgs | 0 sim/testsuite/{sim => }/frv/fr500/cmqaddhus.cgs | 0 sim/testsuite/{sim => }/frv/fr500/cmqsubhss.cgs | 0 sim/testsuite/{sim => }/frv/fr500/cmqsubhus.cgs | 0 sim/testsuite/{sim => }/frv/fr500/dcpl.cgs | 0 sim/testsuite/{sim => }/frv/fr500/dcul.cgs | 0 sim/testsuite/{sim => }/frv/fr500/mclracc.cgs | 0 sim/testsuite/{sim => }/frv/fr500/mqaddhss.cgs | 0 sim/testsuite/{sim => }/frv/fr500/mqaddhus.cgs | 0 sim/testsuite/{sim => }/frv/fr500/mqsubhss.cgs | 0 sim/testsuite/{sim => }/frv/fr500/mqsubhus.cgs | 0 sim/testsuite/{sim => }/frv/fr550/allinsn.exp | 0 sim/testsuite/{sim => }/frv/fr550/cmaddhss.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmaddhus.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmcpxiu.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmcpxru.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmmachs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmmachu.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmqaddhss.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmqaddhus.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmqmachs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmqmachu.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmqsubhss.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmqsubhus.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmsubhss.cgs | 0 sim/testsuite/{sim => }/frv/fr550/cmsubhus.cgs | 0 sim/testsuite/{sim => }/frv/fr550/dcpl.cgs | 0 sim/testsuite/{sim => }/frv/fr550/dcul.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mabshs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/maddaccs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/maddhss.cgs | 0 sim/testsuite/{sim => }/frv/fr550/maddhus.cgs | 0 sim/testsuite/{sim => }/frv/fr550/masaccs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mdaddaccs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mdasaccs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mdsubaccs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mmachs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mmachu.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mmrdhs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mmrdhu.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mqaddhss.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mqaddhus.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mqmachs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mqmachu.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mqmacxhs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mqsubhss.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mqsubhus.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mqxmachs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mqxmacxhs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/msubaccs.cgs | 0 sim/testsuite/{sim => }/frv/fr550/msubhss.cgs | 0 sim/testsuite/{sim => }/frv/fr550/msubhus.cgs | 0 sim/testsuite/{sim => }/frv/fr550/mtrap.cgs | 0 sim/testsuite/{sim => }/frv/fr550/udiv.cgs | 0 sim/testsuite/{sim => }/frv/fr550/udivi.cgs | 0 sim/testsuite/{sim => }/frv/fsqrtd.cgs | 0 sim/testsuite/{sim => }/frv/fsqrts.cgs | 0 sim/testsuite/{sim => }/frv/fstoi.cgs | 0 sim/testsuite/{sim => }/frv/fsubd.cgs | 0 sim/testsuite/{sim => }/frv/fsubs.cgs | 0 sim/testsuite/{sim => }/frv/fteq.cgs | 0 sim/testsuite/{sim => }/frv/ftge.cgs | 0 sim/testsuite/{sim => }/frv/ftgt.cgs | 0 sim/testsuite/{sim => }/frv/ftieq.cgs | 0 sim/testsuite/{sim => }/frv/ftige.cgs | 0 sim/testsuite/{sim => }/frv/ftigt.cgs | 0 sim/testsuite/{sim => }/frv/ftile.cgs | 0 sim/testsuite/{sim => }/frv/ftilg.cgs | 0 sim/testsuite/{sim => }/frv/ftilt.cgs | 0 sim/testsuite/{sim => }/frv/ftine.cgs | 0 sim/testsuite/{sim => }/frv/ftino.cgs | 0 sim/testsuite/{sim => }/frv/ftio.cgs | 0 sim/testsuite/{sim => }/frv/ftira.cgs | 0 sim/testsuite/{sim => }/frv/ftiu.cgs | 0 sim/testsuite/{sim => }/frv/ftiue.cgs | 0 sim/testsuite/{sim => }/frv/ftiug.cgs | 0 sim/testsuite/{sim => }/frv/ftiuge.cgs | 0 sim/testsuite/{sim => }/frv/ftiul.cgs | 0 sim/testsuite/{sim => }/frv/ftle.cgs | 0 sim/testsuite/{sim => }/frv/ftlg.cgs | 0 sim/testsuite/{sim => }/frv/ftlt.cgs | 0 sim/testsuite/{sim => }/frv/ftne.cgs | 0 sim/testsuite/{sim => }/frv/ftno.cgs | 0 sim/testsuite/{sim => }/frv/fto.cgs | 0 sim/testsuite/{sim => }/frv/ftra.cgs | 0 sim/testsuite/{sim => }/frv/ftu.cgs | 0 sim/testsuite/{sim => }/frv/ftue.cgs | 0 sim/testsuite/{sim => }/frv/ftug.cgs | 0 sim/testsuite/{sim => }/frv/ftuge.cgs | 0 sim/testsuite/{sim => }/frv/ftul.cgs | 0 sim/testsuite/{sim => }/frv/ftule.cgs | 0 sim/testsuite/{sim => }/frv/grloop.ms | 0 sim/testsuite/{sim => }/frv/hello.ms | 0 sim/testsuite/{sim => }/frv/icei.cgs | 0 sim/testsuite/{sim => }/frv/ici.cgs | 0 sim/testsuite/{sim => }/frv/icpl.cgs | 0 sim/testsuite/{sim => }/frv/icul.cgs | 0 sim/testsuite/{sim => }/frv/interrupts.exp | 0 .../{sim => }/frv/interrupts/Ipipe-fr400.cgs | 0 .../{sim => }/frv/interrupts/Ipipe-fr500.cgs | 0 .../{sim => }/frv/interrupts/badalign-fr550.cgs | 0 .../{sim => }/frv/interrupts/badalign.cgs | 0 .../{sim => }/frv/interrupts/compound-fr550.cgs | 0 .../{sim => }/frv/interrupts/compound.cgs | 0 .../frv/interrupts/data_store_error-fr550.cgs | 0 .../{sim => }/frv/interrupts/data_store_error.cgs | 0 .../frv/interrupts/fp_exception-fr550.cgs | 0 .../{sim => }/frv/interrupts/fp_exception.cgs | 0 sim/testsuite/{sim => }/frv/interrupts/illinsn.cgs | 0 .../frv/interrupts/insn_access_error-fr550.cgs | 0 .../{sim => }/frv/interrupts/insn_access_error.cgs | 0 .../{sim => }/frv/interrupts/mp_exception.cgs | 0 .../frv/interrupts/privileged_instruction.cgs | 0 .../{sim => }/frv/interrupts/regalign.cgs | 0 sim/testsuite/{sim => }/frv/interrupts/reset.cgs | 0 .../{sim => }/frv/interrupts/shadow_regs.cgs | 0 sim/testsuite/{sim => }/frv/interrupts/timer.cgs | 0 sim/testsuite/{sim => }/frv/jmpil.cgs | 0 sim/testsuite/{sim => }/frv/jmpl.cgs | 0 sim/testsuite/{sim => }/frv/jmpl.pcgs | 0 sim/testsuite/{sim => }/frv/ld.cgs | 0 sim/testsuite/{sim => }/frv/ldbf.cgs | 0 sim/testsuite/{sim => }/frv/ldbfi.cgs | 0 sim/testsuite/{sim => }/frv/ldbfu.cgs | 0 sim/testsuite/{sim => }/frv/ldc.cgs | 0 sim/testsuite/{sim => }/frv/ldcu.cgs | 0 sim/testsuite/{sim => }/frv/ldd.cgs | 0 sim/testsuite/{sim => }/frv/lddc.cgs | 0 sim/testsuite/{sim => }/frv/lddcu.cgs | 0 sim/testsuite/{sim => }/frv/lddf.cgs | 0 sim/testsuite/{sim => }/frv/lddfi.cgs | 0 sim/testsuite/{sim => }/frv/lddfu.cgs | 0 sim/testsuite/{sim => }/frv/lddi.cgs | 0 sim/testsuite/{sim => }/frv/lddu.cgs | 0 sim/testsuite/{sim => }/frv/ldf.cgs | 0 sim/testsuite/{sim => }/frv/ldfi.cgs | 0 sim/testsuite/{sim => }/frv/ldfu.cgs | 0 sim/testsuite/{sim => }/frv/ldhf.cgs | 0 sim/testsuite/{sim => }/frv/ldhfi.cgs | 0 sim/testsuite/{sim => }/frv/ldhfu.cgs | 0 sim/testsuite/{sim => }/frv/ldi.cgs | 0 sim/testsuite/{sim => }/frv/ldq.cgs | 0 sim/testsuite/{sim => }/frv/ldqc.cgs | 0 sim/testsuite/{sim => }/frv/ldqcu.cgs | 0 sim/testsuite/{sim => }/frv/ldqf.cgs | 0 sim/testsuite/{sim => }/frv/ldqfi.cgs | 0 sim/testsuite/{sim => }/frv/ldqfu.cgs | 0 sim/testsuite/{sim => }/frv/ldqi.cgs | 0 sim/testsuite/{sim => }/frv/ldqu.cgs | 0 sim/testsuite/{sim => }/frv/ldsb.cgs | 0 sim/testsuite/{sim => }/frv/ldsbi.cgs | 0 sim/testsuite/{sim => }/frv/ldsbu.cgs | 0 sim/testsuite/{sim => }/frv/ldsh.cgs | 0 sim/testsuite/{sim => }/frv/ldshi.cgs | 0 sim/testsuite/{sim => }/frv/ldshu.cgs | 0 sim/testsuite/{sim => }/frv/ldu.cgs | 0 sim/testsuite/{sim => }/frv/ldub.cgs | 0 sim/testsuite/{sim => }/frv/ldubi.cgs | 0 sim/testsuite/{sim => }/frv/ldubu.cgs | 0 sim/testsuite/{sim => }/frv/lduh.cgs | 0 sim/testsuite/{sim => }/frv/lduhi.cgs | 0 sim/testsuite/{sim => }/frv/lduhu.cgs | 0 sim/testsuite/{sim => }/frv/lrbranch.pcgs | 0 sim/testsuite/{sim => }/frv/mabshs.cgs | 0 sim/testsuite/{sim => }/frv/maddhss.cgs | 0 sim/testsuite/{sim => }/frv/maddhus.cgs | 0 sim/testsuite/{sim => }/frv/mand.cgs | 0 sim/testsuite/{sim => }/frv/maveh.cgs | 0 sim/testsuite/{sim => }/frv/mbtoh.cgs | 0 sim/testsuite/{sim => }/frv/mbtohe.cgs | 0 sim/testsuite/{sim => }/frv/mclracc.cgs | 0 sim/testsuite/{sim => }/frv/mcmpsh.cgs | 0 sim/testsuite/{sim => }/frv/mcmpuh.cgs | 0 sim/testsuite/{sim => }/frv/mcop1.cgs | 0 sim/testsuite/{sim => }/frv/mcop2.cgs | 0 sim/testsuite/{sim => }/frv/mcplhi.cgs | 0 sim/testsuite/{sim => }/frv/mcpli.cgs | 0 sim/testsuite/{sim => }/frv/mcpxis.cgs | 0 sim/testsuite/{sim => }/frv/mcpxiu.cgs | 0 sim/testsuite/{sim => }/frv/mcpxrs.cgs | 0 sim/testsuite/{sim => }/frv/mcpxru.cgs | 0 sim/testsuite/{sim => }/frv/mcut.cgs | 0 sim/testsuite/{sim => }/frv/mcuti.cgs | 0 sim/testsuite/{sim => }/frv/mcutss.cgs | 0 sim/testsuite/{sim => }/frv/mcutssi.cgs | 0 sim/testsuite/{sim => }/frv/mdaddaccs.cgs | 0 sim/testsuite/{sim => }/frv/mdasaccs.cgs | 0 sim/testsuite/{sim => }/frv/mdcutssi.cgs | 0 sim/testsuite/{sim => }/frv/mdpackh.cgs | 0 sim/testsuite/{sim => }/frv/mdrotli.cgs | 0 sim/testsuite/{sim => }/frv/mdsubaccs.cgs | 0 sim/testsuite/{sim => }/frv/mdunpackh.cgs | 0 sim/testsuite/{sim => }/frv/membar.cgs | 0 sim/testsuite/{sim => }/frv/mexpdhd.cgs | 0 sim/testsuite/{sim => }/frv/mexpdhw.cgs | 0 sim/testsuite/{sim => }/frv/mhdseth.cgs | 0 sim/testsuite/{sim => }/frv/mhdsets.cgs | 0 sim/testsuite/{sim => }/frv/mhsethih.cgs | 0 sim/testsuite/{sim => }/frv/mhsethis.cgs | 0 sim/testsuite/{sim => }/frv/mhsetloh.cgs | 0 sim/testsuite/{sim => }/frv/mhsetlos.cgs | 0 sim/testsuite/{sim => }/frv/mhtob.cgs | 0 sim/testsuite/{sim => }/frv/misc.exp | 0 sim/testsuite/{sim => }/frv/mmachs.cgs | 0 sim/testsuite/{sim => }/frv/mmachu.cgs | 0 sim/testsuite/{sim => }/frv/mmrdhs.cgs | 0 sim/testsuite/{sim => }/frv/mmrdhu.cgs | 0 sim/testsuite/{sim => }/frv/mmulhs.cgs | 0 sim/testsuite/{sim => }/frv/mmulhu.cgs | 0 sim/testsuite/{sim => }/frv/mmulxhs.cgs | 0 sim/testsuite/{sim => }/frv/mmulxhu.cgs | 0 sim/testsuite/{sim => }/frv/mnop.cgs | 0 sim/testsuite/{sim => }/frv/mnot.cgs | 0 sim/testsuite/{sim => }/frv/mor.cgs | 0 sim/testsuite/{sim => }/frv/mov.cgs | 0 sim/testsuite/{sim => }/frv/movfg.cgs | 0 sim/testsuite/{sim => }/frv/movfgd.cgs | 0 sim/testsuite/{sim => }/frv/movfgq.cgs | 0 sim/testsuite/{sim => }/frv/movgf.cgs | 0 sim/testsuite/{sim => }/frv/movgfd.cgs | 0 sim/testsuite/{sim => }/frv/movgfq.cgs | 0 sim/testsuite/{sim => }/frv/movgs.cgs | 0 sim/testsuite/{sim => }/frv/movsg.cgs | 0 sim/testsuite/{sim => }/frv/mpackh.cgs | 0 sim/testsuite/{sim => }/frv/mqcpxis.cgs | 0 sim/testsuite/{sim => }/frv/mqcpxiu.cgs | 0 sim/testsuite/{sim => }/frv/mqcpxrs.cgs | 0 sim/testsuite/{sim => }/frv/mqcpxru.cgs | 0 sim/testsuite/{sim => }/frv/mqlclrhs.cgs | 0 sim/testsuite/{sim => }/frv/mqlmths.cgs | 0 sim/testsuite/{sim => }/frv/mqmachs.cgs | 0 sim/testsuite/{sim => }/frv/mqmachu.cgs | 0 sim/testsuite/{sim => }/frv/mqmacxhs.cgs | 0 sim/testsuite/{sim => }/frv/mqmulhs.cgs | 0 sim/testsuite/{sim => }/frv/mqmulhu.cgs | 0 sim/testsuite/{sim => }/frv/mqmulxhs.cgs | 0 sim/testsuite/{sim => }/frv/mqmulxhu.cgs | 0 sim/testsuite/{sim => }/frv/mqsaths.cgs | 0 sim/testsuite/{sim => }/frv/mqsllhi.cgs | 0 sim/testsuite/{sim => }/frv/mqsrahi.cgs | 0 sim/testsuite/{sim => }/frv/mqxmachs.cgs | 0 sim/testsuite/{sim => }/frv/mqxmacxhs.cgs | 0 sim/testsuite/{sim => }/frv/mrdacc.cgs | 0 sim/testsuite/{sim => }/frv/mrdaccg.cgs | 0 sim/testsuite/{sim => }/frv/mrotli.cgs | 0 sim/testsuite/{sim => }/frv/mrotri.cgs | 0 sim/testsuite/{sim => }/frv/msaths.cgs | 0 sim/testsuite/{sim => }/frv/msathu.cgs | 0 sim/testsuite/{sim => }/frv/msllhi.cgs | 0 sim/testsuite/{sim => }/frv/msrahi.cgs | 0 sim/testsuite/{sim => }/frv/msrlhi.cgs | 0 sim/testsuite/{sim => }/frv/msubhss.cgs | 0 sim/testsuite/{sim => }/frv/msubhus.cgs | 0 sim/testsuite/{sim => }/frv/mtrap.cgs | 0 sim/testsuite/{sim => }/frv/munpackh.cgs | 0 sim/testsuite/{sim => }/frv/mwcut.cgs | 0 sim/testsuite/{sim => }/frv/mwcuti.cgs | 0 sim/testsuite/{sim => }/frv/mwtacc.cgs | 0 sim/testsuite/{sim => }/frv/mwtaccg.cgs | 0 sim/testsuite/{sim => }/frv/mxor.cgs | 0 sim/testsuite/{sim => }/frv/nandcr.cgs | 0 sim/testsuite/{sim => }/frv/nandncr.cgs | 0 sim/testsuite/{sim => }/frv/nfadds.cgs | 0 sim/testsuite/{sim => }/frv/nfdadds.cgs | 0 sim/testsuite/{sim => }/frv/nfdcmps.cgs | 0 sim/testsuite/{sim => }/frv/nfddivs.cgs | 0 sim/testsuite/{sim => }/frv/nfditos.cgs | 0 sim/testsuite/{sim => }/frv/nfdivs.cgs | 0 sim/testsuite/{sim => }/frv/nfdmadds.cgs | 0 sim/testsuite/{sim => }/frv/nfdmas.cgs | 0 sim/testsuite/{sim => }/frv/nfdmss.cgs | 0 sim/testsuite/{sim => }/frv/nfdmulcs.cgs | 0 sim/testsuite/{sim => }/frv/nfdmuls.cgs | 0 sim/testsuite/{sim => }/frv/nfdsads.cgs | 0 sim/testsuite/{sim => }/frv/nfdsqrts.cgs | 0 sim/testsuite/{sim => }/frv/nfdstoi.cgs | 0 sim/testsuite/{sim => }/frv/nfdsubs.cgs | 0 sim/testsuite/{sim => }/frv/nfitos.cgs | 0 sim/testsuite/{sim => }/frv/nfmadds.cgs | 0 sim/testsuite/{sim => }/frv/nfmas.cgs | 0 sim/testsuite/{sim => }/frv/nfmss.cgs | 0 sim/testsuite/{sim => }/frv/nfmsubs.cgs | 0 sim/testsuite/{sim => }/frv/nfmuls.cgs | 0 sim/testsuite/{sim => }/frv/nfsqrts.cgs | 0 sim/testsuite/{sim => }/frv/nfstoi.cgs | 0 sim/testsuite/{sim => }/frv/nfsubs.cgs | 0 sim/testsuite/{sim => }/frv/nld.cgs | 0 sim/testsuite/{sim => }/frv/nldbf.cgs | 0 sim/testsuite/{sim => }/frv/nldbfi.cgs | 0 sim/testsuite/{sim => }/frv/nldbfu.cgs | 0 sim/testsuite/{sim => }/frv/nldd.cgs | 0 sim/testsuite/{sim => }/frv/nlddf.cgs | 0 sim/testsuite/{sim => }/frv/nlddfi.cgs | 0 sim/testsuite/{sim => }/frv/nlddfu.cgs | 0 sim/testsuite/{sim => }/frv/nlddi.cgs | 0 sim/testsuite/{sim => }/frv/nlddu.cgs | 0 sim/testsuite/{sim => }/frv/nldf.cgs | 0 sim/testsuite/{sim => }/frv/nldfi.cgs | 0 sim/testsuite/{sim => }/frv/nldfu.cgs | 0 sim/testsuite/{sim => }/frv/nldhf.cgs | 0 sim/testsuite/{sim => }/frv/nldhfi.cgs | 0 sim/testsuite/{sim => }/frv/nldhfu.cgs | 0 sim/testsuite/{sim => }/frv/nldi.cgs | 0 sim/testsuite/{sim => }/frv/nldq.cgs | 0 sim/testsuite/{sim => }/frv/nldqf.cgs | 0 sim/testsuite/{sim => }/frv/nldqfi.cgs | 0 sim/testsuite/{sim => }/frv/nldqfu.cgs | 0 sim/testsuite/{sim => }/frv/nldqu.cgs | 0 sim/testsuite/{sim => }/frv/nldsb.cgs | 0 sim/testsuite/{sim => }/frv/nldsbi.cgs | 0 sim/testsuite/{sim => }/frv/nldsbu.cgs | 0 sim/testsuite/{sim => }/frv/nldsh.cgs | 0 sim/testsuite/{sim => }/frv/nldshi.cgs | 0 sim/testsuite/{sim => }/frv/nldshu.cgs | 0 sim/testsuite/{sim => }/frv/nldu.cgs | 0 sim/testsuite/{sim => }/frv/nldub.cgs | 0 sim/testsuite/{sim => }/frv/nldubi.cgs | 0 sim/testsuite/{sim => }/frv/nldubu.cgs | 0 sim/testsuite/{sim => }/frv/nlduh.cgs | 0 sim/testsuite/{sim => }/frv/nlduhi.cgs | 0 sim/testsuite/{sim => }/frv/nlduhu.cgs | 0 sim/testsuite/{sim => }/frv/nop.cgs | 0 sim/testsuite/{sim => }/frv/norcr.cgs | 0 sim/testsuite/{sim => }/frv/norncr.cgs | 0 sim/testsuite/{sim => }/frv/not.cgs | 0 sim/testsuite/{sim => }/frv/notcr.cgs | 0 sim/testsuite/{sim => }/frv/nsdiv.cgs | 0 sim/testsuite/{sim => }/frv/nsdivi.cgs | 0 sim/testsuite/{sim => }/frv/nudiv.cgs | 0 sim/testsuite/{sim => }/frv/nudivi.cgs | 0 sim/testsuite/{sim => }/frv/or.cgs | 0 sim/testsuite/{sim => }/frv/orcc.cgs | 0 sim/testsuite/{sim => }/frv/orcr.cgs | 0 sim/testsuite/{sim => }/frv/ori.cgs | 0 sim/testsuite/{sim => }/frv/oricc.cgs | 0 sim/testsuite/{sim => }/frv/orncr.cgs | 0 sim/testsuite/{sim => }/frv/parallel.exp | 0 sim/testsuite/{sim => }/frv/ret.cgs | 0 sim/testsuite/{sim => }/frv/rett.cgs | 0 sim/testsuite/{sim => }/frv/scan.cgs | 0 sim/testsuite/{sim => }/frv/scani.cgs | 0 sim/testsuite/{sim => }/frv/sdiv.cgs | 0 sim/testsuite/{sim => }/frv/sdivi.cgs | 0 sim/testsuite/{sim => }/frv/sethi.cgs | 0 sim/testsuite/{sim => }/frv/sethilo.pcgs | 0 sim/testsuite/{sim => }/frv/setlo.cgs | 0 sim/testsuite/{sim => }/frv/setlos.cgs | 0 sim/testsuite/{sim => }/frv/sll.cgs | 0 sim/testsuite/{sim => }/frv/sllcc.cgs | 0 sim/testsuite/{sim => }/frv/slli.cgs | 0 sim/testsuite/{sim => }/frv/sllicc.cgs | 0 sim/testsuite/{sim => }/frv/smul.cgs | 0 sim/testsuite/{sim => }/frv/smulcc.cgs | 0 sim/testsuite/{sim => }/frv/smuli.cgs | 0 sim/testsuite/{sim => }/frv/smulicc.cgs | 0 sim/testsuite/{sim => }/frv/sra.cgs | 0 sim/testsuite/{sim => }/frv/sracc.cgs | 0 sim/testsuite/{sim => }/frv/srai.cgs | 0 sim/testsuite/{sim => }/frv/sraicc.cgs | 0 sim/testsuite/{sim => }/frv/srl.cgs | 0 sim/testsuite/{sim => }/frv/srlcc.cgs | 0 sim/testsuite/{sim => }/frv/srli.cgs | 0 sim/testsuite/{sim => }/frv/srlicc.cgs | 0 sim/testsuite/{sim => }/frv/st.cgs | 0 sim/testsuite/{sim => }/frv/stb.cgs | 0 sim/testsuite/{sim => }/frv/stbf.cgs | 0 sim/testsuite/{sim => }/frv/stbfi.cgs | 0 sim/testsuite/{sim => }/frv/stbfu.cgs | 0 sim/testsuite/{sim => }/frv/stbi.cgs | 0 sim/testsuite/{sim => }/frv/stbu.cgs | 0 sim/testsuite/{sim => }/frv/stc.cgs | 0 sim/testsuite/{sim => }/frv/stcu.cgs | 0 sim/testsuite/{sim => }/frv/std.cgs | 0 sim/testsuite/{sim => }/frv/std.pcgs | 0 sim/testsuite/{sim => }/frv/stdc.cgs | 0 sim/testsuite/{sim => }/frv/stdc.pcgs | 0 sim/testsuite/{sim => }/frv/stdcu.cgs | 0 sim/testsuite/{sim => }/frv/stdf.cgs | 0 sim/testsuite/{sim => }/frv/stdf.pcgs | 0 sim/testsuite/{sim => }/frv/stdfi.cgs | 0 sim/testsuite/{sim => }/frv/stdfu.cgs | 0 sim/testsuite/{sim => }/frv/stdi.cgs | 0 sim/testsuite/{sim => }/frv/stdu.cgs | 0 sim/testsuite/{sim => }/frv/stf.cgs | 0 sim/testsuite/{sim => }/frv/stfi.cgs | 0 sim/testsuite/{sim => }/frv/stfu.cgs | 0 sim/testsuite/{sim => }/frv/sth.cgs | 0 sim/testsuite/{sim => }/frv/sthf.cgs | 0 sim/testsuite/{sim => }/frv/sthfi.cgs | 0 sim/testsuite/{sim => }/frv/sthfu.cgs | 0 sim/testsuite/{sim => }/frv/sthi.cgs | 0 sim/testsuite/{sim => }/frv/sthu.cgs | 0 sim/testsuite/{sim => }/frv/sti.cgs | 0 sim/testsuite/{sim => }/frv/stq.cgs | 0 sim/testsuite/{sim => }/frv/stq.pcgs | 0 sim/testsuite/{sim => }/frv/stqc.cgs | 0 sim/testsuite/{sim => }/frv/stqc.pcgs | 0 sim/testsuite/{sim => }/frv/stqcu.cgs | 0 sim/testsuite/{sim => }/frv/stqf.cgs | 0 sim/testsuite/{sim => }/frv/stqf.pcgs | 0 sim/testsuite/{sim => }/frv/stqfi.cgs | 0 sim/testsuite/{sim => }/frv/stqfu.cgs | 0 sim/testsuite/{sim => }/frv/stqi.cgs | 0 sim/testsuite/{sim => }/frv/stqu.cgs | 0 sim/testsuite/{sim => }/frv/stu.cgs | 0 sim/testsuite/{sim => }/frv/sub.cgs | 0 sim/testsuite/{sim => }/frv/subcc.cgs | 0 sim/testsuite/{sim => }/frv/subi.cgs | 0 sim/testsuite/{sim => }/frv/subicc.cgs | 0 sim/testsuite/{sim => }/frv/subx.cgs | 0 sim/testsuite/{sim => }/frv/subxcc.cgs | 0 sim/testsuite/{sim => }/frv/subxi.cgs | 0 sim/testsuite/{sim => }/frv/subxicc.cgs | 0 sim/testsuite/{sim => }/frv/swap.cgs | 0 sim/testsuite/{sim => }/frv/swapi.cgs | 0 sim/testsuite/{sim => }/frv/tc.cgs | 0 sim/testsuite/{sim => }/frv/teq.cgs | 0 sim/testsuite/{sim => }/frv/testutils.inc | 0 sim/testsuite/{sim => }/frv/tge.cgs | 0 sim/testsuite/{sim => }/frv/tgt.cgs | 0 sim/testsuite/{sim => }/frv/thi.cgs | 0 sim/testsuite/{sim => }/frv/tic.cgs | 0 sim/testsuite/{sim => }/frv/tieq.cgs | 0 sim/testsuite/{sim => }/frv/tige.cgs | 0 sim/testsuite/{sim => }/frv/tigt.cgs | 0 sim/testsuite/{sim => }/frv/tihi.cgs | 0 sim/testsuite/{sim => }/frv/tile.cgs | 0 sim/testsuite/{sim => }/frv/tils.cgs | 0 sim/testsuite/{sim => }/frv/tilt.cgs | 0 sim/testsuite/{sim => }/frv/tin.cgs | 0 sim/testsuite/{sim => }/frv/tinc.cgs | 0 sim/testsuite/{sim => }/frv/tine.cgs | 0 sim/testsuite/{sim => }/frv/tino.cgs | 0 sim/testsuite/{sim => }/frv/tinv.cgs | 0 sim/testsuite/{sim => }/frv/tip.cgs | 0 sim/testsuite/{sim => }/frv/tira.cgs | 0 sim/testsuite/{sim => }/frv/tiv.cgs | 0 sim/testsuite/{sim => }/frv/tle.cgs | 0 sim/testsuite/{sim => }/frv/tls.cgs | 0 sim/testsuite/{sim => }/frv/tlt.cgs | 0 sim/testsuite/{sim => }/frv/tn.cgs | 0 sim/testsuite/{sim => }/frv/tnc.cgs | 0 sim/testsuite/{sim => }/frv/tne.cgs | 0 sim/testsuite/{sim => }/frv/tno.cgs | 0 sim/testsuite/{sim => }/frv/tnv.cgs | 0 sim/testsuite/{sim => }/frv/tp.cgs | 0 sim/testsuite/{sim => }/frv/tra.cgs | 0 sim/testsuite/{sim => }/frv/tv.cgs | 0 sim/testsuite/{sim => }/frv/udiv.cgs | 0 sim/testsuite/{sim => }/frv/udivi.cgs | 0 sim/testsuite/{sim => }/frv/umul.cgs | 0 sim/testsuite/{sim => }/frv/umulcc.cgs | 0 sim/testsuite/{sim => }/frv/umuli.cgs | 0 sim/testsuite/{sim => }/frv/umulicc.cgs | 0 sim/testsuite/{sim => }/frv/xor.cgs | 0 sim/testsuite/{sim => }/frv/xorcc.cgs | 0 sim/testsuite/{sim => }/frv/xorcr.cgs | 0 sim/testsuite/{sim => }/frv/xori.cgs | 0 sim/testsuite/{sim => }/frv/xoricc.cgs | 0 sim/testsuite/{sim => }/ft32/ChangeLog | 0 sim/testsuite/{sim => }/ft32/allinsn.exp | 0 sim/testsuite/{sim => }/ft32/basic.s | 0 sim/testsuite/{sim => }/ft32/testutils.inc | 0 sim/testsuite/{sim => }/h8300/ChangeLog | 0 sim/testsuite/{sim => }/h8300/addb.s | 0 sim/testsuite/{sim => }/h8300/addl.s | 0 sim/testsuite/{sim => }/h8300/adds.s | 0 sim/testsuite/{sim => }/h8300/addw.s | 0 sim/testsuite/{sim => }/h8300/addx.s | 0 sim/testsuite/{sim => }/h8300/allinsn.exp | 0 sim/testsuite/{sim => }/h8300/andb.s | 0 sim/testsuite/{sim => }/h8300/andl.s | 0 sim/testsuite/{sim => }/h8300/andw.s | 0 sim/testsuite/{sim => }/h8300/band.s | 0 sim/testsuite/{sim => }/h8300/bfld.s | 0 sim/testsuite/{sim => }/h8300/biand.s | 0 sim/testsuite/{sim => }/h8300/bra.s | 0 sim/testsuite/{sim => }/h8300/brabc.s | 0 sim/testsuite/{sim => }/h8300/bset.s | 0 sim/testsuite/{sim => }/h8300/cmpb.s | 0 sim/testsuite/{sim => }/h8300/cmpl.s | 0 sim/testsuite/{sim => }/h8300/cmpw.s | 0 sim/testsuite/{sim => }/h8300/daa.s | 0 sim/testsuite/{sim => }/h8300/das.s | 0 sim/testsuite/{sim => }/h8300/dec.s | 0 sim/testsuite/{sim => }/h8300/div.s | 0 sim/testsuite/{sim => }/h8300/extl.s | 0 sim/testsuite/{sim => }/h8300/extw.s | 0 sim/testsuite/{sim => }/h8300/inc.s | 0 sim/testsuite/{sim => }/h8300/jmp.s | 0 sim/testsuite/{sim => }/h8300/ldc.s | 0 sim/testsuite/{sim => }/h8300/ldm.s | 0 sim/testsuite/{sim => }/h8300/mac.s | 0 sim/testsuite/{sim => }/h8300/mova.s | 0 sim/testsuite/{sim => }/h8300/movb.s | 0 sim/testsuite/{sim => }/h8300/movl.s | 0 sim/testsuite/{sim => }/h8300/movmd.s | 0 sim/testsuite/{sim => }/h8300/movsd.s | 0 sim/testsuite/{sim => }/h8300/movw.s | 0 sim/testsuite/{sim => }/h8300/mul.s | 0 sim/testsuite/{sim => }/h8300/neg.s | 0 sim/testsuite/{sim => }/h8300/nop.s | 0 sim/testsuite/{sim => }/h8300/not.s | 0 sim/testsuite/{sim => }/h8300/orb.s | 0 sim/testsuite/{sim => }/h8300/orl.s | 0 sim/testsuite/{sim => }/h8300/orw.s | 0 sim/testsuite/{sim => }/h8300/rotl.s | 0 sim/testsuite/{sim => }/h8300/rotr.s | 0 sim/testsuite/{sim => }/h8300/rotxl.s | 0 sim/testsuite/{sim => }/h8300/rotxr.s | 0 sim/testsuite/{sim => }/h8300/shal.s | 0 sim/testsuite/{sim => }/h8300/shar.s | 0 sim/testsuite/{sim => }/h8300/shll.s | 0 sim/testsuite/{sim => }/h8300/shlr.s | 0 sim/testsuite/{sim => }/h8300/stack.s | 0 sim/testsuite/{sim => }/h8300/stc.s | 0 sim/testsuite/{sim => }/h8300/subb.s | 0 sim/testsuite/{sim => }/h8300/subl.s | 0 sim/testsuite/{sim => }/h8300/subs.s | 0 sim/testsuite/{sim => }/h8300/subw.s | 0 sim/testsuite/{sim => }/h8300/subx.s | 0 sim/testsuite/{sim => }/h8300/tas.s | 0 sim/testsuite/{sim => }/h8300/testutils.inc | 0 sim/testsuite/{sim => }/h8300/xorb.s | 0 sim/testsuite/{sim => }/h8300/xorl.s | 0 sim/testsuite/{sim => }/h8300/xorw.s | 0 sim/testsuite/{sim => }/iq2000/ChangeLog | 0 sim/testsuite/{sim => }/iq2000/allinsn.exp | 0 sim/testsuite/{sim => }/iq2000/pass.s | 0 sim/testsuite/{sim => }/iq2000/testutils.inc | 0 sim/testsuite/{sim => }/lm32/ChangeLog | 0 sim/testsuite/{sim => }/lm32/allinsn.exp | 0 sim/testsuite/{sim => }/lm32/pass.s | 0 sim/testsuite/{sim => }/lm32/testutils.inc | 0 sim/testsuite/{sim => }/m32c/ChangeLog | 0 sim/testsuite/{sim => }/m32c/allinsn.exp | 0 sim/testsuite/{sim => }/m32c/blinky.s | 0 sim/testsuite/{sim => }/m32c/fail.s | 0 sim/testsuite/{sim => }/m32c/gloss.s | 0 sim/testsuite/{sim => }/m32c/pass.s | 0 sim/testsuite/{sim => }/m32c/sample.ld | 0 sim/testsuite/{sim => }/m32c/sample.s | 0 sim/testsuite/{sim => }/m32c/sample2.c | 0 sim/testsuite/{sim => }/m32c/testutils.inc | 0 sim/testsuite/{sim => }/m32r/ChangeLog | 0 sim/testsuite/{sim => }/m32r/add.cgs | 0 sim/testsuite/{sim => }/m32r/add3.cgs | 0 sim/testsuite/{sim => }/m32r/addi.cgs | 0 sim/testsuite/{sim => }/m32r/addv.cgs | 0 sim/testsuite/{sim => }/m32r/addv3.cgs | 0 sim/testsuite/{sim => }/m32r/addx.cgs | 0 sim/testsuite/{sim => }/m32r/allinsn.exp | 0 sim/testsuite/{sim => }/m32r/and.cgs | 0 sim/testsuite/{sim => }/m32r/and3.cgs | 0 sim/testsuite/{sim => }/m32r/bc24.cgs | 0 sim/testsuite/{sim => }/m32r/bc8.cgs | 0 sim/testsuite/{sim => }/m32r/beq.cgs | 0 sim/testsuite/{sim => }/m32r/beqz.cgs | 0 sim/testsuite/{sim => }/m32r/bgez.cgs | 0 sim/testsuite/{sim => }/m32r/bgtz.cgs | 0 sim/testsuite/{sim => }/m32r/bl24.cgs | 0 sim/testsuite/{sim => }/m32r/bl8.cgs | 0 sim/testsuite/{sim => }/m32r/blez.cgs | 0 sim/testsuite/{sim => }/m32r/bltz.cgs | 0 sim/testsuite/{sim => }/m32r/bnc24.cgs | 0 sim/testsuite/{sim => }/m32r/bnc8.cgs | 0 sim/testsuite/{sim => }/m32r/bne.cgs | 0 sim/testsuite/{sim => }/m32r/bnez.cgs | 0 sim/testsuite/{sim => }/m32r/bra24.cgs | 0 sim/testsuite/{sim => }/m32r/bra8.cgs | 0 sim/testsuite/{sim => }/m32r/cmp.cgs | 0 sim/testsuite/{sim => }/m32r/cmpi.cgs | 0 sim/testsuite/{sim => }/m32r/cmpu.cgs | 0 sim/testsuite/{sim => }/m32r/cmpui.cgs | 0 sim/testsuite/{sim => }/m32r/div.cgs | 0 sim/testsuite/{sim => }/m32r/divu.cgs | 0 sim/testsuite/{sim => }/m32r/exit47.ms | 0 sim/testsuite/{sim => }/m32r/hello.ms | 0 sim/testsuite/{sim => }/m32r/hw-trap.ms | 0 sim/testsuite/{sim => }/m32r/jl.cgs | 0 sim/testsuite/{sim => }/m32r/jmp.cgs | 0 sim/testsuite/{sim => }/m32r/ld-d.cgs | 0 sim/testsuite/{sim => }/m32r/ld-plus.cgs | 0 sim/testsuite/{sim => }/m32r/ld.cgs | 0 sim/testsuite/{sim => }/m32r/ld24.cgs | 0 sim/testsuite/{sim => }/m32r/ldb-d.cgs | 0 sim/testsuite/{sim => }/m32r/ldb.cgs | 0 sim/testsuite/{sim => }/m32r/ldh-d.cgs | 0 sim/testsuite/{sim => }/m32r/ldh.cgs | 0 sim/testsuite/{sim => }/m32r/ldi16.cgs | 0 sim/testsuite/{sim => }/m32r/ldi8.cgs | 0 sim/testsuite/{sim => }/m32r/ldub-d.cgs | 0 sim/testsuite/{sim => }/m32r/ldub.cgs | 0 sim/testsuite/{sim => }/m32r/lduh-d.cgs | 0 sim/testsuite/{sim => }/m32r/lduh.cgs | 0 sim/testsuite/{sim => }/m32r/lock.cgs | 0 sim/testsuite/{sim => }/m32r/machi.cgs | 0 sim/testsuite/{sim => }/m32r/maclo.cgs | 0 sim/testsuite/{sim => }/m32r/macwhi.cgs | 0 sim/testsuite/{sim => }/m32r/macwlo.cgs | 0 sim/testsuite/{sim => }/m32r/misc.exp | 0 sim/testsuite/{sim => }/m32r/mul.cgs | 0 sim/testsuite/{sim => }/m32r/mulhi.cgs | 0 sim/testsuite/{sim => }/m32r/mullo.cgs | 0 sim/testsuite/{sim => }/m32r/mulwhi.cgs | 0 sim/testsuite/{sim => }/m32r/mulwlo.cgs | 0 sim/testsuite/{sim => }/m32r/mv.cgs | 0 sim/testsuite/{sim => }/m32r/mvfachi.cgs | 0 sim/testsuite/{sim => }/m32r/mvfaclo.cgs | 0 sim/testsuite/{sim => }/m32r/mvfacmi.cgs | 0 sim/testsuite/{sim => }/m32r/mvfc.cgs | 0 sim/testsuite/{sim => }/m32r/mvtachi.cgs | 0 sim/testsuite/{sim => }/m32r/mvtaclo.cgs | 0 sim/testsuite/{sim => }/m32r/mvtc.cgs | 0 sim/testsuite/{sim => }/m32r/neg.cgs | 0 sim/testsuite/{sim => }/m32r/nop.cgs | 0 sim/testsuite/{sim => }/m32r/not.cgs | 0 sim/testsuite/{sim => }/m32r/or.cgs | 0 sim/testsuite/{sim => }/m32r/or3.cgs | 0 sim/testsuite/{sim => }/m32r/rac.cgs | 0 sim/testsuite/{sim => }/m32r/rach.cgs | 0 sim/testsuite/{sim => }/m32r/rem.cgs | 0 sim/testsuite/{sim => }/m32r/remu.cgs | 0 sim/testsuite/{sim => }/m32r/rte.cgs | 0 sim/testsuite/{sim => }/m32r/seth.cgs | 0 sim/testsuite/{sim => }/m32r/sll.cgs | 0 sim/testsuite/{sim => }/m32r/sll3.cgs | 0 sim/testsuite/{sim => }/m32r/slli.cgs | 0 sim/testsuite/{sim => }/m32r/sra.cgs | 0 sim/testsuite/{sim => }/m32r/sra3.cgs | 0 sim/testsuite/{sim => }/m32r/srai.cgs | 0 sim/testsuite/{sim => }/m32r/srl.cgs | 0 sim/testsuite/{sim => }/m32r/srl3.cgs | 0 sim/testsuite/{sim => }/m32r/srli.cgs | 0 sim/testsuite/{sim => }/m32r/st-d.cgs | 0 sim/testsuite/{sim => }/m32r/st-minus.cgs | 0 sim/testsuite/{sim => }/m32r/st-plus.cgs | 0 sim/testsuite/{sim => }/m32r/st.cgs | 0 sim/testsuite/{sim => }/m32r/stb-d.cgs | 0 sim/testsuite/{sim => }/m32r/stb.cgs | 0 sim/testsuite/{sim => }/m32r/sth-d.cgs | 0 sim/testsuite/{sim => }/m32r/sth.cgs | 0 sim/testsuite/{sim => }/m32r/sub.cgs | 0 sim/testsuite/{sim => }/m32r/subv.cgs | 0 sim/testsuite/{sim => }/m32r/subx.cgs | 0 sim/testsuite/{sim => }/m32r/testutils.inc | 0 sim/testsuite/{sim => }/m32r/trap.cgs | 0 sim/testsuite/{sim => }/m32r/unlock.cgs | 0 sim/testsuite/{sim => }/m32r/uread16.ms | 0 sim/testsuite/{sim => }/m32r/uread32.ms | 0 sim/testsuite/{sim => }/m32r/uwrite16.ms | 0 sim/testsuite/{sim => }/m32r/uwrite32.ms | 0 sim/testsuite/{sim => }/m32r/xor.cgs | 0 sim/testsuite/{sim => }/m32r/xor3.cgs | 0 sim/testsuite/{sim => }/m68hc11/ChangeLog | 0 sim/testsuite/{sim => }/m68hc11/allinsn.exp | 0 sim/testsuite/{sim => }/m68hc11/pass.s | 0 sim/testsuite/{sim => }/m68hc11/testutils.inc | 0 sim/testsuite/{sim => }/mcore/ChangeLog | 0 sim/testsuite/{sim => }/mcore/allinsn.exp | 0 sim/testsuite/{sim => }/mcore/fail.s | 0 sim/testsuite/{sim => }/mcore/pass.s | 0 sim/testsuite/{sim => }/mcore/testutils.inc | 0 sim/testsuite/{sim => }/microblaze/ChangeLog | 0 sim/testsuite/{sim => }/microblaze/allinsn.exp | 0 sim/testsuite/{sim => }/microblaze/pass.s | 0 sim/testsuite/{sim => }/microblaze/testutils.inc | 0 sim/testsuite/{sim => }/mips/ChangeLog | 0 sim/testsuite/{sim => }/mips/basic.exp | 0 sim/testsuite/{sim => }/mips/fpu64-ps-sb1.s | 0 sim/testsuite/{sim => }/mips/fpu64-ps.s | 0 sim/testsuite/{sim => }/mips/hilo-hazard-1.s | 0 sim/testsuite/{sim => }/mips/hilo-hazard-2.s | 0 sim/testsuite/{sim => }/mips/hilo-hazard-3.s | 0 sim/testsuite/{sim => }/mips/hilo-hazard-4.s | 0 sim/testsuite/{sim => }/mips/mdmx-ob-sb1.s | 0 sim/testsuite/{sim => }/mips/mdmx-ob.s | 0 sim/testsuite/{sim => }/mips/mips32-dsp.s | 0 sim/testsuite/{sim => }/mips/mips32-dsp2.s | 0 sim/testsuite/{sim => }/mips/sanity.s | 0 sim/testsuite/{sim => }/mips/testutils.inc | 0 sim/testsuite/{sim => }/mips/utils-dsp.inc | 0 sim/testsuite/{sim => }/mips/utils-fpu.inc | 0 sim/testsuite/{sim => }/mips/utils-mdmx.inc | 0 sim/testsuite/{sim => }/mn10300/ChangeLog | 0 sim/testsuite/{sim => }/mn10300/allinsn.exp | 0 sim/testsuite/{sim => }/mn10300/pass.s | 0 sim/testsuite/{sim => }/mn10300/testutils.inc | 0 sim/testsuite/{sim => }/moxie/ChangeLog | 0 sim/testsuite/{sim => }/moxie/allinsn.exp | 0 sim/testsuite/{sim => }/moxie/pass.s | 0 sim/testsuite/{sim => }/moxie/testutils.inc | 0 sim/testsuite/{sim => }/msp430/ChangeLog | 0 sim/testsuite/{sim => }/msp430/add.s | 0 sim/testsuite/{sim => }/msp430/allinsn.exp | 0 sim/testsuite/{sim => }/msp430/mpyull_hwmult.s | 0 sim/testsuite/{sim => }/msp430/rrux.s | 0 sim/testsuite/{sim => }/msp430/testutils.inc | 0 sim/testsuite/{sim => }/or1k/ChangeLog | 0 sim/testsuite/{sim => }/or1k/add.S | 0 sim/testsuite/{sim => }/or1k/adrp.S | 0 sim/testsuite/{sim => }/or1k/alltests.exp | 0 sim/testsuite/{sim => }/or1k/and.S | 0 sim/testsuite/{sim => }/or1k/basic.S | 0 sim/testsuite/{sim => }/or1k/div.S | 0 sim/testsuite/{sim => }/or1k/ext.S | 0 sim/testsuite/{sim => }/or1k/find.S | 0 sim/testsuite/{sim => }/or1k/flag.S | 0 sim/testsuite/{sim => }/or1k/fpu-unordered.S | 0 sim/testsuite/{sim => }/or1k/fpu.S | 0 sim/testsuite/{sim => }/or1k/fpu64a32-unordered.S | 0 sim/testsuite/{sim => }/or1k/fpu64a32.S | 0 sim/testsuite/{sim => }/or1k/jump.S | 0 sim/testsuite/{sim => }/or1k/load.S | 0 sim/testsuite/{sim => }/or1k/mac.S | 0 sim/testsuite/{sim => }/or1k/mfspr.S | 0 sim/testsuite/{sim => }/or1k/mul.S | 0 sim/testsuite/{sim => }/or1k/or.S | 0 sim/testsuite/{sim => }/or1k/or1k-asm-test-env.h | 0 .../{sim => }/or1k/or1k-asm-test-helpers.h | 0 sim/testsuite/{sim => }/or1k/or1k-asm-test.h | 0 sim/testsuite/{sim => }/or1k/or1k-asm.h | 0 sim/testsuite/{sim => }/or1k/or1k-test.ld | 0 sim/testsuite/{sim => }/or1k/ror.S | 0 sim/testsuite/{sim => }/or1k/shift.S | 0 sim/testsuite/{sim => }/or1k/spr-defs.h | 0 sim/testsuite/{sim => }/or1k/sub.S | 0 sim/testsuite/{sim => }/or1k/xor.S | 0 sim/testsuite/{sim => }/pru/ChangeLog | 0 sim/testsuite/{sim => }/pru/add.s | 0 sim/testsuite/{sim => }/pru/allinsn.exp | 0 sim/testsuite/{sim => }/pru/dmem-zero-pass.s | 0 sim/testsuite/{sim => }/pru/dmem-zero-trap.s | 0 sim/testsuite/{sim => }/pru/dram.s | 0 sim/testsuite/{sim => }/pru/jmp.s | 0 sim/testsuite/{sim => }/pru/lmbd.s | 0 sim/testsuite/{sim => }/pru/loop-imm.s | 0 sim/testsuite/{sim => }/pru/loop-reg.s | 0 sim/testsuite/{sim => }/pru/mul.s | 0 sim/testsuite/{sim => }/pru/subreg.s | 0 sim/testsuite/{sim => }/pru/testutils.inc | 0 sim/testsuite/riscv/ChangeLog | 3 + sim/testsuite/riscv/allinsn.exp | 15 + sim/testsuite/riscv/pass.s | 7 + sim/testsuite/riscv/testutils.inc | 52 + sim/testsuite/{sim => }/sh/ChangeLog | 0 sim/testsuite/{sim => }/sh/add.s | 0 sim/testsuite/{sim => }/sh/allinsn.exp | 0 sim/testsuite/{sim => }/sh/and.s | 0 sim/testsuite/{sim => }/sh/bandor.s | 0 sim/testsuite/{sim => }/sh/bandornot.s | 0 sim/testsuite/{sim => }/sh/bclr.s | 0 sim/testsuite/{sim => }/sh/bld.s | 0 sim/testsuite/{sim => }/sh/bldnot.s | 0 sim/testsuite/{sim => }/sh/bset.s | 0 sim/testsuite/{sim => }/sh/bst.s | 0 sim/testsuite/{sim => }/sh/bxor.s | 0 sim/testsuite/{sim => }/sh/clip.s | 0 sim/testsuite/{sim => }/sh/div.s | 0 sim/testsuite/{sim => }/sh/dmxy.s | 0 sim/testsuite/{sim => }/sh/fabs.s | 0 sim/testsuite/{sim => }/sh/fadd.s | 0 sim/testsuite/{sim => }/sh/fail.s | 0 sim/testsuite/{sim => }/sh/fcmpeq.s | 0 sim/testsuite/{sim => }/sh/fcmpgt.s | 0 sim/testsuite/{sim => }/sh/fcnvds.s | 0 sim/testsuite/{sim => }/sh/fcnvsd.s | 0 sim/testsuite/{sim => }/sh/fdiv.s | 0 sim/testsuite/{sim => }/sh/fipr.s | 0 sim/testsuite/{sim => }/sh/fldi0.s | 0 sim/testsuite/{sim => }/sh/fldi1.s | 0 sim/testsuite/{sim => }/sh/flds.s | 0 sim/testsuite/{sim => }/sh/float.s | 0 sim/testsuite/{sim => }/sh/fmac.s | 0 sim/testsuite/{sim => }/sh/fmov.s | 0 sim/testsuite/{sim => }/sh/fmul.s | 0 sim/testsuite/{sim => }/sh/fneg.s | 0 sim/testsuite/{sim => }/sh/fpchg.s | 0 sim/testsuite/{sim => }/sh/frchg.s | 0 sim/testsuite/{sim => }/sh/fsca.s | 0 sim/testsuite/{sim => }/sh/fschg.s | 0 sim/testsuite/{sim => }/sh/fsqrt.s | 0 sim/testsuite/{sim => }/sh/fsrra.s | 0 sim/testsuite/{sim => }/sh/fsub.s | 0 sim/testsuite/{sim => }/sh/ftrc.s | 0 sim/testsuite/{sim => }/sh/ldrc.s | 0 sim/testsuite/{sim => }/sh/loop.s | 0 sim/testsuite/{sim => }/sh/macl.s | 0 sim/testsuite/{sim => }/sh/macw.s | 0 sim/testsuite/{sim => }/sh/mov.s | 0 sim/testsuite/{sim => }/sh/movi.s | 0 sim/testsuite/{sim => }/sh/movli.s | 0 sim/testsuite/{sim => }/sh/movua.s | 0 sim/testsuite/{sim => }/sh/movxy.s | 0 sim/testsuite/{sim => }/sh/mulr.s | 0 sim/testsuite/{sim => }/sh/pabs.s | 0 sim/testsuite/{sim => }/sh/padd.s | 0 sim/testsuite/{sim => }/sh/paddc.s | 0 sim/testsuite/{sim => }/sh/pand.s | 0 sim/testsuite/{sim => }/sh/pass.s | 0 sim/testsuite/{sim => }/sh/pclr.s | 0 sim/testsuite/{sim => }/sh/pdec.s | 0 sim/testsuite/{sim => }/sh/pdmsb.s | 0 sim/testsuite/{sim => }/sh/pinc.s | 0 sim/testsuite/{sim => }/sh/pmuls.s | 0 sim/testsuite/{sim => }/sh/prnd.s | 0 sim/testsuite/{sim => }/sh/pshai.s | 0 sim/testsuite/{sim => }/sh/pshar.s | 0 sim/testsuite/{sim => }/sh/pshli.s | 0 sim/testsuite/{sim => }/sh/pshlr.s | 0 sim/testsuite/{sim => }/sh/psub.s | 0 sim/testsuite/{sim => }/sh/pswap.s | 0 sim/testsuite/{sim => }/sh/pushpop.s | 0 sim/testsuite/{sim => }/sh/resbank.s | 0 sim/testsuite/{sim => }/sh/sett.s | 0 sim/testsuite/{sim => }/sh/shll.s | 0 sim/testsuite/{sim => }/sh/shll16.s | 0 sim/testsuite/{sim => }/sh/shll2.s | 0 sim/testsuite/{sim => }/sh/shll8.s | 0 sim/testsuite/{sim => }/sh/shlr.s | 0 sim/testsuite/{sim => }/sh/shlr16.s | 0 sim/testsuite/{sim => }/sh/shlr2.s | 0 sim/testsuite/{sim => }/sh/shlr8.s | 0 sim/testsuite/{sim => }/sh/swap.s | 0 sim/testsuite/{sim => }/sh/testutils.inc | 0 sim/testsuite/sim/bfin/ChangeLog | 370 - sim/testsuite/sim/bfin/s21.s | 298 - sim/testsuite/{sim => }/v850/ChangeLog | 0 sim/testsuite/{sim => }/v850/allinsns.exp | 0 sim/testsuite/{sim => }/v850/bsh.cgs | 0 sim/testsuite/{sim => }/v850/div.cgs | 0 sim/testsuite/{sim => }/v850/divh.cgs | 0 sim/testsuite/{sim => }/v850/divh_3.cgs | 0 sim/testsuite/{sim => }/v850/divhu.cgs | 0 sim/testsuite/{sim => }/v850/divu.cgs | 0 sim/testsuite/{sim => }/v850/sar.cgs | 0 sim/testsuite/{sim => }/v850/satadd.cgs | 0 sim/testsuite/{sim => }/v850/satsub.cgs | 0 sim/testsuite/{sim => }/v850/satsubi.cgs | 0 sim/testsuite/{sim => }/v850/satsubr.cgs | 0 sim/testsuite/{sim => }/v850/shl.cgs | 0 sim/testsuite/{sim => }/v850/shr.cgs | 0 sim/testsuite/{sim => }/v850/testutils.cgs | 0 sim/testsuite/{sim => }/v850/testutils.inc | 0 sim/v850/ChangeLog | 23 +- sim/v850/configure | 228 +- sim/v850/configure.ac | 1 - sim/v850/interp.c | 2 - sim/v850/simops.c | 3 +- 3942 files changed, 39211 insertions(+), 15439 deletions(-) delete mode 100644 gas/testsuite/gas/all/byte.d delete mode 100644 gas/testsuite/gas/all/byte.l delete mode 100644 gas/testsuite/gas/all/byte.s create mode 100644 gas/testsuite/gas/elf/pr27228.d create mode 100644 gas/testsuite/gas/elf/pr27228.s delete mode 100644 gas/testsuite/gas/elf/warn-2.s create mode 100644 gas/testsuite/gas/i386/pr27198.d create mode 100644 gas/testsuite/gas/i386/pr27198.err create mode 100644 gas/testsuite/gas/i386/pr27198.s create mode 100644 gas/testsuite/gas/nios2/relax.d create mode 100644 gas/testsuite/gas/nios2/relax.s delete mode 100644 gas/testsuite/gas/riscv/bitmanip-insns-32.d delete mode 100644 gas/testsuite/gas/riscv/bitmanip-insns-64.d delete mode 100644 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}/bfin/c_dsp32shift_expexp_r.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_fdepx.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_fextx.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lf.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_ln.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_lp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_rn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_rp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lmix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ones.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_pack.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_rot.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_rot_mix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_signbits_r.s (100%) rename sim/testsuite/{sim => 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rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahh_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_amix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lf.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_ln.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_lp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_rn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_rp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lmix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_rot.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_ippm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drhi_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drhi_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drlo_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drlo_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_ippm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drhi_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drhi_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drlo_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drlo_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_except_illopcode.S (100%) rename sim/testsuite/{sim => }/bfin/c_except_sys_sstep.S (100%) rename sim/testsuite/{sim => }/bfin/c_except_user_mode.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_disable.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_disable_enable.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_excpt.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_loopsetup_stld.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_nested.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_nmi.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_pending.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_pending_2.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_timer.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_timer_reload.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_timer_tcount.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_timer_tscale.S (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_drhi.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_drlo.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_ibml.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_ibml.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_ibml.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lzhi_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lzhi_ibml.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lzhi_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_pibml.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_xb.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_xh.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_xb.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_xh.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_ppmm_hbx.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_xb.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_xh.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_p_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_p_p_mm.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_p_p_pp.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_mm.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_mm_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_mm_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_pp.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_pp_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_pp_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_p_mm.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_p_pp.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_xb.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_xh.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dr_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dr_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_st_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_ld_dr_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_ld_dr_xh.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_ld_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_ld_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_st_dr_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_st_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_st_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstiifp_ld_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstiifp_ld_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstiifp_st_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstiifp_st_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_dr_hi.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_dr_lo.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_h_xh.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_lohi.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_st_dr_hi.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_st_dr_lo.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_st_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_st_lohi.s (100%) rename sim/testsuite/{sim => }/bfin/c_linkage.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_alshft_mix.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_arith_shft.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_bitclr.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_bitset.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_bittgl.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_bittst.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_log_l_shft.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_log_l_shft_astat.S (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_log_r_shft.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_log_r_shft_astat.S (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_nbittst.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_nested.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_nested_bot.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_nested_prelc.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_nested_top.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_overlap.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_div2_lc0.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_div2_lc1.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_lc0.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_lc1.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_stld.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_prelc.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_topbotcntr.s (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_interr_ctl.s (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_loop.S (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_loop_user_except.S (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_ppop_illegal_adr.S (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_ppopm_illegal_adr.S (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_timer.S (100%) rename sim/testsuite/{sim => }/bfin/c_mode_supervisor.S (100%) rename sim/testsuite/{sim => }/bfin/c_mode_user.S (100%) rename sim/testsuite/{sim => }/bfin/c_mode_user_superivsor.S (100%) rename sim/testsuite/{sim => }/bfin/c_multi_issue_dsp_ld_ld.s (100%) rename sim/testsuite/{sim => }/bfin/c_multi_issue_dsp_ldst_1.s (100%) rename sim/testsuite/{sim => }/bfin/c_multi_issue_dsp_ldst_2.s (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_call_pcpr.s (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_call_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_clisti_interr.S (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_csync_mmr.S (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_except_rtx.S (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_excpt.S (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_jump_pcpr.s (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_jump_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_nop.s (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_raise_rt_i_n.S (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_rts.s (100%) rename sim/testsuite/{sim => }/bfin/c_ptr2op_pr_neg_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ptr2op_pr_sft_2_1.s (100%) rename sim/testsuite/{sim => }/bfin/c_ptr2op_pr_shadd_1_2.s (100%) rename sim/testsuite/{sim => }/bfin/c_pushpopmultiple_dp.s (100%) rename sim/testsuite/{sim => }/bfin/c_pushpopmultiple_dp_pair.s (100%) rename sim/testsuite/{sim => }/bfin/c_pushpopmultiple_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_pushpopmultiple_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_acc_acc.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_dag_lz_dep.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_dr_acc_acc.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_dr_dep_nostall.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_dr_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_dr_imlb.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_dr_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_imlb_dep_nostall.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_imlb_dep_stall.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_imlb_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_imlb_imlb.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_imlb_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_pr_dep_nostall.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_pr_dep_stall.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_pr_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_pr_imlb.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_pr_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ac_raise_mv.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ac_raise_mv_ppop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ac_regmv_pushpop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_dec_raise_pushpop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex1_brcc_mv_pop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex1_call_mv_pop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex1_j_mv_pop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex1_raise_brcc_mv_pop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex1_raise_call_mv_pop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex1_raise_j_mv_pop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex2_brcc_mp_mv_pop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex2_mmr_mvpop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex2_mmrj_mvpop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex2_raise_mmr_mvpop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex2_raise_mmrj_mvpop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex3_ls_brcc_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex3_ls_mmr_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex3_ls_mmrj_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex3_raise_ls_mmrj_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_wb_cs_lsmmrj_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_wb_raisecs_lsmmrj_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_wb_rti_lsmmrj_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_wb_rtn_lsmmrj_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_wb_rtx_lsmmrj_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_ujump.s (100%) rename sim/testsuite/{sim => }/bfin/cc-alu.S (100%) rename sim/testsuite/{sim => }/bfin/cc-astat-bits.s (100%) rename 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sim/testsuite/{sim => }/cris/c/exitg2.c (100%) rename sim/testsuite/{sim => }/cris/c/fcntl1.c (100%) rename sim/testsuite/{sim => }/cris/c/fcntl2.c (100%) rename sim/testsuite/{sim => }/cris/c/fdopen1.c (100%) rename sim/testsuite/{sim => }/cris/c/fdopen2.c (100%) rename sim/testsuite/{sim => }/cris/c/freopen1.c (100%) rename sim/testsuite/{sim => }/cris/c/freopen2.c (100%) rename sim/testsuite/{sim => }/cris/c/ftruncate1.c (100%) rename sim/testsuite/{sim => }/cris/c/ftruncate2.c (100%) rename sim/testsuite/{sim => }/cris/c/getcwd1.c (100%) rename sim/testsuite/{sim => }/cris/c/gettod.c (100%) rename sim/testsuite/{sim => }/cris/c/hello.c (100%) rename sim/testsuite/{sim => }/cris/c/helloaout.c (100%) rename sim/testsuite/{sim => }/cris/c/hellodyn.c (100%) rename sim/testsuite/{sim => }/cris/c/hellodyn2.c (100%) rename sim/testsuite/{sim => }/cris/c/hellodyn3.c (100%) rename sim/testsuite/{sim => }/cris/c/kill1.c (100%) rename sim/testsuite/{sim => }/cris/c/kill2.c (100%) rename sim/testsuite/{sim => }/cris/c/kill3.c (100%) rename sim/testsuite/{sim => }/cris/c/mapbrk.c (100%) rename sim/testsuite/{sim => }/cris/c/mmap1.c (100%) rename sim/testsuite/{sim => }/cris/c/mmap2.c (100%) rename sim/testsuite/{sim => }/cris/c/mmap3.c (100%) rename sim/testsuite/{sim => }/cris/c/mmap4.c (100%) rename sim/testsuite/{sim => }/cris/c/mmap5.c (100%) rename sim/testsuite/{sim => }/cris/c/mmap6.c (100%) rename sim/testsuite/{sim => }/cris/c/mmap7.c (100%) rename sim/testsuite/{sim => }/cris/c/mmap8.c (100%) rename sim/testsuite/{sim => }/cris/c/mprotect1.c (100%) rename sim/testsuite/{sim => }/cris/c/mprotect2.c (100%) rename sim/testsuite/{sim => }/cris/c/mremap.c (100%) rename sim/testsuite/{sim => }/cris/c/openpf1.c (100%) rename sim/testsuite/{sim => }/cris/c/openpf2.c (100%) rename sim/testsuite/{sim => }/cris/c/openpf3.c (100%) rename sim/testsuite/{sim => }/cris/c/openpf4.c (100%) rename sim/testsuite/{sim => }/cris/c/openpf5.c (100%) rename sim/testsuite/{sim => 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rename sim/testsuite/{sim => }/cris/c/sjlj.c (100%) rename sim/testsuite/{sim => }/cris/c/sock1.c (100%) rename sim/testsuite/{sim => }/cris/c/stat1.c (100%) rename sim/testsuite/{sim => }/cris/c/stat2.c (100%) rename sim/testsuite/{sim => }/cris/c/stat3.c (100%) rename sim/testsuite/{sim => }/cris/c/stat4.c (100%) rename sim/testsuite/{sim => }/cris/c/stat5.c (100%) rename sim/testsuite/{sim => }/cris/c/stat7.c (100%) rename sim/testsuite/{sim => }/cris/c/stat8.c (100%) rename sim/testsuite/{sim => }/cris/c/syscall1.c (100%) rename sim/testsuite/{sim => }/cris/c/syscall2.c (100%) rename sim/testsuite/{sim => }/cris/c/syscall3.c (100%) rename sim/testsuite/{sim => }/cris/c/syscall4.c (100%) rename sim/testsuite/{sim => }/cris/c/syscall5.c (100%) rename sim/testsuite/{sim => }/cris/c/syscall6.c (100%) rename sim/testsuite/{sim => }/cris/c/syscall7.c (100%) rename sim/testsuite/{sim => }/cris/c/syscall8.c (100%) rename sim/testsuite/{sim => }/cris/c/sysctl1.c (100%) rename sim/testsuite/{sim => }/cris/c/sysctl2.c (100%) rename sim/testsuite/{sim => }/cris/c/sysctl3.c (100%) rename sim/testsuite/{sim => }/cris/c/thread2.c (100%) rename sim/testsuite/{sim => }/cris/c/thread3.c (100%) rename sim/testsuite/{sim => }/cris/c/thread4.c (100%) rename sim/testsuite/{sim => }/cris/c/thread5.c (100%) rename sim/testsuite/{sim => }/cris/c/time1.c (100%) rename sim/testsuite/{sim => }/cris/c/time2.c (100%) rename sim/testsuite/{sim => }/cris/c/truncate1.c (100%) rename sim/testsuite/{sim => }/cris/c/truncate2.c (100%) rename sim/testsuite/{sim => }/cris/c/ugetrlimit1.c (100%) rename sim/testsuite/{sim => }/cris/c/uname1.c (100%) rename sim/testsuite/{sim => }/cris/c/writev1.c (100%) rename sim/testsuite/{sim => }/cris/c/writev2.c (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/host1.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq1.ms (100%) rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/irq2.ms (100%) rename sim/testsuite/{sim => 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rename sim/testsuite/{sim => }/frv/candcc.cgs (100%) rename sim/testsuite/{sim => }/frv/ccalll.cgs (100%) rename sim/testsuite/{sim => }/frv/cckc.cgs (100%) rename sim/testsuite/{sim => }/frv/cckeq.cgs (100%) rename sim/testsuite/{sim => }/frv/cckge.cgs (100%) rename sim/testsuite/{sim => }/frv/cckgt.cgs (100%) rename sim/testsuite/{sim => }/frv/cckhi.cgs (100%) rename sim/testsuite/{sim => }/frv/cckle.cgs (100%) rename sim/testsuite/{sim => }/frv/cckls.cgs (100%) rename sim/testsuite/{sim => }/frv/ccklt.cgs (100%) rename sim/testsuite/{sim => }/frv/cckn.cgs (100%) rename sim/testsuite/{sim => }/frv/ccknc.cgs (100%) rename sim/testsuite/{sim => }/frv/cckne.cgs (100%) rename sim/testsuite/{sim => }/frv/cckno.cgs (100%) rename sim/testsuite/{sim => }/frv/ccknv.cgs (100%) rename sim/testsuite/{sim => }/frv/cckp.cgs (100%) rename sim/testsuite/{sim => }/frv/cckra.cgs (100%) rename sim/testsuite/{sim => }/frv/cckv.cgs (100%) rename sim/testsuite/{sim => }/frv/ccmp.cgs (100%) rename sim/testsuite/{sim => }/frv/cfabss.cgs (100%) rename sim/testsuite/{sim => }/frv/cfadds.cgs (100%) rename sim/testsuite/{sim => }/frv/cfckeq.cgs (100%) rename sim/testsuite/{sim => }/frv/cfckge.cgs (100%) rename sim/testsuite/{sim => }/frv/cfckgt.cgs (100%) rename sim/testsuite/{sim => }/frv/cfckle.cgs (100%) rename sim/testsuite/{sim => }/frv/cfcklg.cgs (100%) rename sim/testsuite/{sim => }/frv/cfcklt.cgs (100%) rename sim/testsuite/{sim => }/frv/cfckne.cgs (100%) rename sim/testsuite/{sim => }/frv/cfckno.cgs (100%) rename sim/testsuite/{sim => }/frv/cfcko.cgs (100%) rename sim/testsuite/{sim => }/frv/cfckra.cgs (100%) rename sim/testsuite/{sim => }/frv/cfcku.cgs (100%) rename sim/testsuite/{sim => }/frv/cfckue.cgs (100%) rename sim/testsuite/{sim => }/frv/cfckug.cgs (100%) rename sim/testsuite/{sim => }/frv/cfckuge.cgs (100%) rename sim/testsuite/{sim => }/frv/cfckul.cgs (100%) rename sim/testsuite/{sim => }/frv/cfckule.cgs (100%) rename sim/testsuite/{sim => }/frv/cfcmps.cgs (100%) rename sim/testsuite/{sim => }/frv/cfdivs.cgs (100%) rename sim/testsuite/{sim => }/frv/cfitos.cgs (100%) rename sim/testsuite/{sim => }/frv/cfmadds.cgs (100%) rename sim/testsuite/{sim => }/frv/cfmas.cgs (100%) rename sim/testsuite/{sim => }/frv/cfmovs.cgs (100%) rename sim/testsuite/{sim => }/frv/cfmss.cgs (100%) rename sim/testsuite/{sim => }/frv/cfmsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/cfmuls.cgs (100%) rename sim/testsuite/{sim => }/frv/cfnegs.cgs (100%) rename sim/testsuite/{sim => }/frv/cfsqrts.cgs (100%) rename sim/testsuite/{sim => }/frv/cfstoi.cgs (100%) rename sim/testsuite/{sim => }/frv/cfsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/cjmpl.cgs (100%) rename sim/testsuite/{sim => }/frv/ckc.cgs (100%) rename sim/testsuite/{sim => }/frv/ckeq.cgs (100%) rename sim/testsuite/{sim => }/frv/ckge.cgs (100%) rename sim/testsuite/{sim => }/frv/ckgt.cgs (100%) rename sim/testsuite/{sim => }/frv/ckhi.cgs (100%) rename sim/testsuite/{sim => }/frv/ckle.cgs (100%) rename sim/testsuite/{sim => }/frv/ckls.cgs (100%) rename sim/testsuite/{sim => }/frv/cklt.cgs (100%) rename sim/testsuite/{sim => }/frv/ckn.cgs (100%) rename sim/testsuite/{sim => }/frv/cknc.cgs (100%) rename sim/testsuite/{sim => }/frv/ckne.cgs (100%) rename sim/testsuite/{sim => }/frv/ckno.cgs (100%) rename sim/testsuite/{sim => }/frv/cknv.cgs (100%) rename sim/testsuite/{sim => }/frv/ckp.cgs (100%) rename sim/testsuite/{sim => }/frv/ckra.cgs (100%) rename sim/testsuite/{sim => }/frv/ckv.cgs (100%) rename sim/testsuite/{sim => }/frv/cld.cgs (100%) rename sim/testsuite/{sim => }/frv/cldbf.cgs (100%) rename sim/testsuite/{sim => }/frv/cldbfu.cgs (100%) rename sim/testsuite/{sim => }/frv/cldd.cgs (100%) rename sim/testsuite/{sim => }/frv/clddf.cgs (100%) rename sim/testsuite/{sim => }/frv/clddfu.cgs (100%) rename sim/testsuite/{sim => }/frv/clddu.cgs (100%) rename sim/testsuite/{sim => }/frv/cldf.cgs (100%) rename sim/testsuite/{sim => }/frv/cldfu.cgs (100%) rename sim/testsuite/{sim => }/frv/cldhf.cgs (100%) rename sim/testsuite/{sim => }/frv/cldhfu.cgs (100%) rename sim/testsuite/{sim => }/frv/cldq.cgs (100%) rename sim/testsuite/{sim => }/frv/cldqu.cgs (100%) rename sim/testsuite/{sim => }/frv/cldsb.cgs (100%) rename sim/testsuite/{sim => }/frv/cldsbu.cgs (100%) rename sim/testsuite/{sim => }/frv/cldsh.cgs (100%) rename sim/testsuite/{sim => }/frv/cldshu.cgs (100%) rename sim/testsuite/{sim => }/frv/cldu.cgs (100%) rename sim/testsuite/{sim => }/frv/cldub.cgs (100%) rename sim/testsuite/{sim => }/frv/cldubu.cgs (100%) rename sim/testsuite/{sim => }/frv/clduh.cgs (100%) rename sim/testsuite/{sim => }/frv/clduhu.cgs (100%) rename sim/testsuite/{sim => }/frv/clrfa.cgs (100%) rename sim/testsuite/{sim => }/frv/clrfr.cgs (100%) rename sim/testsuite/{sim => }/frv/clrga.cgs (100%) rename sim/testsuite/{sim => }/frv/clrgr.cgs (100%) rename sim/testsuite/{sim => }/frv/cmaddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/cmaddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/cmand.cgs (100%) rename sim/testsuite/{sim => }/frv/cmbtoh.cgs (100%) rename sim/testsuite/{sim => }/frv/cmbtohe.cgs (100%) rename sim/testsuite/{sim => }/frv/cmcpxis.cgs (100%) rename sim/testsuite/{sim => }/frv/cmcpxiu.cgs (100%) rename sim/testsuite/{sim => }/frv/cmcpxrs.cgs (100%) rename sim/testsuite/{sim => }/frv/cmcpxru.cgs (100%) rename sim/testsuite/{sim => }/frv/cmexpdhd.cgs (100%) rename sim/testsuite/{sim => }/frv/cmexpdhw.cgs (100%) rename sim/testsuite/{sim => }/frv/cmhtob.cgs (100%) rename sim/testsuite/{sim => }/frv/cmmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/cmmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/cmmulhs.cgs (100%) rename sim/testsuite/{sim => }/frv/cmmulhu.cgs (100%) rename sim/testsuite/{sim => }/frv/cmnot.cgs (100%) rename sim/testsuite/{sim => }/frv/cmor.cgs (100%) rename sim/testsuite/{sim => }/frv/cmov.cgs (100%) rename sim/testsuite/{sim => }/frv/cmovfg.cgs (100%) rename sim/testsuite/{sim => }/frv/cmovfgd.cgs (100%) rename sim/testsuite/{sim => }/frv/cmovgf.cgs (100%) rename sim/testsuite/{sim => }/frv/cmovgfd.cgs (100%) rename sim/testsuite/{sim => }/frv/cmp.cgs (100%) rename sim/testsuite/{sim => }/frv/cmpb.cgs (100%) rename sim/testsuite/{sim => }/frv/cmpba.cgs (100%) rename sim/testsuite/{sim => }/frv/cmpi.cgs (100%) rename sim/testsuite/{sim => }/frv/cmqmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/cmqmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/cmqmulhs.cgs (100%) rename sim/testsuite/{sim => }/frv/cmqmulhu.cgs (100%) rename sim/testsuite/{sim => }/frv/cmsubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/cmsubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/cmxor.cgs (100%) rename sim/testsuite/{sim => }/frv/cnot.cgs (100%) rename sim/testsuite/{sim => }/frv/commitfa.cgs (100%) rename sim/testsuite/{sim => }/frv/commitfr.cgs (100%) rename sim/testsuite/{sim => }/frv/commitga.cgs (100%) rename sim/testsuite/{sim => }/frv/commitgr.cgs (100%) rename sim/testsuite/{sim => }/frv/cop1.cgs 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sim/testsuite/{sim => }/frv/cstdf.cgs (100%) rename sim/testsuite/{sim => }/frv/cstdfu.cgs (100%) rename sim/testsuite/{sim => }/frv/cstdu.cgs (100%) rename sim/testsuite/{sim => }/frv/cstf.cgs (100%) rename sim/testsuite/{sim => }/frv/cstfu.cgs (100%) rename sim/testsuite/{sim => }/frv/csth.cgs (100%) rename sim/testsuite/{sim => }/frv/csthf.cgs (100%) rename sim/testsuite/{sim => }/frv/csthfu.cgs (100%) rename sim/testsuite/{sim => }/frv/csthu.cgs (100%) rename sim/testsuite/{sim => }/frv/cstq.cgs (100%) rename sim/testsuite/{sim => }/frv/cstu.cgs (100%) rename sim/testsuite/{sim => }/frv/csub.cgs (100%) rename sim/testsuite/{sim => }/frv/csubcc.cgs (100%) rename sim/testsuite/{sim => }/frv/cswap.cgs (100%) rename sim/testsuite/{sim => }/frv/cudiv.cgs (100%) rename sim/testsuite/{sim => }/frv/cxor.cgs (100%) rename sim/testsuite/{sim => }/frv/cxorcc.cgs (100%) rename sim/testsuite/{sim => }/frv/dcef.cgs (100%) rename sim/testsuite/{sim => }/frv/dcei.cgs (100%) rename sim/testsuite/{sim => }/frv/dcf.cgs (100%) rename sim/testsuite/{sim => }/frv/dci.cgs (100%) rename sim/testsuite/{sim => }/frv/exit47.ms (100%) rename sim/testsuite/{sim => }/frv/fabsd.cgs (100%) rename sim/testsuite/{sim => }/frv/fabss.cgs (100%) rename sim/testsuite/{sim => }/frv/faddd.cgs (100%) rename sim/testsuite/{sim => }/frv/fadds.cgs (100%) rename sim/testsuite/{sim => }/frv/fbeq.cgs (100%) rename sim/testsuite/{sim => }/frv/fbeqlr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbge.cgs (100%) rename sim/testsuite/{sim => }/frv/fbgelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbgt.cgs (100%) rename sim/testsuite/{sim => }/frv/fbgtlr.cgs (100%) rename sim/testsuite/{sim => }/frv/fble.cgs (100%) rename sim/testsuite/{sim => }/frv/fblelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fblg.cgs (100%) rename sim/testsuite/{sim => }/frv/fblglr.cgs (100%) rename sim/testsuite/{sim => }/frv/fblt.cgs (100%) rename sim/testsuite/{sim => }/frv/fbltlr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbne.cgs (100%) rename sim/testsuite/{sim => }/frv/fbnelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbno.cgs (100%) rename sim/testsuite/{sim => }/frv/fbnolr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbo.cgs (100%) rename sim/testsuite/{sim => }/frv/fbolr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbra.cgs (100%) rename sim/testsuite/{sim => }/frv/fbralr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbu.cgs (100%) rename sim/testsuite/{sim => }/frv/fbue.cgs (100%) rename sim/testsuite/{sim => }/frv/fbuelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbug.cgs (100%) rename sim/testsuite/{sim => }/frv/fbuge.cgs (100%) rename sim/testsuite/{sim => }/frv/fbugelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbuglr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbul.cgs (100%) rename sim/testsuite/{sim => }/frv/fbule.cgs (100%) rename sim/testsuite/{sim => }/frv/fbulelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbullr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbulr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbeqlr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbgelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbgtlr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcblelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcblglr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbltlr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbnelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbnolr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbolr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbralr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbuelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbugelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbuglr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbulelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbullr.cgs (100%) rename sim/testsuite/{sim => }/frv/fcbulr.cgs (100%) rename sim/testsuite/{sim => }/frv/fckeq.cgs (100%) rename sim/testsuite/{sim => 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=> }/frv/fmad.cgs (100%) rename sim/testsuite/{sim => }/frv/fmaddd.cgs (100%) rename sim/testsuite/{sim => }/frv/fmadds.cgs (100%) rename sim/testsuite/{sim => }/frv/fmas.cgs (100%) rename sim/testsuite/{sim => }/frv/fmovd.cgs (100%) rename sim/testsuite/{sim => }/frv/fmovs.cgs (100%) rename sim/testsuite/{sim => }/frv/fmsd.cgs (100%) rename sim/testsuite/{sim => }/frv/fmss.cgs (100%) rename sim/testsuite/{sim => }/frv/fmsubd.cgs (100%) rename sim/testsuite/{sim => }/frv/fmsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/fmuld.cgs (100%) rename sim/testsuite/{sim => }/frv/fmuls.cgs (100%) rename sim/testsuite/{sim => }/frv/fnegd.cgs (100%) rename sim/testsuite/{sim => }/frv/fnegs.cgs (100%) rename sim/testsuite/{sim => }/frv/fnop.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/addss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/allinsn.exp (100%) rename sim/testsuite/{sim => }/frv/fr400/csdiv.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/maddaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/masaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/maveh.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mclracc.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhdseth.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhdsets.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhsethih.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhsethis.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhsetloh.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhsetlos.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/movgs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/movsg.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/msubaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/scutss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/sdiv.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/sdivi.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/slass.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/smass.cgs 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}/frv/fr550/mqmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqmacxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqsubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqsubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqxmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqxmacxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/msubaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/msubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/msubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mtrap.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/udiv.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/udivi.cgs (100%) rename sim/testsuite/{sim => }/frv/fsqrtd.cgs (100%) rename sim/testsuite/{sim => }/frv/fsqrts.cgs (100%) rename sim/testsuite/{sim => }/frv/fstoi.cgs (100%) rename sim/testsuite/{sim => }/frv/fsubd.cgs (100%) rename sim/testsuite/{sim => }/frv/fsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/fteq.cgs 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