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from 4ab36e8e562 x86: Add g++.target/i386/pr103750.C new b437418bc95 RISC-V: Add pattern for vector-scalar multiply-add/sub [PR119100] new 5566b20dd5f RISC-V: Use helper function to get FPR to VR move cost new 036660001db libstdc++: Remove redundant macro checks in std.cc.in new f12151e527d libstdc++: Use explicit cast to unsigned in std::rotr and s [...] new 4db88b963b0 libstdc++: Replace some implicit conversions in std::vector
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Summary of changes: gcc/config/riscv/autovec-opt.md | 52 +++ gcc/config/riscv/riscv-opts.h | 1 + gcc/config/riscv/riscv-protos.h | 1 + gcc/config/riscv/riscv-vector-costs.cc | 4 +- gcc/config/riscv/riscv.cc | 44 ++- gcc/config/riscv/riscv.opt | 4 + .../gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c | 10 + .../gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c | 10 + .../gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c | 10 + .../gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c | 10 + .../gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c | 10 + .../gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c | 10 + .../gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c | 10 + .../gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c | 10 + .../gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c | 10 + .../gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c | 10 + .../gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c | 10 + .../gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c | 10 + .../gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop.h | 61 +++ .../riscv/rvv/autovec/vx_vf/vf_mulop_data.h | 413 +++++++++++++++++++++ .../riscv/rvv/autovec/vx_vf/vf_mulop_run.h | 34 ++ .../riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c | 15 + .../riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f32.c | 15 + .../riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f64.c | 15 + .../riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c | 15 + .../riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f32.c | 15 + .../riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f64.c | 15 + libstdc++-v3/include/bits/stl_vector.h | 6 +- libstdc++-v3/include/bits/vector.tcc | 2 +- libstdc++-v3/include/std/bit | 4 +- libstdc++-v3/src/c++23/std.cc.in | 8 - 31 files changed, 822 insertions(+), 22 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop_data.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop_run.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f64.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f64.c