[Tcwg-commits] [toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-defconfig updated (48ad8194a56 -> afd03cd3358)

25 Dec 2020


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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-defconfig
in repository toolchain/ci/llvm-project.
from  48ad8194a56 [IRSim] Adding support for isomorphic predicates
      adds  db7a2f347f1 Precommit transform tests that have poison as insertelement [...]
      adds  30365472489 Precommit analysis/etc tests for inselt poison placeholder
      adds  9939cf5a564 [ExecutionEngine, Linker] Use erase_if (NFC)
      adds  200b15af45a [Analysis] Remove spliceFunction (NFC)
      adds  b8cb1802a8a [obj2yaml] - Dump the content of a broken GNU hash table properly.
      adds  90177912a4d Revert "[InstCombine] Fold gep inbounds of null to null"
      adds  61177943c9c [AMDGPU] Use MUBUF instructions for global address space access
      adds  e0751234ef0 [CodeGen] Add "noreturn" attirbute to _Unwind_Resume
      adds  ef2f843347b Revert "[InstCombine] Check inbounds in load/store of gep n [...]
      adds  ce4413e4894 Moved dwarf_eh_resume.ll from Generic to X86 folder
      adds  fb468953082 [Support] Explicitly state that KnownBits::getMinValue/getM [...]
      adds  6895581fd2c [Support] Add KnownBits::getSignedMinValue/getSignedMaxValu [...]
      adds  89abe1cf83a [InstCombine] foldICmpUsingKnownBits - use KnownBits signed [...]
      adds  df812115e3c [CodeGen, Transforms] Use llvm::any_of (NFC)
      adds  e457896a6ef [CodeGen] Remove unused function hasInlineAsmMemConstraint (NFC)
      adds  ff3749fc793 [NFC] SimplifyCFGOpt::simplifyUnreachable(): pacify unused  [...]
      adds  b3021a72a6d [IR][InstCombine] Add m_ImmConstant(), that matches on non- [...]
      adds  da4c7e15df3 [NFC][InstCombine] Autogenerate check lines in vec_shuffle.ll test
      adds  1fda23367d4 [NFC][InstCombine] Add test for `a & ~(a ^ b)` pattern
      adds  5b78303433c [InstCombine] Fold `a & ~(a ^ b)` to `x & y`
      adds  8001dcbd50c [NFC][InstCombine] Add test coverage for `(x ^ C) ^ y` pattern
      adds  d9ebaeeb468 [InstCombine] Hoist xor-by-constant from xor-by-value
      adds  6e074a8324d [NFC][LoopIdiom] Improve test coverage for 'left-shift-unti [...]
      adds  25aebe2ccfb [LoopIdiom] 'left-shift-until-bittest': keep no-wrap flags  [...]
       new  afd03cd3358 [RISCV] Define vector single-width reduction intrinsic.
The 1 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails.  The revisions
listed as "adds" were already present in the repository and have only
been added to this reference.
Summary of changes:
 llvm/docs/AMDGPUUsage.rst                          |    5 +
 llvm/include/llvm/Analysis/CallGraph.h             |    7 -
 llvm/include/llvm/CodeGen/Analysis.h               |    5 -
 llvm/include/llvm/IR/IntrinsicsRISCV.td            |   35 +
 llvm/include/llvm/IR/PatternMatch.h                |   43 +-
 llvm/include/llvm/Support/KnownBits.h              |   24 +-
 llvm/lib/Analysis/CallGraph.cpp                    |   14 -
 llvm/lib/CodeGen/Analysis.cpp                      |   21 -
 llvm/lib/CodeGen/DwarfEHPrepare.cpp                |    2 +
 llvm/lib/CodeGen/GlobalISel/LegalityPredicates.cpp |    9 +-
 llvm/lib/CodeGen/MultiHazardRecognizer.cpp         |    7 +-
 llvm/lib/ExecutionEngine/SectionMemoryManager.cpp  |    8 +-
 llvm/lib/Linker/IRMover.cpp                        |    3 +-
 llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp         |   34 +-
 llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h           |   23 +-
 llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td    |  128 +-
 .../Transforms/InstCombine/InstCombineAddSub.cpp   |    4 +-
 .../Transforms/InstCombine/InstCombineAndOrXor.cpp |   15 +
 .../Transforms/InstCombine/InstCombineCalls.cpp    |    4 +-
 .../Transforms/InstCombine/InstCombineCompares.cpp |   51 +-
 .../InstCombine/InstCombineLoadStoreAlloca.cpp     |   24 +-
 .../Transforms/InstCombine/InstCombineNegator.cpp  |    3 +-
 .../InstCombine/InstructionCombining.cpp           |   14 +-
 .../Instrumentation/ControlHeightReduction.cpp     |    7 +-
 llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp  |   50 +-
 llvm/lib/Transforms/Utils/CodeMoverUtils.cpp       |   45 +-
 llvm/lib/Transforms/Utils/SimplifyCFG.cpp          |    1 +
 llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp    |    6 +-
 .../CostModel/AArch64/kryo-inseltpoison.ll         |   26 +
 .../PowerPC/insert_extract-inseltpoison.ll         |  187 +
 .../CostModel/SystemZ/vectorinstrs-inseltpoison.ll |   56 +
 .../X86/insert-extract-at-zero-inseltpoison.ll     |   40 +
 .../Analysis/CostModel/X86/loop_v2-inseltpoison.ll |   39 +
 .../X86/masked-intrinsic-cost-inseltpoison.ll      | 1911 ++++++++++
 .../CostModel/X86/uniformshift-inseltpoison.ll     |   39 +
 .../CostModel/X86/vector-insert-inseltpoison.ll    | 1270 +++++++
 .../CostModel/X86/vector_gep-inseltpoison.ll       |   17 +
 .../CostModel/X86/vshift-ashr-cost-inseltpoison.ll | 1843 ++++++++++
 .../CostModel/X86/vshift-lshr-cost-inseltpoison.ll | 1867 ++++++++++
 .../CostModel/X86/vshift-shl-cost-inseltpoison.ll  | 2197 +++++++++++
 .../Analysis/DemandedBits/vectors-inseltpoison.ll  |  136 +
 .../irtranslator-invoke-probabilities.ll           |    2 +-
 llvm/test/CodeGen/AMDGPU/lower-kernargs.ll         |    5 +-
 llvm/test/CodeGen/AMDGPU/memory-legalizer-fence.ll |    2 +-
 .../AMDGPU/memory-legalizer-global-agent.ll        |  838 ++---
 .../AMDGPU/memory-legalizer-global-nontemporal.ll  |   18 +-
 .../AMDGPU/memory-legalizer-global-singlethread.ll |  838 ++---
 .../AMDGPU/memory-legalizer-global-system.ll       |  838 ++---
 .../AMDGPU/memory-legalizer-global-wavefront.ll    |  838 ++---
 .../AMDGPU/memory-legalizer-global-workgroup.ll    |  838 ++---
 .../CodeGen/AMDGPU/memory-legalizer-local-agent.ll |  402 +-
 .../AMDGPU/memory-legalizer-local-nontemporal.ll   |   38 +-
 .../AMDGPU/memory-legalizer-local-singlethread.ll  |  402 +-
 .../AMDGPU/memory-legalizer-local-system.ll        |  402 +-
 .../AMDGPU/memory-legalizer-local-wavefront.ll     |  402 +-
 .../AMDGPU/memory-legalizer-local-workgroup.ll     |  402 +-
 .../AMDGPU/memory-legalizer-private-nontemporal.ll |   78 +-
 llvm/test/CodeGen/RISCV/rvv/vfredmax-rv32.ll       |  463 +++
 llvm/test/CodeGen/RISCV/rvv/vfredmax-rv64.ll       |  631 ++++
 llvm/test/CodeGen/RISCV/rvv/vfredmin-rv32.ll       |  463 +++
 llvm/test/CodeGen/RISCV/rvv/vfredmin-rv64.ll       |  631 ++++
 llvm/test/CodeGen/RISCV/rvv/vfredosum-rv32.ll      |  463 +++
 llvm/test/CodeGen/RISCV/rvv/vfredosum-rv64.ll      |  631 ++++
 llvm/test/CodeGen/RISCV/rvv/vfredsum-rv32.ll       |  463 +++
 llvm/test/CodeGen/RISCV/rvv/vfredsum-rv64.ll       |  631 ++++
 llvm/test/CodeGen/RISCV/rvv/vredand-rv32.ll        |  715 ++++
 llvm/test/CodeGen/RISCV/rvv/vredand-rv64.ll        |  883 +++++
 llvm/test/CodeGen/RISCV/rvv/vredmax-rv32.ll        |  715 ++++
 llvm/test/CodeGen/RISCV/rvv/vredmax-rv64.ll        |  883 +++++
 llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv32.ll       |  715 ++++
 llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv64.ll       |  883 +++++
 llvm/test/CodeGen/RISCV/rvv/vredmin-rv32.ll        |  715 ++++
 llvm/test/CodeGen/RISCV/rvv/vredmin-rv64.ll        |  883 +++++
 llvm/test/CodeGen/RISCV/rvv/vredminu-rv32.ll       |  715 ++++
 llvm/test/CodeGen/RISCV/rvv/vredminu-rv64.ll       |  883 +++++
 llvm/test/CodeGen/RISCV/rvv/vredor-rv32.ll         |  715 ++++
 llvm/test/CodeGen/RISCV/rvv/vredor-rv64.ll         |  883 +++++
 llvm/test/CodeGen/RISCV/rvv/vredsum-rv32.ll        |  715 ++++
 llvm/test/CodeGen/RISCV/rvv/vredsum-rv64.ll        |  883 +++++
 llvm/test/CodeGen/RISCV/rvv/vredxor-rv32.ll        |  715 ++++
 llvm/test/CodeGen/RISCV/rvv/vredxor-rv64.ll        |  883 +++++
 llvm/test/CodeGen/X86/dwarf_eh_resume.ll           |   23 +
 .../X86/stack-value-piece-inseltpoison.ll          |  114 +
 llvm/test/Other/scalable-vectors-core-ir.ll        |   12 +-
 .../Attributor/dereferenceable-2-inseltpoison.ll   |  847 +++++
 llvm/test/Transforms/BDCE/vectors-inseltpoison.ll  |  102 +
 .../AArch64/gather-scatter-opt-inseltpoison.ll     |  113 +
 .../bypass-slow-div-debug-info-inseltpoison.ll     |   76 +
 .../ARM/sink-add-mul-shufflevector-inseltpoison.ll |  219 ++
 .../CodeGenPrepare/ARM/sinkchain-inseltpoison.ll   |  107 +
 .../X86/gather-scatter-opt-inseltpoison.ll         |  113 +
 .../X86/sink-addrmode-inseltpoison.ll              |  321 ++
 .../CodeGenPrepare/X86/vec-shift-inseltpoison.ll   |  406 +++
 .../X86/x86-shuffle-sink-inseltpoison.ll           |  257 ++
 .../2016-08-30-MaskedScatterGather-inseltpoison.ll |   42 +
 ...xpr-vector-constainsundef-crash-inseltpoison.ll |   25 +
 .../GVN/non-integral-pointers-inseltpoison.ll      |  456 +++
 .../AMDGPU/old-pass-regressions-inseltpoison.ll    |  143 +
 .../dereferenceable-inseltpoison.ll                |  357 ++
 .../AArch64/sve-bitcast-inseltpoison.ll            |   13 +
 .../amdgcn-demanded-vector-elts-inseltpoison.ll    | 3828 ++++++++++++++++++++
 .../InstCombine/X86/x86-addsub-inseltpoison.ll     |  194 +
 .../InstCombine/X86/x86-avx512-inseltpoison.ll     | 3407 +++++++++++++++++
 .../InstCombine/X86/x86-pack-inseltpoison.ll       |  635 ++++
 .../InstCombine/X86/x86-sse-inseltpoison.ll        |  694 ++++
 .../InstCombine/X86/x86-sse2-inseltpoison.ll       |  541 +++
 .../InstCombine/X86/x86-sse41-inseltpoison.ll      |  124 +
 .../X86/x86-vec_demanded_elts-inseltpoison.ll      |  110 +
 .../X86/x86-vector-shifts-inseltpoison.ll          | 3783 +++++++++++++++++++
 .../InstCombine/X86/x86-xop-inseltpoison.ll        |  305 ++
 llvm/test/Transforms/InstCombine/and-xor-or.ll     |   43 +
 .../Transforms/InstCombine/bitcast-inseltpoison.ll |  573 +++
 .../InstCombine/bitcast-vec-canon-inseltpoison.ll  |  167 +
 .../InstCombine/broadcast-inseltpoison.ll          |  179 +
 .../InstCombine/extractelement-inseltpoison.ll     |  332 ++
 .../InstCombine/fold-vector-zero-inseltpoison.ll   |   35 +
 llvm/test/Transforms/InstCombine/getelementptr.ll  |    6 +-
 .../hoist-xor-by-constant-from-xor-by-value.ll     |   75 +
 .../InstCombine/icmp-bc-vec-inseltpoison.ll        |  127 +
 .../InstCombine/inselt-binop-inseltpoison.ll       |  635 ++++
 .../insert-extract-shuffle-inseltpoison.ll         |  735 ++++
 .../invert-variable-mask-in-masked-merge-scalar.ll |    5 +-
 .../invert-variable-mask-in-masked-merge-vector.ll |    5 +-
 llvm/test/Transforms/InstCombine/load.ll           |    5 +-
 .../InstCombine/masked_intrinsics-inseltpoison.ll  |  271 ++
 llvm/test/Transforms/InstCombine/or-xor.ll         |   68 +-
 .../Transforms/InstCombine/pr38984-inseltpoison.ll |   41 +
 .../InstCombine/scalarization-inseltpoison.ll      |  335 ++
 .../select-extractelement-inseltpoison.ll          |  213 ++
 .../InstCombine/shift-add-inseltpoison.ll          |  122 +
 .../shufflevector-div-rem-inseltpoison.ll          |  122 +
 llvm/test/Transforms/InstCombine/store.ll          |    5 +-
 .../trunc-extractelement-inseltpoison.ll           |  195 +
 .../InstCombine/udiv-pow2-vscale-inseltpoison.ll   |   27 +
 .../unfold-masked-merge-with-const-mask-scalar.ll  |    6 +-
 .../unfold-masked-merge-with-const-mask-vector.ll  |    6 +-
 .../InstCombine/vec_demanded_elts-inseltpoison.ll  |  850 +++++
 .../vec_extract_var_elt-inseltpoison.ll            |   26 +
 .../InstCombine/vec_gep_scalar_arg-inseltpoison.ll |   16 +
 .../InstCombine/vec_phi_extract-inseltpoison.ll    |  107 +
 ...{vec_shuffle.ll => vec_shuffle-inseltpoison.ll} |   36 +-
 llvm/test/Transforms/InstCombine/vec_shuffle.ll    |   12 +-
 .../InstCombine/vector-casts-inseltpoison.ll       |  413 +++
 .../InstCombine/vector_gep1-inseltpoison.ll        |   74 +
 .../vector_insertelt_shuffle-inseltpoison.ll       |   93 +
 .../vscale_extractelement-inseltpoison.ll          |  185 +
 .../vscale_insertelement-inseltpoison.ll           |  102 +
 llvm/test/Transforms/InstCombine/xor2.ll           |   44 +-
 .../ConstProp/InsertElement-inseltpoison.ll        |   52 +
 .../InstSimplify/ConstProp/vscale-inseltpoison.ll  |  301 ++
 .../ConstProp/vscale-shufflevector-inseltpoison.ll |   39 +
 .../Transforms/InstSimplify/select-inseltpoison.ll | 1007 +++++
 .../Transforms/InstSimplify/vscale-inseltpoison.ll |  199 +
 .../AMDGPU/selects-inseltpoison.ll                 |   95 +
 .../X86/load-width-inseltpoison.ll                 |   40 +
 .../X86/vectorize-i8-nested-add-inseltpoison.ll    |  165 +
 .../LoopIdiom/X86/left-shift-until-bittest.ll      | 1875 +++++-----
 .../ARM/vctp-chains-inseltpoison.ll                |  257 ++
 .../p8-unrolling-legalize-vectors-inseltpoison.ll  |  256 ++
 ...08-30-MaskedScatterGather-xfail-inseltpoison.ll |   43 +
 .../PGOProfile/counter_promo_nest-inseltpoison.ll  |  165 +
 .../PhaseOrdering/X86/addsub-inseltpoison.ll       |  101 +
 .../PhaseOrdering/X86/horiz-math-inseltpoison.ll   |  153 +
 .../X86/scalarization-inseltpoison.ll              |   71 +
 .../PhaseOrdering/vector-trunc-inseltpoison.ll     |   23 +
 .../base-vector-inseltpoison.ll                    |  279 ++
 .../check_traversal_order-inseltpoison.ll          |   38 +
 .../live-vector-nosplit-inseltpoison.ll            |  119 +
 .../accelerate-vector-functions-inseltpoison.ll    | 1300 +++++++
 .../AArch64/insertelement-inseltpoison.ll          |   44 +
 .../AArch64/transpose-inseltpoison.ll              |  294 ++
 .../AMDGPU/add_sub_sat-inseltpoison.ll             |  336 ++
 .../SLPVectorizer/AMDGPU/bswap-inseltpoison.ll     |   38 +
 .../SLPVectorizer/AMDGPU/round-inseltpoison.ll     |   38 +
 .../ARM/extract-insert-inseltpoison.ll             |   31 +
 .../non-vectorizable-intrinsic-inseltpoison.ll     |   57 +
 .../SLPVectorizer/X86/PR35865-inseltpoison.ll      |   29 +
 .../X86/alternate-calls-inseltpoison.ll            |   65 +
 .../X86/alternate-cast-inseltpoison.ll             |  466 +++
 .../SLPVectorizer/X86/alternate-fp-inseltpoison.ll |  179 +
 .../X86/alternate-int-inseltpoison.ll              |  497 +++
 .../SLPVectorizer/X86/arith-fp-inseltpoison.ll     | 1365 +++++++
 .../X86/blending-shuffle-inseltpoison.ll           |  200 +
 .../SLPVectorizer/X86/cmp_commute-inseltpoison.ll  |  283 ++
 .../X86/crash_scheduling-inseltpoison.ll           |   81 +
 .../X86/external_user_jumbled_load-inseltpoison.ll |   43 +
 .../X86/extract-shuffle-inseltpoison.ll            |   22 +
 .../SLPVectorizer/X86/fptosi-inseltpoison.ll       |  534 +++
 .../SLPVectorizer/X86/hadd-inseltpoison.ll         |  433 +++
 .../SLPVectorizer/X86/hsub-inseltpoison.ll         |  433 +++
 .../insert-element-build-vector-inseltpoison.ll    |  540 +++
 .../SLPVectorizer/X86/load-merge-inseltpoison.ll   |  208 ++
 .../SLPVectorizer/X86/pr31599-inseltpoison.ll      |   30 +
 .../SLPVectorizer/X86/pr42022-inseltpoison.ll      |  278 ++
 .../SLPVectorizer/X86/pr44067-inseltpoison.ll      |  118 +
 .../SLPVectorizer/X86/pr47629-inseltpoison.ll      |  664 ++++
 .../SLPVectorizer/X86/sext-inseltpoison.ll         | 1039 ++++++
 .../SLPVectorizer/X86/sign-extend-inseltpoison.ll  |   62 +
 .../SLPVectorizer/X86/sitofp-inseltpoison.ll       | 1331 +++++++
 .../SLPVectorizer/X86/value-bug-inseltpoison.ll    |  108 +
 .../X86/vec_list_bias-inseltpoison.ll              |  105 +
 .../SLPVectorizer/X86/zext-inseltpoison.ll         | 1123 ++++++
 .../vectorizable-functions-inseltpoison.ll         |   78 +
 .../Transforms/Scalarizer/basic-inseltpoison.ll    |  561 +++
 .../Scalarizer/dbgloc-bug-inseltpoison.ll          |   44 +
 .../Scalarizer/order-bug-inseltpoison.ll           |   24 +
 .../ARM/speculate-vector-ops-inseltpoison.ll       |  112 +
 .../speculate-vector-ops-inseltpoison.ll           |   60 +
 .../spec-other-inseltpoison.ll                     |   88 +
 .../rebuild-ssa-infinite-loop-inseltpoison.ll      |   53 +
 .../AMDGPU/as-transition-inseltpoison.ll           |   36 +
 .../VectorCombine/Hexagon/load-inseltpoison.ll     |   17 +
 .../X86/extract-binop-inseltpoison.ll              |  575 +++
 .../VectorCombine/X86/insert-binop-inseltpoison.ll |  234 ++
 .../X86/insert-binop-with-constant-inseltpoison.ll |  728 ++++
 .../VectorCombine/X86/load-inseltpoison.ll         |  649 ++++
 .../X86/scalarize-cmp-inseltpoison.ll              |  290 ++
 llvm/test/tools/obj2yaml/ELF/gnu-hash-section.yaml |   21 +-
 llvm/tools/obj2yaml/elf2yaml.cpp                   |    4 +-
 llvm/unittests/Support/KnownBitsTest.cpp           |   14 +
 220 files changed, 74337 insertions(+), 4284 deletions(-)
 create mode 100644 llvm/test/Analysis/CostModel/AArch64/kryo-inseltpoison.ll
 create mode 100644 llvm/test/Analysis/CostModel/PowerPC/insert_extract-inseltpoison.ll
 create mode 100644 llvm/test/Analysis/CostModel/SystemZ/vectorinstrs-inseltpoison.ll
 create mode 100644 llvm/test/Analysis/CostModel/X86/insert-extract-at-zero-inseltp [...]
 create mode 100644 llvm/test/Analysis/CostModel/X86/loop_v2-inseltpoison.ll
 create mode 100644 llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost-inseltpoison.ll
 create mode 100644 llvm/test/Analysis/CostModel/X86/uniformshift-inseltpoison.ll
 create mode 100644 llvm/test/Analysis/CostModel/X86/vector-insert-inseltpoison.ll
 create mode 100644 llvm/test/Analysis/CostModel/X86/vector_gep-inseltpoison.ll
 create mode 100644 llvm/test/Analysis/CostModel/X86/vshift-ashr-cost-inseltpoison.ll
 create mode 100644 llvm/test/Analysis/CostModel/X86/vshift-lshr-cost-inseltpoison.ll
 create mode 100644 llvm/test/Analysis/CostModel/X86/vshift-shl-cost-inseltpoison.ll
 create mode 100644 llvm/test/Analysis/DemandedBits/vectors-inseltpoison.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredmax-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredmax-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredmin-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredmin-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredosum-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredosum-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredsum-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredsum-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredand-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredand-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredmax-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredmax-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredmin-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredmin-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredminu-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredminu-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredor-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredor-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredsum-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredsum-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredxor-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredxor-rv64.ll
 create mode 100644 llvm/test/CodeGen/X86/dwarf_eh_resume.ll
 create mode 100644 llvm/test/DebugInfo/X86/stack-value-piece-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/Attributor/dereferenceable-2-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/BDCE/vectors-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/CodeGenPrepare/AArch64/gather-scatter-opt- [...]
 create mode 100644 llvm/test/Transforms/CodeGenPrepare/AMDGPU/bypass-slow-div-debu [...]
 create mode 100644 llvm/test/Transforms/CodeGenPrepare/ARM/sink-add-mul-shufflevec [...]
 create mode 100644 llvm/test/Transforms/CodeGenPrepare/ARM/sinkchain-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/CodeGenPrepare/X86/gather-scatter-opt-inse [...]
 create mode 100644 llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/CodeGenPrepare/X86/vec-shift-inseltpoison.ll
 create mode 100644 llvm/test/Transforms/CodeGenPrepare/X86/x86-shuffle-sink-inselt [...]
 create mode 100644 llvm/test/Transforms/GVN/2016-08-30-MaskedScatterGather-inseltp [...]
 create mode 100644 llvm/test/Transforms/GVN/constexpr-vector-constainsundef-crash- [...]
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[Tcwg-commits] [toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-defconfig updated (48ad8194a56 -> afd03cd3358)