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from 2bd791038b5 [TableGen] Give the option of tolerating duplicate register names new e65af32d44f [RISCV] MC layer support for the standard RV32F instruction [...]
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Summary of changes: lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 36 +++++ .../RISCV/Disassembler/RISCVDisassembler.cpp | 25 +++ lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp | 12 +- lib/Target/RISCV/InstPrinter/RISCVInstPrinter.h | 4 + lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h | 58 ++++++- lib/Target/RISCV/RISCV.td | 6 + lib/Target/RISCV/RISCVInstrFormats.td | 47 +++++- lib/Target/RISCV/RISCVInstrInfo.td | 1 + lib/Target/RISCV/RISCVInstrInfoF.td | 167 +++++++++++++++++++++ lib/Target/RISCV/RISCVRegisterInfo.td | 52 +++++++ lib/Target/RISCV/RISCVSubtarget.h | 2 + test/MC/RISCV/rv32f-invalid.s | 29 ++++ test/MC/RISCV/rv32f-valid.s | 164 ++++++++++++++++++++ test/MC/RISCV/rv32i-invalid.s | 4 + 14 files changed, 594 insertions(+), 13 deletions(-) create mode 100644 lib/Target/RISCV/RISCVInstrInfoF.td create mode 100644 test/MC/RISCV/rv32f-invalid.s create mode 100644 test/MC/RISCV/rv32f-valid.s