[Tcwg-commits] [llvm] branch master updated (638f42a216c -> 2d481c770a9)

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from 638f42a216c Revert r342494 as it was failing on a bot and the author ca [...] new 50dce07c8dd [WebAssembly] v4f32.abs and v2f64.abs new 9a1a4ca8cef [XRay][compiler-rt] FDRLogWriter Abstraction new b064c24e4a2 ScheduleDAG: Cleanup dumping code; NFC new b4967025822 AArch64MacroFusion: Factor out some opcode handling code; NFC new b74b9fdb9a2 [WebAssembly][NFC] Remove extra space in WebAssemblyInstrSIMD.td new aef051374a9 [DWARF Verifier] Add helper function to dump DIEs. [NFC] new e8654dabcf8 [DebugInfo][Dexter] Speculated BB presents illegal variable [...] new 94083e06715 [X86][SSE] Update extractelement test in preparation for D52140 new c75b449af65 [COFF] Emit @feat.00 on 64-bit and set the CFG bit when emi [...] new 2fdd5d38064 [RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32A new ab1155a38d3 [ADT][BitVector] Add push_back() new 60bebed7a91 [TableGen] CodeGenDAGPatterns::GenerateVariants - use BitVe [...] new 45e19861a8e Verify commit access in fixing typo new fd06cb2db23 [InstCombine] Don't transform sin/cos -> tanl if for half types new f02ce8dcad4 [TableGen] CodeGenDAGPatterns::GenerateVariants - use BitVe [...] new fa4dbf77f1d [New PM] Introducing PassInstrumentation framework new bb4c3570003 [ARM] Fix unwind information for floating point registers new 74e3c34a76f [InstCombine] foldICmpWithLowBitMaskedVal(): handle ~(-1 < [...] new 47c99e0a969 [InstCombine] foldICmpWithLowBitMaskedVal(): handle uncanon [...] new 7795456d9e4 [InstCombine] foldICmpWithLowBitMaskedVal(): handle uncanon [...] new 80b0618b4c8 [benchmark] Cherrypick fix for MinGW/ARM from upstream new 490f68fb298 [AtomicExpandPass]: Add a hook for custom cmpxchg expansion in IR new 3b4fa0d0339 Fix -Wsign-compare warnings. NFCI new 68fc66e3d30 Revert rL342544: [New PM] Introducing PassInstrumentation f [...] new dcc25258ae6 [DAGCombiner][x86] add transform/hook to decompose integer [...] new a9c15c18d50 [TableGen][SubtargetEmitter] Add the ability for processor [...] new bf6ec206615 [bpf] Symbol sizes and types in object file new 76c0cf65821 [AMDGPU] Add instruction selection for i1 to f16 conversion new eb2ecf38ab4 Attempt to unbreak buidlbot lld-x86_64-darwin13 after r342555. new 8ea1c2fe6a3 [X86] Add initial SimplifyDemandedVectorEltsForTargetNode support new 563a3bbd658 [LLJIT] Add API to expose linking layer from LLJIT classes new bb017fb10f9 [mips][microMIPS] Fix the definition of MOVEP instruction new d4b73063533 [mips][microMIPS] Extending size reduction pass with MOVEP new 3c27669a0d7 [ThinLTO] Extract getReferencedTypeIds from [NFC] new 6e5f07e0421 [ThinLTO] Write TYPE_IDs for types used in functions import [...] new 3a89b36622b [x86] change names of vector splitting helper functions; NFC new 9de32f78e1c Copy utilities updated and added for MI flags new 71589ff6720 [X86] Handle COPYs of physregs better (regalloc hints) new be08b55fc5f [InstCombine] Disable strcmp->memcmp transform for MSan. new f9cabb9ebf9 [ARM] Refactor Exynos feature set (NFC) new b044a64d277 [ARM] Adjust the feature set for Exynos new 55025c47718 Workaround a limitation of llvm::Any when used with types t [...] new 9214de517ed MachineScheduler: Add -misched-print-dags flag new 98f7c2ba4a9 AArch64: Add FuseCryptoEOR fusion rules new e48b2117883 [x86] add test for add+not vector fold; NFC new 2327768f69d Fix the build when LLVM_TARGETS_TO_BUILD is empty. new fe5554490ad [SelectionDAG] allow vector types with isBitwiseNot() new de66c77d885 [x86] add test for 256-bit andn (PR37749); NFC new c3779f52e63 Revert "[XRay][compiler-rt] FDRLogWriter Abstraction" and 1 more. new 5ffd6db668e [New PM] Introducing PassInstrumentation framework new eddbfad05ce [WEB] add new flags to a DebugInfo lit test new 776583c82b8 [WebAssembly] Renumber SIMD ops new 5dd1dd3856e [PowerPC] Fix the assert of combineBVOfConsecutiveLoads whe [...] new 6bf5f37c12c [unittests] Do not use llvm::sort in googlemock new f68a67ad961 Fix for bug 34002 - label generated before it block is fina [...] new 85a14f04918 Temporarily Revert "[New PM] Introducing PassInstrumentatio [...] new ba88c3a89a7 [XRay][compiler-rt] FDRLogWriter Abstraction new 32a3289434c [MachineVerifier] Relax checkLivenessAtDef regarding dead s [...] new 3f24abff843 Improve the doc about the initial commit email sent to the ML new e1f5d9d40de [NFC][x86][AArch64] Add BEXTR-like test patterns. new b5fa23ba6e5 [RISCV][MC] Improve parsing of jal/j operands new 44db1d1e245 [IR] Add a boolean field in DILocation to know if a line mu [...] new 0b774f63bca [IPSCCP] Fix a problem with removing labels in a switch wit [...] new 37d99d3dedb [DWARF] - Emit the correct value for DW_AT_addr_base. new fc05216ee6a [ADT] Try again to use the same version of llvm::Optional o [...] new 0bc4e615841 Fix line-endings. NFCI. new 21164cc5a55 Fix -Wdocumentation warnings introduced by r342555. NFC new d4dc55135e9 [RISCV][MC] Modify evaluateConstantImm interface to allow r [...] new eda0de3f051 [X86][SSE] Remove PSHUFLW/PSHUFHW combineRedundantHalfShuff [...] new f724c01683a [ADT] Bring back memmove to make GCC 5.4 happy new db98902adc6 [llvm-exegesis] Improve Register Setup (roll forward of D51856). new be9fcb899f8 [X86][SSE] Remove UNPCKL(SHUFFLE)->UNPCKH custom combine new 911cc8dde35 [llvm-exegesis] Fix broken build bots. new a6fe72111f3 [InstCombine] Handle vector compares in foldGEPIcmp() new dff6e8d22fa [IR] reduce duplication in unittest for shuffles; NFC new 1c86ce8fa79 [IR] add shuffle query for vector concatenation new c12a4567e46 [llvm-mca][BtVer2] Modify ANDN tests in zero-idioms-avx-256.s. NFC new b17277efb8b [PDB] Add the ability to map forward references to full decls. new 24b5a5351b0 [gcov] Fix wrong line hit counts when multiple blocks are o [...] new 39b643282cd [PDB] Better printing of builtin types when using DIA dumper. new 4dc31615f57 [PDB] Fix failing test. new e6959a6ecfe [New PM] Introducing PassInstrumentation framework new e8e1aa27c99 [InstCombine] add tests for vector concat with binop (PR330 [...] new 5748c47c626 [SelectionDAG] replace duplicated peekThroughBitcast helper [...] new 2d481c770a9 Fix warnings.

The 85 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.

Summary of changes: docs/DeveloperPolicy.rst | 4 +- docs/SourceLevelDebugging.rst | 15 + include/llvm/ADT/Any.h | 10 + include/llvm/ADT/BitVector.h | 17 + include/llvm/ADT/Optional.h | 9 +- include/llvm/ADT/SmallBitVector.h | 5 + include/llvm/Analysis/CGSCCPassManager.h | 33 +- include/llvm/CodeGen/MachineInstr.h | 3 + include/llvm/CodeGen/MachineScheduler.h | 5 + include/llvm/CodeGen/ScheduleDAG.h | 17 +- include/llvm/CodeGen/ScheduleDAGInstrs.h | 3 +- include/llvm/CodeGen/SelectionDAGNodes.h | 8 + include/llvm/CodeGen/TargetLowering.h | 40 +- include/llvm/CodeGen/TargetSubtargetInfo.h | 25 + include/llvm/DebugInfo/DWARF/DWARFVerifier.h | 1 + include/llvm/DebugInfo/PDB/Native/RawTypes.h | 1 - include/llvm/DebugInfo/PDB/Native/TpiHashing.h | 48 + include/llvm/DebugInfo/PDB/Native/TpiStream.h | 9 + include/llvm/DebugInfo/PDB/PDBExtras.h | 1 + include/llvm/ExecutionEngine/Orc/LLJIT.h | 3 + include/llvm/IR/DebugInfoMetadata.h | 33 +- include/llvm/IR/DebugLoc.h | 7 +- include/llvm/IR/Instructions.h | 5 + include/llvm/IR/Intrinsics.td | 1 + include/llvm/IR/IntrinsicsRISCV.td | 39 + include/llvm/IR/Metadata.h | 6 +- include/llvm/IR/PassInstrumentation.h | 150 + include/llvm/IR/PassManager.h | 122 +- include/llvm/MC/MCInstrAnalysis.h | 51 +- include/llvm/MC/MCParser/MCTargetAsmParser.h | 3 + include/llvm/Passes/PassBuilder.h | 6 +- include/llvm/ProfileData/GCOV.h | 20 +- include/llvm/Target/TargetInstrPredicate.td | 98 + include/llvm/Transforms/Scalar/LoopPassManager.h | 19 +- include/llvm/Transforms/Utils/Local.h | 3 + include/llvm/XRay/Trace.h | 13 +- lib/Analysis/CGSCCPassManager.cpp | 12 + lib/AsmParser/LLParser.cpp | 11 +- lib/Bitcode/Reader/BitcodeReader.cpp | 3 +- lib/Bitcode/Reader/MetadataLoader.cpp | 6 +- lib/Bitcode/Writer/BitcodeWriter.cpp | 51 +- lib/CodeGen/AsmPrinter/AddressPool.cpp | 12 +- lib/CodeGen/AsmPrinter/AddressPool.h | 6 + lib/CodeGen/AsmPrinter/DwarfDebug.cpp | 12 +- lib/CodeGen/AsmPrinter/DwarfUnit.cpp | 7 + lib/CodeGen/AsmPrinter/DwarfUnit.h | 3 + lib/CodeGen/AtomicExpandPass.cpp | 76 +- lib/CodeGen/DFAPacketizer.cpp | 3 +- lib/CodeGen/GlobalISel/IRTranslator.cpp | 7 +- lib/CodeGen/LatencyPriorityQueue.cpp | 4 +- lib/CodeGen/MachineInstr.cpp | 36 + lib/CodeGen/MachinePipeliner.cpp | 9 +- lib/CodeGen/MachineScheduler.cpp | 60 +- lib/CodeGen/MachineVerifier.cpp | 32 +- lib/CodeGen/MacroFusion.cpp | 12 +- lib/CodeGen/PostRASchedulerList.cpp | 12 +- lib/CodeGen/ScheduleDAG.cpp | 100 +- lib/CodeGen/ScheduleDAGInstrs.cpp | 18 +- lib/CodeGen/ScoreboardHazardRecognizer.cpp | 3 +- lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 87 +- lib/CodeGen/SelectionDAG/InstrEmitter.cpp | 9 + lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp | 7 +- lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp | 12 +- lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp | 25 +- lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h | 4 +- lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp | 4 +- lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 17 +- lib/DebugInfo/DWARF/DWARFVerifier.cpp | 42 +- lib/DebugInfo/PDB/DIA/DIARawSymbol.cpp | 4 +- lib/DebugInfo/PDB/Native/SymbolCache.cpp | 1 + lib/DebugInfo/PDB/Native/TpiHashing.cpp | 43 + lib/DebugInfo/PDB/Native/TpiStream.cpp | 89 + lib/DebugInfo/PDB/PDBExtras.cpp | 30 + lib/FuzzMutate/IRMutator.cpp | 1 + lib/IR/AsmWriter.cpp | 2 + lib/IR/CMakeLists.txt | 1 + lib/IR/DebugInfoMetadata.cpp | 19 +- lib/IR/DebugLoc.cpp | 17 +- lib/IR/Instructions.cpp | 17 + lib/IR/LLVMContextImpl.h | 13 +- lib/IR/PassInstrumentation.cpp | 22 + lib/MC/MCInstrAnalysis.cpp | 5 - lib/MC/MCParser/AsmParser.cpp | 2 + lib/Passes/PassRegistry.def | 4 + lib/ProfileData/GCOV.cpp | 152 +- lib/Target/AArch64/AArch64.td | 5 + lib/Target/AArch64/AArch64ISelLowering.cpp | 10 +- lib/Target/AArch64/AArch64ISelLowering.h | 3 +- lib/Target/AArch64/AArch64MacroFusion.cpp | 251 +- lib/Target/AArch64/AArch64Subtarget.cpp | 2 +- lib/Target/AArch64/AArch64Subtarget.h | 2 + lib/Target/AMDGPU/GCNILPSched.cpp | 2 +- lib/Target/AMDGPU/GCNMinRegStrategy.cpp | 2 +- lib/Target/AMDGPU/R600MachineScheduler.cpp | 8 +- lib/Target/AMDGPU/SIInstructions.td | 10 + lib/Target/AMDGPU/SIMachineScheduler.cpp | 14 +- lib/Target/ARM/ARM.td | 90 +- lib/Target/ARM/ARMAsmPrinter.cpp | 10 +- lib/Target/ARM/ARMISelLowering.cpp | 10 +- lib/Target/ARM/ARMISelLowering.h | 3 +- lib/Target/ARM/ARMSubtarget.cpp | 8 +- lib/Target/ARM/ARMSubtarget.h | 2 +- lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 7 +- lib/Target/BPF/MCTargetDesc/BPFMCAsmInfo.h | 4 +- lib/Target/Hexagon/HexagonISelLowering.cpp | 9 +- lib/Target/Hexagon/HexagonISelLowering.h | 3 +- lib/Target/Hexagon/HexagonMachineScheduler.cpp | 7 +- lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 153 +- lib/Target/Mips/Disassembler/MipsDisassembler.cpp | 29 + lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp | 6 + lib/Target/Mips/MicroMips32r6InstrInfo.td | 4 +- lib/Target/Mips/MicroMipsInstrInfo.td | 28 +- lib/Target/Mips/MicroMipsSizeReduction.cpp | 115 +- lib/Target/Mips/MipsDelaySlotFiller.cpp | 5 +- lib/Target/Mips/MipsRegisterBankInfo.cpp | 3 + lib/Target/Mips/MipsRegisterInfo.td | 28 + lib/Target/PowerPC/PPCHazardRecognizers.cpp | 5 +- lib/Target/PowerPC/PPCISelLowering.cpp | 3 +- lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 91 +- lib/Target/RISCV/CMakeLists.txt | 1 + lib/Target/RISCV/RISCV.h | 4 + lib/Target/RISCV/RISCVExpandPseudoInsts.cpp | 452 + lib/Target/RISCV/RISCVISelLowering.cpp | 93 +- lib/Target/RISCV/RISCVISelLowering.h | 9 + lib/Target/RISCV/RISCVInstrInfo.td | 20 +- lib/Target/RISCV/RISCVInstrInfoA.td | 125 + lib/Target/RISCV/RISCVTargetMachine.cpp | 10 + lib/Target/WebAssembly/WebAssemblyInstrSIMD.td | 76 +- lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp | 78 +- lib/Target/X86/X86AsmPrinter.cpp | 23 +- lib/Target/X86/X86ISelLowering.cpp | 259 +- lib/Target/X86/X86ISelLowering.h | 9 + lib/Target/X86/X86RegisterInfo.h | 2 + lib/Target/X86/X86ScheduleBtVer2.td | 62 + lib/Transforms/InstCombine/InstCombineCompares.cpp | 18 +- lib/Transforms/Instrumentation/GCOVProfiling.cpp | 3 +- lib/Transforms/Scalar/LoopPassManager.cpp | 10 + lib/Transforms/Scalar/SCCP.cpp | 64 +- lib/Transforms/Utils/BuildLibCalls.cpp | 2 + lib/Transforms/Utils/Local.cpp | 7 + lib/Transforms/Utils/SimplifyCFG.cpp | 8 +- lib/Transforms/Utils/SimplifyLibCalls.cpp | 5 +- test/Assembler/dilocation.ll | 13 +- test/Bitcode/DILocation-implicit-code.ll | 190 + test/Bitcode/DILocation-implicit-code.ll.bc | Bin 0 -> 4680 bytes test/CodeGen/AArch64/extract-bits.ll | 717 ++ test/CodeGen/AArch64/misched-fusion-crypto-eor.mir | 75 + test/CodeGen/AMDGPU/sitofp.f16.ll | 19 + test/CodeGen/AMDGPU/uitofp.f16.ll | 19 + test/CodeGen/ARM/unwind-fp.ll | 15 + test/CodeGen/Hexagon/swp-epilog-phi6.ll | 2 +- test/CodeGen/Hexagon/verify-liveness-at-def.mir | 74 + .../micromips-sizereduction/micromips-movep.ll | 29 + .../micromips-sizereduction/micromips-movep.mir | 86 + test/CodeGen/PowerPC/crash.ll | 17 + test/CodeGen/RISCV/atomic-rmw.ll | 4282 ++++++++++ test/CodeGen/WebAssembly/simd-arith.ll | 25 + test/CodeGen/WinCFGuard/cfguard.ll | 2 + test/CodeGen/X86/2012-01-12-extract-sv.ll | 5 +- test/CodeGen/X86/GlobalISel/add-ext.ll | 228 + test/CodeGen/X86/GlobalISel/add-scalar.ll | 3 +- test/CodeGen/X86/GlobalISel/and-scalar.ll | 10 +- test/CodeGen/X86/GlobalISel/ashr-scalar.ll | 73 +- test/CodeGen/X86/GlobalISel/binop.ll | 4 +- test/CodeGen/X86/GlobalISel/callingconv.ll | 6 +- test/CodeGen/X86/GlobalISel/ext-x86-64.ll | 19 +- test/CodeGen/X86/GlobalISel/ext.ll | 20 +- test/CodeGen/X86/GlobalISel/lshr-scalar.ll | 69 +- test/CodeGen/X86/GlobalISel/memop-scalar.ll | 18 +- test/CodeGen/X86/GlobalISel/mul-scalar.ll | 31 +- test/CodeGen/X86/GlobalISel/or-scalar.ll | 10 +- test/CodeGen/X86/GlobalISel/phi.ll | 62 +- test/CodeGen/X86/GlobalISel/ptrtoint.ll | 12 +- test/CodeGen/X86/GlobalISel/shl-scalar-widening.ll | 37 +- test/CodeGen/X86/GlobalISel/shl-scalar.ll | 65 +- test/CodeGen/X86/GlobalISel/sub-scalar.ll | 10 +- test/CodeGen/X86/GlobalISel/trunc.ll | 12 +- test/CodeGen/X86/GlobalISel/undef.ll | 3 +- test/CodeGen/X86/GlobalISel/xor-scalar.ll | 10 +- test/CodeGen/X86/add.ll | 87 +- test/CodeGen/X86/addcarry.ll | 40 +- test/CodeGen/X86/and-encoding.ll | 18 +- test/CodeGen/X86/andimm8.ll | 11 +- test/CodeGen/X86/anyext.ll | 3 +- test/CodeGen/X86/apm.ll | 4 +- test/CodeGen/X86/atomic-eflags-reuse.ll | 48 +- test/CodeGen/X86/atomic128.ll | 3 +- test/CodeGen/X86/avg.ll | 10 +- test/CodeGen/X86/avoid-sfb.ll | 76 +- test/CodeGen/X86/avx-intel-ocl.ll | 2 +- test/CodeGen/X86/avx-logic.ll | 29 + test/CodeGen/X86/avx-vinsertf128.ll | 9 +- test/CodeGen/X86/avx512-arith.ll | 4 +- test/CodeGen/X86/avx512-calling-conv.ll | 4 +- test/CodeGen/X86/avx512-insert-extract.ll | 32 +- test/CodeGen/X86/avx512-intrinsics-upgrade.ll | 28 +- test/CodeGen/X86/avx512-mask-op.ll | 15 +- test/CodeGen/X86/avx512-regcall-NoMask.ll | 45 +- test/CodeGen/X86/avx512-schedule.ll | 38 +- test/CodeGen/X86/avx512-select.ll | 6 +- test/CodeGen/X86/avx512bw-mask-op.ll | 20 +- test/CodeGen/X86/avx512dq-mask-op.ll | 12 +- test/CodeGen/X86/avx512vl-arith.ll | 8 +- test/CodeGen/X86/bigstructret.ll | 14 +- test/CodeGen/X86/bitcast-i256.ll | 4 +- test/CodeGen/X86/bitcast-int-to-vector-bool.ll | 6 +- test/CodeGen/X86/bitreverse.ll | 57 +- .../CodeGen/X86/bmi-intrinsics-fast-isel-x86_64.ll | 8 +- test/CodeGen/X86/bmi-intrinsics-fast-isel.ll | 8 +- test/CodeGen/X86/bmi.ll | 4 +- test/CodeGen/X86/bmi2.ll | 28 +- test/CodeGen/X86/bool-math.ll | 33 +- test/CodeGen/X86/bool-simplify.ll | 4 +- test/CodeGen/X86/bswap-rotate.ll | 3 +- test/CodeGen/X86/bswap-wide-int.ll | 16 +- test/CodeGen/X86/bswap.ll | 15 +- test/CodeGen/X86/bswap_tree.ll | 8 +- test/CodeGen/X86/bswap_tree2.ll | 18 +- test/CodeGen/X86/bt.ll | 12 +- test/CodeGen/X86/btc_bts_btr.ll | 79 +- test/CodeGen/X86/bypass-slow-division-64.ll | 27 +- test/CodeGen/X86/clear-highbits.ll | 56 +- test/CodeGen/X86/clear-lowbits.ll | 106 +- test/CodeGen/X86/cmov-into-branch.ll | 31 +- test/CodeGen/X86/cmov.ll | 11 +- test/CodeGen/X86/cmovcmov.ll | 18 +- test/CodeGen/X86/cmp.ll | 8 +- test/CodeGen/X86/cmpxchg-clobber-flags.ll | 4 +- test/CodeGen/X86/cmpxchg-i128-i1.ll | 22 +- test/CodeGen/X86/combine-add.ll | 12 +- test/CodeGen/X86/combine-rotates.ll | 2 +- test/CodeGen/X86/combine-sdiv.ll | 281 +- test/CodeGen/X86/combine-srem.ll | 20 +- test/CodeGen/X86/combine-udiv.ll | 2 +- test/CodeGen/X86/combine-urem.ll | 2 +- test/CodeGen/X86/conditional-indecrement.ll | 36 +- test/CodeGen/X86/dagcombine-cse.ll | 4 - test/CodeGen/X86/dagcombine-select.ll | 21 +- test/CodeGen/X86/divide-by-constant.ll | 54 +- test/CodeGen/X86/divrem.ll | 9 +- test/CodeGen/X86/divrem8_ext.ll | 4 + test/CodeGen/X86/extract-bits.ll | 5642 +++++++++++++ test/CodeGen/X86/extract-lowbits.ll | 1153 ++- test/CodeGen/X86/extractelement-load.ll | 25 +- test/CodeGen/X86/fast-isel-fold-mem.ll | 2 +- test/CodeGen/X86/fast-isel-select-cmov.ll | 16 +- test/CodeGen/X86/fast-isel-select-cmov2.ll | 188 +- test/CodeGen/X86/fast-isel-select-pseudo-cmov.ll | 11 +- test/CodeGen/X86/fast-isel-sext-zext.ll | 8 +- test/CodeGen/X86/fast-isel-shift.ll | 112 +- test/CodeGen/X86/fast-isel-store.ll | 5 +- test/CodeGen/X86/fixup-bw-copy.ll | 28 +- test/CodeGen/X86/fma.ll | 15 +- test/CodeGen/X86/fold-vector-sext-crash2.ll | 8 +- test/CodeGen/X86/funnel-shift-rot.ll | 26 +- test/CodeGen/X86/funnel-shift.ll | 24 +- test/CodeGen/X86/ghc-cc64.ll | 4 +- test/CodeGen/X86/hipe-cc64.ll | 3 +- test/CodeGen/X86/i128-mul.ll | 12 +- test/CodeGen/X86/iabs.ll | 9 +- test/CodeGen/X86/imul.ll | 34 +- test/CodeGen/X86/insertps-combine.ll | 5 +- test/CodeGen/X86/lea-opt.ll | 33 +- test/CodeGen/X86/legalize-shift-64.ll | 7 +- test/CodeGen/X86/legalize-shl-vec.ll | 60 +- test/CodeGen/X86/machine-combiner-int.ll | 57 +- test/CodeGen/X86/machine-cp.ll | 64 +- test/CodeGen/X86/machine-cse.ll | 10 +- test/CodeGen/X86/madd.ll | 4 +- test/CodeGen/X86/mask-negated-bool.ll | 4 +- test/CodeGen/X86/misched-matmul.ll | 2 +- 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