[Tcwg-commits] [gcc] branch master updated (ff5a14abeb3 -> fa18217f60f)

20 Nov 2024


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unknown user pushed a change to branch master
in repository gcc.
from  ff5a14abeb3 tree-optimization/117574 - bougs niter lt-to-ne
       new  42f1a08e41d RISC-V: Rearrange the test files for vector SAT_ADD [NFC]
       new  b95d585fd49 RISC-V: Introduce riscv/rvv/autovec/sat folder to rvv.exp t [...]
       new  fa18217f60f RISC-V: Refine the rtl dump expand check for vector SAT_ADD
The 3 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails.  The revisions
listed as "adds" were already present in the repository and have only
been added to this reference.
Summary of changes:
 .../riscv/rvv/autovec/binop/vec_sat_s_add-1.c      |  9 -------
 .../riscv/rvv/autovec/binop/vec_sat_s_add-10.c     |  9 -------
 .../riscv/rvv/autovec/binop/vec_sat_s_add-11.c     |  9 -------
 .../riscv/rvv/autovec/binop/vec_sat_s_add-12.c     |  9 -------
 .../riscv/rvv/autovec/binop/vec_sat_s_add-13.c     |  9 -------
 .../riscv/rvv/autovec/binop/vec_sat_s_add-14.c     |  9 -------
 .../riscv/rvv/autovec/binop/vec_sat_s_add-15.c     |  9 -------
 .../riscv/rvv/autovec/binop/vec_sat_s_add-16.c     |  9 -------
 .../riscv/rvv/autovec/binop/vec_sat_s_add-2.c      |  9 -------
 .../riscv/rvv/autovec/binop/vec_sat_s_add-3.c      |  9 -------
 .../riscv/rvv/autovec/binop/vec_sat_s_add-4.c      |  9 -------
 .../riscv/rvv/autovec/binop/vec_sat_s_add-5.c      |  9 -------
 .../riscv/rvv/autovec/binop/vec_sat_s_add-6.c      |  9 -------
 .../riscv/rvv/autovec/binop/vec_sat_s_add-7.c      |  9 -------
 .../riscv/rvv/autovec/binop/vec_sat_s_add-8.c      |  9 -------
 .../riscv/rvv/autovec/binop/vec_sat_s_add-9.c      |  9 -------
 .../riscv/rvv/autovec/binop/vec_sat_u_add-2.c      |  9 -------
 .../riscv/rvv/autovec/{ => sat}/vec_sat_arith.h    |  0
 .../{binop => sat}/vec_sat_binary_vvv_run.h        |  0
 .../{binop => sat}/vec_sat_binary_vvx_run.h        |  0
 .../autovec/{binop => sat}/vec_sat_binary_vx_run.h |  0
 .../rvv/autovec/{binop => sat}/vec_sat_data.h      |  0
 .../riscv/rvv/autovec/sat/vec_sat_s_add-1-s16.c    | 10 ++++++++
 .../riscv/rvv/autovec/sat/vec_sat_s_add-1-s32.c    | 10 ++++++++
 .../riscv/rvv/autovec/sat/vec_sat_s_add-1-s64.c    | 10 ++++++++
 .../riscv/rvv/autovec/sat/vec_sat_s_add-1-s8.c     | 10 ++++++++
 .../riscv/rvv/autovec/sat/vec_sat_s_add-2-s16.c    | 10 ++++++++
 .../riscv/rvv/autovec/sat/vec_sat_s_add-2-s32.c    | 10 ++++++++
 .../riscv/rvv/autovec/sat/vec_sat_s_add-2-s64.c    | 10 ++++++++
 .../riscv/rvv/autovec/sat/vec_sat_s_add-2-s8.c     | 10 ++++++++
 .../riscv/rvv/autovec/sat/vec_sat_s_add-3-s16.c    | 10 ++++++++
 .../riscv/rvv/autovec/sat/vec_sat_s_add-3-s32.c    | 10 ++++++++
 .../riscv/rvv/autovec/sat/vec_sat_s_add-3-s64.c    | 10 ++++++++
 .../riscv/rvv/autovec/sat/vec_sat_s_add-3-s8.c     | 10 ++++++++
 .../riscv/rvv/autovec/sat/vec_sat_s_add-4-s16.c    | 10 ++++++++
 .../riscv/rvv/autovec/sat/vec_sat_s_add-4-s32.c    | 10 ++++++++
 .../riscv/rvv/autovec/sat/vec_sat_s_add-4-s64.c    | 10 ++++++++
 .../riscv/rvv/autovec/sat/vec_sat_s_add-4-s8.c     | 10 ++++++++
 .../vec_sat_s_add-run-1-s16.c}                     |  2 +-
 .../vec_sat_s_add-run-1-s32.c}                     |  2 +-
 .../vec_sat_s_add-run-1-s64.c}                     |  2 +-
 .../vec_sat_s_add-run-1-s8.c}                      |  2 +-
 .../vec_sat_s_add-run-2-s16.c}                     |  2 +-
 .../vec_sat_s_add-run-2-s32.c}                     |  2 +-
 .../vec_sat_s_add-run-2-s64.c}                     |  2 +-
 .../vec_sat_s_add-run-2-s8.c}                      |  2 +-
 .../vec_sat_s_add-run-3-s16.c}                     |  2 +-
 .../vec_sat_s_add-run-3-s32.c}                     |  2 +-
 .../vec_sat_s_add-run-3-s64.c}                     |  2 +-
 .../vec_sat_s_add-run-3-s8.c}                      |  2 +-
 .../vec_sat_s_add-run-4-s16.c}                     |  2 +-
 .../vec_sat_s_add-run-4-s32.c}                     |  2 +-
 .../vec_sat_s_add-run-4-s64.c}                     |  2 +-
 .../vec_sat_s_add-run-4-s8.c}                      |  2 +-
 .../riscv/rvv/autovec/sat/vec_sat_u_add-1-u16.c    | 28 ++++++++++++++++++++++
 .../vec_sat_u_add-1-u32.c}                         |  4 ++--
 .../vec_sat_u_add-1-u64.c}                         |  4 ++--
 .../vec_sat_u_add-1.c => sat/vec_sat_u_add-1-u8.c} |  4 ++--
 .../vec_sat_u_add-2-u16.c}                         |  4 ++--
 .../vec_sat_u_add-2-u32.c}                         |  4 ++--
 .../vec_sat_u_add-2-u64.c}                         |  4 ++--
 .../vec_sat_u_add-5.c => sat/vec_sat_u_add-2-u8.c} |  4 ++--
 .../vec_sat_u_add-3-u16.c}                         |  4 ++--
 .../vec_sat_u_add-3-u32.c}                         |  4 ++--
 .../vec_sat_u_add-3-u64.c}                         |  4 ++--
 .../vec_sat_u_add-9.c => sat/vec_sat_u_add-3-u8.c} |  4 ++--
 .../vec_sat_u_add-4-u16.c}                         |  4 ++--
 .../vec_sat_u_add-4-u32.c}                         |  4 ++--
 .../vec_sat_u_add-4-u64.c}                         |  4 ++--
 .../vec_sat_u_add-4-u8.c}                          |  4 ++--
 .../vec_sat_u_add-5-u16.c}                         |  4 ++--
 .../vec_sat_u_add-5-u32.c}                         |  4 ++--
 .../vec_sat_u_add-5-u64.c}                         |  4 ++--
 .../vec_sat_u_add-5-u8.c}                          |  4 ++--
 .../vec_sat_u_add-6-u16.c}                         |  4 ++--
 .../vec_sat_u_add-6-u32.c}                         |  4 ++--
 .../vec_sat_u_add-6-u64.c}                         |  4 ++--
 .../vec_sat_u_add-6-u8.c}                          |  4 ++--
 .../vec_sat_u_add-7-u16.c}                         |  4 ++--
 .../vec_sat_u_add-7-u32.c}                         |  4 ++--
 .../vec_sat_u_add-7-u64.c}                         |  4 ++--
 .../vec_sat_u_add-7-u8.c}                          |  4 ++--
 .../vec_sat_u_add-8-u16.c}                         |  4 ++--
 .../vec_sat_u_add-8-u32.c}                         |  4 ++--
 .../vec_sat_u_add-8-u64.c}                         |  4 ++--
 .../vec_sat_u_add-8-u8.c}                          |  4 ++--
 .../vec_sat_u_add-run-1-u16.c}                     |  2 +-
 .../vec_sat_u_add-run-1-u32.c}                     |  2 +-
 .../vec_sat_u_add-run-1-u64.c}                     |  2 +-
 .../vec_sat_u_add-run-1-u8.c}                      |  2 +-
 .../vec_sat_u_add-run-2-u16.c}                     |  2 +-
 .../vec_sat_u_add-run-2-u32.c}                     |  2 +-
 .../vec_sat_u_add-run-2-u64.c}                     |  2 +-
 .../vec_sat_u_add-run-2-u8.c}                      |  2 +-
 .../vec_sat_u_add-run-3-u16.c}                     |  2 +-
 .../vec_sat_u_add-run-3-u32.c}                     |  2 +-
 .../vec_sat_u_add-run-3-u64.c}                     |  2 +-
 .../vec_sat_u_add-run-3-u8.c}                      |  2 +-
 .../vec_sat_u_add-run-4-u16.c}                     |  2 +-
 .../vec_sat_u_add-run-4-u32.c}                     |  2 +-
 .../vec_sat_u_add-run-4-u64.c}                     |  2 +-
 .../vec_sat_u_add-run-4-u8.c}                      |  2 +-
 .../vec_sat_u_add-run-5-u16.c}                     |  2 +-
 .../vec_sat_u_add-run-5-u32.c}                     |  2 +-
 .../vec_sat_u_add-run-5-u64.c}                     |  2 +-
 .../vec_sat_u_add-run-5-u8.c}                      |  2 +-
 .../vec_sat_u_add-run-6-u16.c}                     |  2 +-
 .../vec_sat_u_add-run-6-u32.c}                     |  2 +-
 .../vec_sat_u_add-run-6-u64.c}                     |  2 +-
 .../vec_sat_u_add-run-6-u8.c}                      |  2 +-
 .../vec_sat_u_add-run-7-u16.c}                     |  2 +-
 .../vec_sat_u_add-run-7-u32.c}                     |  2 +-
 .../vec_sat_u_add-run-7-u64.c}                     |  2 +-
 .../vec_sat_u_add-run-7-u8.c}                      |  2 +-
 .../vec_sat_u_add-run-8-u16.c}                     |  2 +-
 .../vec_sat_u_add-run-8-u32.c}                     |  2 +-
 .../vec_sat_u_add-run-8-u64.c}                     |  2 +-
 .../vec_sat_u_add-run-8-u8.c}                      |  2 +-
 .../vec_sat_u_add_imm-1-u16.c}                     |  4 ++--
 .../vec_sat_u_add_imm-1-u32.c}                     |  4 ++--
 .../vec_sat_u_add_imm-1-u64.c}                     |  4 ++--
 .../vec_sat_u_add_imm-1-u8.c}                      |  4 ++--
 .../vec_sat_u_add_imm-2-u16.c}                     |  4 ++--
 .../vec_sat_u_add_imm-2-u32.c}                     |  4 ++--
 .../vec_sat_u_add_imm-2-u64.c}                     |  4 ++--
 .../vec_sat_u_add_imm-2-u8.c}                      |  4 ++--
 .../vec_sat_u_add_imm-3-u16.c}                     |  4 ++--
 .../vec_sat_u_add_imm-3-u32.c}                     |  4 ++--
 .../vec_sat_u_add_imm-3-u64.c}                     |  4 ++--
 .../vec_sat_u_add_imm-3-u8.c}                      |  4 ++--
 .../vec_sat_u_add_imm-4-u16.c}                     |  4 ++--
 .../vec_sat_u_add_imm-4-u32.c}                     |  4 ++--
 .../vec_sat_u_add_imm-4-u64.c}                     |  4 ++--
 .../vec_sat_u_add_imm-4-u8.c}                      |  4 ++--
 .../vec_sat_u_add_imm-run-1-u16.c}                 |  2 +-
 .../vec_sat_u_add_imm-run-1-u32.c}                 |  2 +-
 .../vec_sat_u_add_imm-run-1-u64.c}                 |  2 +-
 .../vec_sat_u_add_imm-run-1-u8.c}                  |  2 +-
 .../vec_sat_u_add_imm-run-2-u16.c}                 |  2 +-
 .../vec_sat_u_add_imm-run-2-u32.c}                 |  2 +-
 .../vec_sat_u_add_imm-run-2-u64.c}                 |  2 +-
 .../vec_sat_u_add_imm-run-2-u8.c}                  |  2 +-
 .../vec_sat_u_add_imm-run-3-u16.c}                 |  2 +-
 .../vec_sat_u_add_imm-run-3-u32.c}                 |  2 +-
 .../vec_sat_u_add_imm-run-3-u64.c}                 |  2 +-
 .../vec_sat_u_add_imm-run-3-u8.c}                  |  2 +-
 .../vec_sat_u_add_imm-run-4-u16.c}                 |  2 +-
 .../vec_sat_u_add_imm-run-4-u32.c}                 |  2 +-
 .../vec_sat_u_add_imm-run-4-u64.c}                 |  2 +-
 .../vec_sat_u_add_imm-run-4-u8.c}                  |  2 +-
 .../vec_sat_u_add_imm_reconcile-1-u16.c}           |  4 ++--
 .../vec_sat_u_add_imm_reconcile-1-u32.c}           |  4 ++--
 .../vec_sat_u_add_imm_reconcile-1-u64.c}           |  4 ++--
 .../vec_sat_u_add_imm_reconcile-1-u8.c}            |  4 ++--
 .../vec_sat_u_add_imm_reconcile-2-u16.c}           |  4 ++--
 .../vec_sat_u_add_imm_reconcile-2-u32.c}           |  4 ++--
 .../vec_sat_u_add_imm_reconcile-2-u64.c}           |  4 ++--
 .../vec_sat_u_add_imm_reconcile-2-u8.c}            |  4 ++--
 .../vec_sat_u_add_imm_reconcile-3-u16.c}           |  4 ++--
 .../vec_sat_u_add_imm_reconcile-3-u32.c}           |  4 ++--
 .../vec_sat_u_add_imm_reconcile-3-u64.c}           |  4 ++--
 .../vec_sat_u_add_imm_reconcile-3-u8.c}            |  4 ++--
 .../vec_sat_u_add_imm_reconcile-4-u16.c}           |  4 ++--
 .../vec_sat_u_add_imm_reconcile-4-u32.c}           |  4 ++--
 .../vec_sat_u_add_imm_reconcile-4-u8.c}            |  4 ++--
 gcc/testsuite/gcc.target/riscv/rvv/rvv.exp         |  2 ++
 166 files changed, 378 insertions(+), 341 deletions(-)
 delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-1.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-10.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-11.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-12.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-13.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-14.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-15.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-16.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-2.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-3.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-4.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-5.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-6.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-7.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-8.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-9.c
 delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{ => sat}/vec_sat_arith.h (100%)
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop => sat}/vec_sat_binary_vvv_ [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop => sat}/vec_sat_binary_vvx_ [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop => sat}/vec_sat_binary_vx_r [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop => sat}/vec_sat_data.h (100%)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s8.c
 rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_s_add-run-2.c =>  [...]
 rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_s_add-run-3.c =>  [...]
 rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_s_add-run-4.c =>  [...]
 rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_s_add-run-1.c =>  [...]
 rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_s_add-run-6.c =>  [...]
 rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_s_add-run-7.c =>  [...]
 rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_s_add-run-8.c =>  [...]
 rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_s_add-run-5.c =>  [...]
 rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_s_add-run-10.c => [...]
 rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_s_add-run-11.c => [...]
 rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_s_add-run-12.c => [...]
 rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_s_add-run-9.c =>  [...]
 rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_s_add-run-14.c => [...]
 rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_s_add-run-15.c => [...]
 rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_s_add-run-16.c => [...]
 rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_s_add-run-13.c => [...]
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u16.c
 rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-3.c => sat/ [...]
 rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-4.c => sat/ [...]
 rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-1.c => sat/ [...]
 rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-6.c => sat/ [...]
 rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-7.c => sat/ [...]
 rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-8.c => sat/ [...]
 rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-5.c => sat/ [...]
 rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-10.c => sat [...]
 rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-11.c => sat [...]
 rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-12.c => sat [...]
 rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-9.c => sat/ [...]
 rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-14.c => sat [...]
 rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-15.c => sat [...]
 rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-16.c => sat [...]
 rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-13.c => sat [...]
 rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-18.c => sat [...]
 rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-19.c => sat [...]
 rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-20.c => sat [...]
 rename gcc/testsuite/gcc.target/riscv/rvv/autovec/{binop/vec_sat_u_add-17.c => sat [...]
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[Tcwg-commits] [gcc] branch master updated (ff5a14abeb3 -> fa18217f60f)