[Tcwg-commits] [toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_bmk_llvm_tx1/llvm-master-aarch64-spec2k6-O3 updated (40d2ef841b68 -> 0c01f42fad41)

5 Jul 2022


      This is an automated email from the git hooks/post-receive script.
tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_llvm_tx1/llvm-master-aarch64-spec2k6-O3
in repository toolchain/ci/llvm-project.
from  40d2ef841b68 [clang-format][NFC] Replace an EXPECT_EQ with a verifyFormat
      adds  68050c235432 Revert "[CMake][Fuchsia] Use libunwind as the default unwinder"
      adds  9ac548e1181c [RISCV] isel (add (and X, 0xFFFFFFFE), Y) as (SH1ADD (SRLI [...]
      adds  b2e9684fe4d1 [RISCV] isel (shl (and X, C2), C) -> (slli (srliw X, C3), C3+C).
      adds  7fc4518f4a70 [MLIR] Rename FusePadOpWithLinalgConsumer -> FusePadOpWith [...]
      adds  23ee84f43201 [globalisel] Add test case for regbank selection.
      adds  b0da3c6fa44b [VPlan] Move setDebugLocFromInst to VPTransformState (NFC).
      adds  5d787689b145 [RISCV] Match RISCVISD::ADD_LO in SelectAddrRegImm.
      adds  5148c685e3bb [mlir][complex] Inverse canonicalization between exp and log
      adds  7788b0c09754 [lsan] malloc_usable_size returns 0 for nullptr
      adds  7e4ab9d5b8b8 [RISCV] Add more SHXADD isel patterns.
      adds  1ecfc12b0c67 [Bazel] Make `builtin_headers_gen` as subset of CMake's `c [...]
      adds  f7819ce166bc [FPEnv] Allow CompoundStmt to keep FP options
      adds  8679cbc29fb7 Reland "[NFC] Add a missing test for for clang-repl"
      adds  022bd92c78ed [LowerMatrixMultiplication] Switch dummy values from undef [...]
      adds  6956840b5c00 Revert "Reland "[NFC] Add a missing test for for clang-repl""
      adds  0f45eaf0da1f [RISCV] Add a scavenge spill slot when use ADDI to compute [...]
      adds  53dc0f107877 [NFC] Switch a few uses of undef to poison as placeholders [...]
      adds  d100a30a5406 [AArch64] Regenerate more tests. NFC
      adds  d71a8bb157ea [MLIR][Affine] Allow affine-expr on RHS in IntegerSet
      adds  13d58ff9f373 [RISCV] Replace call to APInt::countTrailingZeros with uin [...]
      adds  2aea8af25136 [libc++] Make _LIBCPP_DEBUG_RANDOMIZE_RANGE a function
      adds  e1f61d864214 [gn build] Port 2aea8af25136
      adds  c1c3134ac422 [InstCombine] add tests for and-of-negated-lowbitmask; NFC
      adds  f9f40aa10d98 [InstCombine] fold negated low-bit-mask to cmp+select
      adds  b1f0efc06acc [clang-format] Tweak help text a bit
      adds  134363208b92 [clang] Fix gcc-6 compilation error. (NFC)
      adds  a65a3bffd31f [clang-tidy] Don't treat invalid branches as identical
      adds  f7a80c3d08d4 [clang-tidy] Properly forward clang-tidy output when runni [...]
      adds  2c3784cff859 [SCEV] recognize llvm.annotation intrinsic
      adds  e98e13ac8f38 [mlir][Vector] Fold ShuffleOp(SplatOp(X), SplatOp(X)) to S [...]
      adds  d2a35e4d39fe [AIX] Handling the label alignment of a global variable wi [...]
      adds  93d6fdfc232c [Driver] Ignore the clang modules validation-related flags [...]
      adds  8eb4dcb73747 [RISCV] Move some SHXADD matching cases into a ComplexPatt [...]
      adds  d36e09cfe591 [RISCV] Add more SHXADD patterns.
      adds  1063dfc02853 [mlir][openmp] Added omp.taskloop
      adds  7283f48a05de [IR] Remove support for insertvalue constant expression
      adds  b4694229aa9d [LV] Simplify setDebugLocFromInst by using early exit (NFC).
      adds  f0089fae1d7e [AArch64] Add additional tests for D120481.
      adds  7fbf55c927f2 [mlir][Tensor] Move ParallelInsertSlice to the tensor dialect
      adds  9604601c9394 [SimplifyCFG] Remove redundant checks for hoisting (NFCI)
      adds  4887d047a31f [libc++][NFC] Replace enable_if with __enable_if_t in a fe [...]
      adds  04f6bf482b86 Revise outdated parts of the developer policy.
      adds  5f0a054f8954 [pseudo] Remove duplicated code in ClangPseudo.cpp
      adds  c9fb3c6ea6cc [mlir][Tensor] Update ParallelInsertSlicOp semantics to ma [...]
      adds  f4dd977537dc [AST] Use canonical constraint declaration for ASTContext: [...]
      adds  42f5b0509ded [mlir][NFC] Fix various warnings generated by GCC 9
      adds  cce64e7a9cba [DAG] visitTRUNCATE - move GetDemandedBits AFTER SimplifyD [...]
      adds  f90f0e8fe7f5 [AMDGPU][GFX10][DOC][NFC] Update assembler syntax description
      adds  bf89d24f5319 [AArch64] NFC: Move safe predicate casting to a separate f [...]
      adds  740633ff08ff [flang] Add TODO for derived types with final procedure
      adds  4905bcac00e6 [ConstantFolding] Check return value of ConstantFoldInstOp [...]
      adds  8e70258b18ba [AMDGPUCodeGenPrepare] Check result of ConstantFoldBinaryO [...]
      adds  19a1e20b8a0f [VectorCombine] Improve shuffle select shuffle-of-shuffles
      adds  25607d143d1d [libc++] Implement `std::ranges::merge`
      adds  3912928aa891 [gn build] Port 25607d143d1d
      adds  32a76fc292d9 [SCEVExpander] Avoid ConstantExpr::get() (NFCI)
      adds  93cbdaef0455 [Reassociate] Avoid ConstantExpr::get()
      adds  2de05afc192d [SLP] Peek into loads when hitting the RecursionMaxDepth
      adds  2ab260eecfab [llvm-ar][test] Add additional MRI script testing
      adds  4e6c30c8354f [libc] Add a separate algorithm_test.
      adds  d7697c175db9 [flang] Avoid segfault when defining op is not a fir::Convert
      adds  f93cd56262d1 [BPI] Avoid ConstantExpr::get()
      adds  aa78c5298ea3 Fix MLIR Python CMake bug causing duplicate sources target.
      adds  644a965c1efe [LV] Vectorize cases with larger number of RT checks, exec [...]
      adds  c06d0b4d02ea [RISCV] Add ADDI instr for computing FrameIndex address
      adds  c146af3f469a [LoopVectorize][NFC] Reinstate TTICapture workaround for gcc-6
      adds  8471c6861992 [LTO] Update remark test after 644a965c1efef6.
      adds  89cb8cae606b [Bitcode] Use bitcode input for test (NFC)
      adds  abbd684c02c7 [InstCombine] Avoid ConstantExpr::get() in phi binop fold
      adds  10ebaf76860e [SLP] add test for load combining + shuffling; NFC
      adds  fdf505f3f223 [mlir][OpenMP] omp.task translation to LLVM IR
      adds  2bfca3561466 [X86] Disable combineVectorSizedSetCCEquality for soft float.
      adds  5785717e18d5 [AArch64] Add support for insert/extract for nxv1i1 types.
      adds  2fde26dfcabe [mlir][Linalg][NFC] Make getReassociationMapForFoldingUnit [...]
      adds  9eb657278611 [LV] Add back CantReorderMemOps remark.
      adds  c3839c0b46a9 CombineContractBroadcast should not create dims unused in LHS+RHS
      adds  bc70ba814dc1 Use add_llvm_install_targets for install-llvmlibc
      adds  b37dafd5dc83 [pseudo] Store shift and goto actions in a compact structu [...]
      adds  12d26ce9b0ec [flang] Make code more homogenous in CodeGen
      adds  47bdf53a5dba [clang-format] Break on AfterColon only if not followed by [...]
      adds  1ab37d996ce3 [clang-format] Update documentation
      adds  2a82c15f63d4 [LV] Consider runtime checks profitable if scalar cost is zero.
      adds  623250b51139 [X86] Regenerate fold-tied-op.ll test checks
      adds  a4e2c1f76295 [Orc][LLJIT] Use JITLink on RISC-V
      adds  b6178ccfe852 [OffloadPackager] Use appropriate kind for LTO bitcode
      adds  4276d00b1253 [InstCombine] add helper function for sub-of-min/max folds; NFC
      adds  8ef053273abf [InstCombine] add tests for sub of smin/smax; NFC
      adds  142aca7741d5 [InstCombine] fold sub of min/max of sub with common operand
      adds  b2b4c8721db0 [InstCombine] Make use of low zero bits to determine exact [...]
      adds  063500afc0b8 [RISCV][NFC] Merge the isolated decleration into foreach.
      adds  98c6a3c0c220 [NFC][ASTImporter] remove the unnecessary condition checks [...]
      adds  85318d328102 [NFC] Remove unused test inputs
      adds  939352b6ec31 [RISCV][Clang] Teach RISCVEmitter to generate BitCast for  [...]
       new  5b4851ed9113 [LoongArch] Add codegen support for load/store operations
       new  b940fe6fe2af [LoongArch] Add codegen support for conditional branches
       new  3610d5f5d4c2 [LoongArch] Add initial support for function calls
       new  0c01f42fad41 [llvm-objcopy] -O binary: align sh_offset for section chan [...]
The 4 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails.  The revisions
listed as "adds" were already present in the repository and have only
been added to this reference.
Summary of changes:
 .../clang-tidy/bugprone/BranchCloneCheck.cpp       |  11 +
 clang-tools-extra/docs/ReleaseNotes.rst            |   4 +
 .../pseudo/include/clang-pseudo/grammar/LRTable.h  | 120 +++-
 clang-tools-extra/pseudo/lib/GLR.cpp               |  16 +-
 clang-tools-extra/pseudo/lib/grammar/LRTable.cpp   |  65 +-
 .../pseudo/lib/grammar/LRTableBuild.cpp            |  61 +-
 clang-tools-extra/pseudo/tool/ClangPseudo.cpp      |  48 +-
 clang-tools-extra/pseudo/unittests/LRTableTest.cpp |   2 +-
 .../test/clang-tidy/check_clang_tidy.py            |  10 +-
 .../bugprone/branch-clone-unknown-expr.cpp         |   9 +
 clang/cmake/caches/Fuchsia-stage2.cmake            |   8 +-
 clang/cmake/caches/Fuchsia.cmake                   |   1 -
 clang/docs/ClangFormat.rst                         |  84 ++-
 clang/include/clang/AST/ASTImportError.h           |   1 -
 clang/include/clang/AST/JSONNodeDumper.h           |   2 +
 clang/include/clang/AST/Stmt.h                     |  38 +-
 clang/include/clang/AST/TextNodeDumper.h           |   1 +
 clang/include/clang/Basic/LangOptions.h            |  13 +
 clang/include/clang/Basic/riscv_vector.td          |  99 +--
 clang/include/clang/Sema/ScopeInfo.h               |   7 +-
 clang/include/clang/Support/RISCVVIntrinsicUtils.h |   2 +
 clang/lib/AST/ASTContext.cpp                       |   3 +
 clang/lib/AST/ASTImporter.cpp                      |  17 +-
 clang/lib/AST/Interp/ByteCodeExprGen.cpp           |   2 +-
 clang/lib/AST/JSONNodeDumper.cpp                   |  15 +
 clang/lib/AST/Stmt.cpp                             |  24 +-
 clang/lib/AST/StmtPrinter.cpp                      |  62 ++
 clang/lib/AST/TextNodeDumper.cpp                   |   6 +
 clang/lib/Analysis/BodyFarm.cpp                    |   3 +-
 clang/lib/Basic/LangOptions.cpp                    |   9 +
 clang/lib/CodeGen/CGCoroutine.cpp                  |   4 +-
 clang/lib/Driver/ToolChains/Clang.cpp              |  63 +-
 clang/lib/Format/ContinuationIndenter.cpp          |   4 +-
 clang/lib/Format/Format.cpp                        |  25 +-
 clang/lib/Format/TokenAnnotator.cpp                |   8 +-
 clang/lib/Sema/Sema.cpp                            |   3 +-
 clang/lib/Sema/SemaDeclCXX.cpp                     |   8 +-
 clang/lib/Sema/SemaExprCXX.cpp                     |   5 +-
 clang/lib/Sema/SemaOpenMP.cpp                      |   9 +-
 clang/lib/Sema/SemaStmt.cpp                        |  11 +-
 clang/lib/Serialization/ASTReaderStmt.cpp          |   8 +-
 clang/lib/Serialization/ASTWriterStmt.cpp          |   3 +
 clang/test/AST/ast-dump-fpfeatures.cpp             |  46 ++
 clang/test/AST/ast-dump-pragma-json.c              | 485 +++++++++++++
 clang/test/AST/ast-print-fp-pragmas.c              |  69 ++
 clang/test/Driver/modules.m                        |  30 +-
 clang/test/Frontend/optimization-remark-options.c  |   2 +-
 clang/test/Modules/Inputs/concept/A.cppm           |   3 -
 clang/test/Modules/Inputs/concept/foo.h            |  13 -
 clang/test/Modules/concept.cppm                    |  50 +-
 clang/tools/clang-format/ClangFormat.cpp           |  10 +-
 clang/tools/clang-offload-packager/CMakeLists.txt  |   1 +
 .../ClangOffloadPackager.cpp                       |   9 +-
 clang/unittests/Format/FormatTest.cpp              |  19 +
 clang/utils/TableGen/RISCVVEmitter.cpp             |  10 +
 compiler-rt/lib/lsan/lsan_allocator.cpp            |   2 +
 .../TestCases/Linux/malloc_usable_size.c           |  21 +
 flang/lib/Lower/ConvertType.cpp                    |   4 +
 flang/lib/Optimizer/Builder/FIRBuilder.cpp         |   5 +-
 flang/lib/Optimizer/CodeGen/CodeGen.cpp            |  49 +-
 flang/test/Lower/extent_triplets.f90               |  11 +
 libc/lib/CMakeLists.txt                            |   9 +-
 libc/test/src/string/memory_utils/CMakeLists.txt   |  17 +-
 libcxx/docs/Status/RangesAlgorithms.csv            |  10 +-
 libcxx/include/CMakeLists.txt                      |   2 +
 libcxx/include/__algorithm/nth_element.h           |  11 +-
 libcxx/include/__algorithm/partial_sort.h          |   9 +-
 libcxx/include/__algorithm/ranges_merge.h          | 142 ++++
 libcxx/include/__algorithm/sort.h                  |   7 +-
 libcxx/include/__debug                             |  16 -
 libcxx/include/__debug_utils/randomize_range.h     |  42 ++
 libcxx/include/__hash_table                        |  16 +-
 libcxx/include/__mutex_base                        |  12 +-
 libcxx/include/__split_buffer                      |  26 +-
 libcxx/include/__tree                              |  32 +-
 libcxx/include/__tuple                             |   6 +-
 libcxx/include/algorithm                           |  18 +
 libcxx/include/array                               |   7 +-
 libcxx/include/exception                           |   4 +-
 libcxx/include/forward_list                        |  42 +-
 libcxx/include/list                                |  16 +-
 libcxx/include/map                                 |  52 +-
 libcxx/include/module.modulemap.in                 |   6 +
 libcxx/include/tuple                               |  16 +-
 libcxx/include/unordered_map                       |  12 +-
 ...ges_robust_against_copying_comparators.pass.cpp |   6 +-
 ...ges_robust_against_copying_projections.pass.cpp |   6 +-
 libcxx/test/libcxx/private_headers.verify.cpp      |   2 +
 .../alg.sorting/alg.merge/ranges_merge.pass.cpp    | 613 +++++++++++++++++
 .../niebloid.compile.pass.cpp                      |   2 +-
 llvm/bindings/go/llvm/ir.go                        |  10 -
 llvm/bindings/ocaml/llvm/llvm.ml                   |   2 -
 llvm/bindings/ocaml/llvm/llvm.mli                  |   5 -
 llvm/bindings/ocaml/llvm/llvm_ocaml.c              |  17 -
 llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst                | 764 +++++++++++----------
 llvm/docs/AMDGPU/gfx10_hwreg.rst                   |  42 +-
 .../AMDGPU/{gfx10_opt.rst => gfx10_opt_0d447d.rst} |   4 +-
 .../AMDGPU/{gfx10_opt.rst => gfx10_opt_847aed.rst} |   2 +-
 ...soffset_c40a5a.rst => gfx10_soffset_73dae7.rst} |   6 +-
 ...soffset_59fade.rst => gfx10_soffset_d01a5c.rst} |   6 +-
 ...x10_vdata_c61803.rst => gfx10_vdata_0aba12.rst} |   4 +-
 ...x10_vdata_87fb90.rst => gfx10_vdata_16d321.rst} |   4 +-
 ...x10_vdata_325b78.rst => gfx10_vdata_35851e.rst} |   6 +-
 ...x10_vdata_b2a787.rst => gfx10_vdata_890652.rst} |   4 +-
 ...x10_vdata_4d8ecf.rst => gfx10_vdata_a9ff5a.rst} |   6 +-
 ...gfx10_vdst_48d3a8.rst => gfx10_vdst_2ea017.rst} |   6 +-
 ...gfx10_vdst_a49b76.rst => gfx10_vdst_322561.rst} |   6 +-
 ...gfx10_vdst_5d50a1.rst => gfx10_vdst_709347.rst} |   4 +-
 llvm/docs/AMDGPU/gfx10_vdst_719833.rst             |  21 -
 ...gfx10_vdst_a49b76.rst => gfx10_vdst_81a6ed.rst} |   4 +-
 ...gfx10_vdst_d7c57e.rst => gfx10_vdst_d71f1c.rst} |   4 +-
 ...gfx10_vdst_f47754.rst => gfx10_vdst_dd8a32.rst} |   4 +-
 llvm/docs/DeveloperPolicy.rst                      |  38 +-
 llvm/docs/LangRef.rst                              |  16 +-
 llvm/docs/ReleaseNotes.rst                         |   2 +
 llvm/include/llvm-c/Core.h                         |   3 -
 llvm/include/llvm/CodeGen/AsmPrinter.h             |   7 +-
 llvm/include/llvm/IR/Constants.h                   |  11 -
 .../Vectorize/LoopVectorizationLegality.h          |   7 -
 llvm/lib/Analysis/BranchProbabilityInfo.cpp        |   6 +-
 llvm/lib/Analysis/ConstantFolding.cpp              |   8 +-
 llvm/lib/Analysis/MemoryBuiltins.cpp               |   6 +-
 llvm/lib/Analysis/ScalarEvolution.cpp              |   8 +-
 llvm/lib/AsmParser/LLParser.cpp                    |  28 +-
 llvm/lib/Bitcode/Writer/BitcodeWriter.cpp          |   3 -
 llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp         |  91 ++-
 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp      |  24 +-
 .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp   |   9 +-
 .../lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h |   2 +-
 llvm/lib/ExecutionEngine/Orc/LLJIT.cpp             |   5 +-
 llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp          |   8 +-
 llvm/lib/IR/AsmWriter.cpp                          |   4 -
 llvm/lib/IR/Constants.cpp                          |  44 +-
 llvm/lib/IR/ConstantsContext.h                     |  60 +-
 llvm/lib/IR/Core.cpp                               |  12 -
 llvm/lib/ObjCopy/ELF/ELFObject.cpp                 |   7 +-
 llvm/lib/Target/AArch64/AArch64ISelLowering.cpp    |  88 ++-
 llvm/lib/Target/AArch64/AArch64ISelLowering.h      |   5 +
 llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td     |  59 +-
 llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp    |   4 +-
 llvm/lib/Target/LoongArch/LoongArchAsmPrinter.h    |   4 +
 .../Target/LoongArch/LoongArchFloat32InstrInfo.td  |   8 +
 .../Target/LoongArch/LoongArchFloat64InstrInfo.td  |   8 +
 llvm/lib/Target/LoongArch/LoongArchFrameLowering.h |   6 +
 .../lib/Target/LoongArch/LoongArchISelLowering.cpp | 154 +++++
 llvm/lib/Target/LoongArch/LoongArchISelLowering.h  |   4 +
 llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp   |  70 +-
 llvm/lib/Target/LoongArch/LoongArchInstrInfo.h     |  10 +
 llvm/lib/Target/LoongArch/LoongArchInstrInfo.td    | 143 +++-
 llvm/lib/Target/LoongArch/LoongArchMCInstLower.cpp |  24 +-
 .../lib/Target/LoongArch/LoongArchRegisterInfo.cpp |  24 +-
 llvm/lib/Target/NVPTX/NVPTXGenericToNVVM.cpp       |   4 -
 llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp          |  45 +-
 llvm/lib/Target/RISCV/RISCVFrameLowering.cpp       |  65 +-
 llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp        | 120 +++-
 llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h          |  12 +-
 llvm/lib/Target/RISCV/RISCVInstrInfo.cpp           |   6 +-
 llvm/lib/Target/RISCV/RISCVInstrInfo.h             |   5 +-
 llvm/lib/Target/RISCV/RISCVInstrInfo.td            |   1 -
 llvm/lib/Target/RISCV/RISCVInstrInfoV.td           |   9 +-
 llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td |  36 +-
 llvm/lib/Target/RISCV/RISCVInstrInfoZb.td          |  23 +-
 llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp        |   2 +-
 llvm/lib/Target/X86/X86ISelLowering.cpp            |  10 +-
 llvm/lib/Transforms/IPO/MergeFunctions.cpp         |   2 +-
 llvm/lib/Transforms/IPO/PruneEH.cpp                |   2 +-
 llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp     |   2 +-
 .../Transforms/InstCombine/InstCombineAddSub.cpp   |  78 ++-
 .../Transforms/InstCombine/InstCombineAndOrXor.cpp |  10 +
 .../Transforms/InstCombine/InstCombineCalls.cpp    |   2 +-
 .../Transforms/InstCombine/InstCombineCasts.cpp    |   9 +-
 .../InstCombine/InstructionCombining.cpp           |   8 +-
 llvm/lib/Transforms/Scalar/DFAJumpThreading.cpp    |   2 +-
 llvm/lib/Transforms/Scalar/LoopDistribute.cpp      |   2 +-
 llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp  |   2 +-
 .../Transforms/Scalar/LowerMatrixIntrinsics.cpp    |  28 +-
 llvm/lib/Transforms/Scalar/Reassociate.cpp         |  21 +-
 .../Transforms/Scalar/TailRecursionElimination.cpp |   4 +-
 .../Transforms/Utils/ScalarEvolutionExpander.cpp   |   3 +-
 llvm/lib/Transforms/Utils/SimplifyCFG.cpp          |   5 +-
 .../Vectorize/LoopVectorizationLegality.cpp        |   1 -
 .../Vectorize/LoopVectorizationPlanner.h           |  10 +-
 llvm/lib/Transforms/Vectorize/LoopVectorize.cpp    | 300 +++++---
 llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp    |  14 +-
 llvm/lib/Transforms/Vectorize/VPlan.cpp            |  24 +
 llvm/lib/Transforms/Vectorize/VPlan.h              |   3 +
 llvm/lib/Transforms/Vectorize/VectorCombine.cpp    | 164 ++++-
 .../ScalarEvolution/annotation-intrinsics.ll       |   4 +-
 llvm/test/Assembler/insertextractvalue.ll          |  28 -
 llvm/test/Assembler/insertvalue-invalid-type-1.ll  |   7 -
 llvm/test/Assembler/unsupported-constexprs.ll      |  17 +-
 .../Inputs/bitcode-parseconstant-delay-select.bc   | Bin 0 -> 1420 bytes
 .../Bitcode/bitcode-parseconstant-delay-select.ll  |   2 +-
 .../CodeGen/AArch64/global-merge-group-by-use.ll   |  68 +-
 .../CodeGen/AArch64/sve-extract-scalable-vector.ll | 336 +++++++++
 .../AArch64/sve-fix-length-and-combine-512.ll      |  36 +-
 llvm/test/CodeGen/AArch64/sve-fp-reduce.ll         | 323 +++++----
 llvm/test/CodeGen/AArch64/sve-insert-vector.ll     | 668 ++++++++++++++++++
 llvm/test/CodeGen/AArch64/vector-gep.ll            |  17 +-
 llvm/test/CodeGen/AArch64/vselect-ext.ll           | 241 ++++++-
 llvm/test/CodeGen/AArch64/win64_vararg.ll          | 357 ++++++----
 llvm/test/CodeGen/AArch64/win64_vararg_float.ll    | 197 ++++--
 llvm/test/CodeGen/AArch64/win64_vararg_float_cc.ll | 221 ++++--
 llvm/test/CodeGen/LoongArch/ir-instruction/br.ll   | 358 ++++++++++
 llvm/test/CodeGen/LoongArch/ir-instruction/call.ll |  79 +++
 .../CodeGen/LoongArch/ir-instruction/indirectbr.ll |  30 +
 .../CodeGen/LoongArch/ir-instruction/load-store.ll | 368 ++++++++++
 llvm/test/CodeGen/PowerPC/aix-alias-alignment-2.ll |  79 +++
 llvm/test/CodeGen/PowerPC/aix-alias-alignment.ll   |  74 ++
 llvm/test/CodeGen/PowerPC/aix-alias.ll             |  16 +-
 llvm/test/CodeGen/RISCV/rv64zba.ll                 | 205 ++++++
 .../RISCV/rvv/access-fixed-objects-by-rvv.ll       |  16 +-
 .../CodeGen/RISCV/rvv/addi-rvv-stack-object.mir    |  60 ++
 llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll   |  98 +--
 llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll        |  62 +-
 llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll | 162 ++---
 llvm/test/CodeGen/RISCV/rvv/calling-conv.ll        |  18 +-
 llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll         |  24 -
 llvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll        |  12 -
 llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll         |  24 -
 .../CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll     |  16 +-
 .../RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll | 111 ++-
 .../RISCV/rvv/fixed-vectors-calling-conv.ll        | 301 ++++----
 .../CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll  | 148 ++--
 .../CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll |  36 +-
 .../RISCV/rvv/fixed-vectors-insert-subvector.ll    |   5 +-
 .../CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll   |  10 +-
 .../RISCV/rvv/fixed-vectors-mask-buildvec.ll       |  24 +-
 .../RISCV/rvv/fixed-vectors-masked-gather.ll       | 112 +--
 .../RISCV/rvv/fixed-vectors-masked-scatter.ll      | 122 ++--
 .../RISCV/rvv/fixed-vectors-reduction-int-vp.ll    |  32 +-
 .../RISCV/rvv/fixed-vectors-reduction-int.ll       |  24 +-
 .../RISCV/rvv/fixed-vectors-setcc-int-vp.ll        |  36 +-
 .../CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll     |  16 +-
 .../CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll     |  16 +-
 .../CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll     |  16 +-
 .../CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll    |  16 +-
 .../CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll     |  16 +-
 .../test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll |  16 +-
 .../CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll     |   8 +-
 .../CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll     |  16 +-
 .../CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll    |  16 +-
 .../CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll    |  16 +-
 llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll |   8 +-
 .../test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll |   8 +-
 llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll |   8 +-
 .../test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll |   8 +-
 .../CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll     |  16 +-
 .../CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll     |  16 +-
 llvm/test/CodeGen/RISCV/rvv/frameindex-addr.ll     |   3 +-
 llvm/test/CodeGen/RISCV/rvv/localvar.ll            |  68 +-
 llvm/test/CodeGen/RISCV/rvv/masked-tama.ll         |   4 +-
 llvm/test/CodeGen/RISCV/rvv/memory-args.ll         |   2 +-
 llvm/test/CodeGen/RISCV/rvv/rvv-args-by-mem.ll     |  19 +-
 llvm/test/CodeGen/RISCV/rvv/rvv-out-arguments.ll   |  60 +-
 llvm/test/CodeGen/RISCV/rvv/rvv-stack-align.mir    |  22 +-
 llvm/test/CodeGen/RISCV/rvv/scalar-stack-align.ll  |  24 +-
 llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll        |  72 +-
 llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll       |  40 +-
 llvm/test/CodeGen/RISCV/rvv/stepvector.ll          |   7 +-
 llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll         |  10 +-
 llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll         |  18 +-
 llvm/test/CodeGen/RISCV/rvv/vaadd.ll               |  16 +-
 llvm/test/CodeGen/RISCV/rvv/vaaddu.ll              |  16 +-
 llvm/test/CodeGen/RISCV/rvv/vadc-rv32.ll           |   8 +-
 llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll         |   8 +-
 llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll             |  16 +-
 llvm/test/CodeGen/RISCV/rvv/vadd.ll                |  16 +-
 llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll           |  16 +-
 llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll         |   8 +-
 llvm/test/CodeGen/RISCV/rvv/vand-vp.ll             |  16 +-
 llvm/test/CodeGen/RISCV/rvv/vasub.ll               |  16 +-
 llvm/test/CodeGen/RISCV/rvv/vasubu.ll              |  16 +-
 llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll           |  16 +-
 llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll         |  16 +-
 llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll             |  16 +-
 llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll          |  16 +-
 llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll        |  16 +-
 llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll            |  16 +-
 llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll          |  12 +-
 llvm/test/CodeGen/RISCV/rvv/vmadc-rv32.ll          |   8 +-
 llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv32.ll |   8 +-
 llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll          |  12 +-
 llvm/test/CodeGen/RISCV/rvv/vmadd-sdnode.ll        |   8 +-
 llvm/test/CodeGen/RISCV/rvv/vmax-rv32.ll           |  16 +-
 llvm/test/CodeGen/RISCV/rvv/vmax-sdnode.ll         |   8 +-
 llvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll          |  16 +-
 llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode.ll        |   8 +-
 llvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll           |  16 +-
 llvm/test/CodeGen/RISCV/rvv/vmin-sdnode.ll         |   8 +-
 llvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll          |  16 +-
 llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll        |   8 +-
 llvm/test/CodeGen/RISCV/rvv/vmsbc-rv32.ll          |   8 +-
 .../test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv32.ll |   8 +-
 llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll          |  12 +-
 llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll          |  18 +-
 llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll         |  18 +-
 llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll          |  12 +-
 llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll         |  12 +-
 llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll          |  12 +-
 llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll         |  12 +-
 llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll          |  12 +-
 llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll         |  12 +-
 llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll          |  12 +-
 llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll         |   8 +-
 llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll             |  16 +-
 llvm/test/CodeGen/RISCV/rvv/vmul.ll                |  16 +-
 llvm/test/CodeGen/RISCV/rvv/vmulh.ll               |  16 +-
 llvm/test/CodeGen/RISCV/rvv/vmulhsu.ll             |  16 +-
 llvm/test/CodeGen/RISCV/rvv/vmulhu.ll              |  16 +-
 llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv32.ll        |   8 +-
 llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll         |  12 +-
 llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll         |  12 +-
 llvm/test/CodeGen/RISCV/rvv/vnmsub-sdnode.ll       |   8 +-
 llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll            |  16 +-
 llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll          |   8 +-
 llvm/test/CodeGen/RISCV/rvv/vor-vp.ll              |  16 +-
 llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll      |   8 +-
 llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll  |  60 +-
 llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll     |  12 +-
 llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll           |  16 +-
 llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll         |  16 +-
 llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll             |  16 +-
 llvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll          |  16 +-
 llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll        |  16 +-
 llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll            |  16 +-
 llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode.ll        |   8 +-
 llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll            |  16 +-
 llvm/test/CodeGen/RISCV/rvv/vrsub.ll               |  16 +-
 llvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll          |  16 +-
 llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll        |   8 +-
 llvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll         |  16 +-
 llvm/test/CodeGen/RISCV/rvv/vsaddu-sdnode.ll       |   8 +-
 llvm/test/CodeGen/RISCV/rvv/vsbc-rv32.ll           |   8 +-
 llvm/test/CodeGen/RISCV/rvv/vselect-int-rv32.ll    |   8 +-
 llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll          |  16 +-
 llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll         |  12 +-
 llvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll          |  16 +-
 llvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll        |   8 +-
 llvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll         |  16 +-
 llvm/test/CodeGen/RISCV/rvv/vssubu-sdnode.ll       |   8 +-
 llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll         |   8 +-
 llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll             |  16 +-
 llvm/test/CodeGen/RISCV/rvv/vsub.ll                |  16 +-
 llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll           |  16 +-
 llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll         |   8 +-
 llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll             |  16 +-
 .../test/CodeGen/RISCV/srem-seteq-illegal-types.ll |  74 +-
 .../test/CodeGen/RISCV/urem-seteq-illegal-types.ll |   4 +-
 llvm/test/CodeGen/X86/fold-tied-op.ll              | 119 +++-
 llvm/test/CodeGen/X86/nonconst-static-iv.ll        |   8 -
 llvm/test/CodeGen/X86/pr56351.ll                   |  18 +
 llvm/test/DebugInfo/AArch64/debug-reg-bank.ll      |  43 ++
 llvm/test/DebugInfo/X86/debug-reg-bank.ll          |  43 ++
 llvm/test/LTO/X86/diagnostic-handler-remarks.ll    |   4 +-
 .../dfa-jump-threading-transform.ll                |   4 +-
 .../DFAJumpThreading/dfa-unfold-select.ll          |   6 +-
 llvm/test/Transforms/InstCombine/and.ll            |  60 ++
 .../Transforms/InstCombine/sadd-with-overflow.ll   |   2 +-
 llvm/test/Transforms/InstCombine/sitofp.ll         |  31 +-
 .../Transforms/InstCombine/ssub-with-overflow.ll   |   2 +-
 llvm/test/Transforms/InstCombine/sub-minmax.ll     | 145 +++-
 .../Transforms/InstCombine/uadd-with-overflow.ll   |   2 +-
 llvm/test/Transforms/InstCombine/with_overflow.ll  |  30 +-
 .../AArch64/runtime-check-size-based-threshold.ll  |  18 +-
 .../AArch64/sve-tail-folding-forced.ll             |   2 +-
 .../AArch64/sve-tail-folding-unroll.ll             |   4 +-
 .../LoopVectorize/AArch64/sve-tail-folding.ll      |  22 +-
 .../Transforms/LoopVectorize/X86/gather_scatter.ll |   2 +-
 .../X86/pointer-runtime-checks-unprofitable.ll     |  60 +-
 llvm/test/Transforms/LoopVectorize/X86/pr23997.ll  |   2 +-
 llvm/test/Transforms/LoopVectorize/X86/pr35432.ll  |   2 +-
 llvm/test/Transforms/LoopVectorize/X86/pr54634.ll  |   2 +-
 .../Transforms/LoopVectorize/X86/runtime-limit.ll  |  22 +-
 .../bigger-expressions-double.ll                   |  12 +-
 .../multiply-right-transpose.ll                    |   4 +-
 .../LowerMatrixIntrinsics/propagate-backward.ll    |  12 +-
 .../propagate-backwards-unsupported.ll             |  18 +-
 .../LowerMatrixIntrinsics/propagate-forward.ll     |  16 +-
 .../LowerMatrixIntrinsics/propagate-mixed-users.ll |   8 +-
 .../propagate-multiple-iterations.ll               |   8 +-
 .../transpose-double-row-major.ll                  |  18 +-
 .../LowerMatrixIntrinsics/transpose-double.ll      |  26 +-
 .../transpose-float-row-major.ll                   |  18 +-
 .../LowerMatrixIntrinsics/transpose-float.ll       |  26 +-
 .../transpose-i32-row-major.ll                     |  18 +-
 .../LowerMatrixIntrinsics/transpose-i32.ll         |  26 +-
 .../transpose-opts-iterator-invalidation.ll        |   4 +-
 .../LowerMatrixIntrinsics/transpose-opts.ll        |  12 +-
 .../MergeFunc/mergefunc-struct-return.ll           |   2 +-
 .../Transforms/SLPVectorizer/AArch64/loadorder.ll  | 151 ++--
 .../X86/load-partial-vector-shuffle.ll             |  73 ++
 .../2010-06-26-MultipleReturnValues.ll             |   6 +-
 .../Transforms/TailCallElim/accum_recursion.ll     |   2 +-
 llvm/test/Transforms/TailCallElim/basic.ll         |   2 +-
 .../VectorCombine/AArch64/select-shuffle.ll        | 260 ++++---
 .../Transforms/WholeProgramDevirt/expand-check.ll  |   2 +-
 llvm/test/tools/llvm-ar/Inputs/mri-crlf.mri        |   2 +
 llvm/test/tools/llvm-ar/mri-crlf.test              |   9 +-
 llvm/test/tools/llvm-ar/mri-delete.test            | 188 ++++-
 llvm/test/tools/llvm-ar/mri-end.test               | 140 ++--
 llvm/test/tools/llvm-ar/mri-nonascii.test          |  37 +-
 .../tools/llvm-objcopy/ELF/binary-no-paddr.test    |  22 +-
 llvm/test/tools/llvm-objcopy/ELF/binary-paddr.test |  40 ++
 llvm/utils/UpdateTestChecks/asm.py                 |   3 +-
 llvm/utils/gn/secondary/libcxx/include/BUILD.gn    |   2 +
 mlir/cmake/modules/AddMLIRPython.cmake             |   2 +-
 mlir/docs/Dialects/Affine.md                       |   4 +-
 mlir/include/mlir/Dialect/Complex/IR/ComplexOps.td |   4 +
 mlir/include/mlir/Dialect/Linalg/Utils/Utils.h     |   9 +
 mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td      | 180 ++++-
 .../mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td     |   2 +-
 mlir/include/mlir/Dialect/SCF/IR/SCFOps.td         | 109 ---
 mlir/include/mlir/Dialect/Tensor/IR/Tensor.h       |   1 +
 mlir/include/mlir/Dialect/Tensor/IR/TensorOps.td   | 149 ++++
 mlir/include/mlir/Dialect/Vector/IR/VectorOps.td   |   1 +
 mlir/include/mlir/IR/AffineMap.h                   |   6 +
 mlir/lib/Dialect/Affine/IR/AffineOps.cpp           |   2 +-
 mlir/lib/Dialect/Complex/IR/ComplexOps.cpp         |  28 +
 mlir/lib/Dialect/Linalg/Transforms/CMakeLists.txt  |   2 +-
 .../lib/Dialect/Linalg/Transforms/DropUnitDims.cpp |  28 -
 ...onsumer.cpp => FusePadOpWithLinalgProducer.cpp} |   2 +-
 mlir/lib/Dialect/Linalg/Utils/Utils.cpp            |  28 +
 mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp       |  55 +-
 mlir/lib/Dialect/SCF/IR/CMakeLists.txt             |   1 -
 mlir/lib/Dialect/SCF/IR/SCF.cpp                    | 143 +---
 .../SCF/Transforms/BufferizableOpInterfaceImpl.cpp | 246 +------
 mlir/lib/Dialect/Tensor/IR/CMakeLists.txt          |   1 +
 mlir/lib/Dialect/Tensor/IR/TensorOps.cpp           | 256 +++++--
 .../Transforms/BufferizableOpInterfaceImpl.cpp     | 244 +++++++
 mlir/lib/Dialect/Vector/IR/VectorOps.cpp           |  37 +-
 .../Dialect/Vector/Transforms/VectorTransforms.cpp |  21 +-
 mlir/lib/ExecutionEngine/OptUtils.cpp              |   2 +-
 mlir/lib/ExecutionEngine/SparseTensorUtils.cpp     |   2 +-
 mlir/lib/IR/AffineMap.cpp                          |  19 +-
 mlir/lib/Parser/AffineParser.cpp                   |  44 +-
 .../Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp   |  27 +
 mlir/test/Dialect/Complex/canonicalize.mlir        |  20 +
 mlir/test/Dialect/OpenMP/invalid.mlir              | 125 ++++
 mlir/test/Dialect/OpenMP/ops.mlir                  | 142 +++-
 mlir/test/Dialect/SCF/canonicalize.mlir            |  25 -
 .../SCF/foreach-thread-canonicalization.mlir       |  50 +-
 mlir/test/Dialect/SCF/invalid.mlir                 |   8 +-
 .../one-shot-bufferize-tensor-copy-insertion.mlir  |   4 +-
 mlir/test/Dialect/SCF/one-shot-bufferize.mlir      |   6 +-
 mlir/test/Dialect/SCF/ops.mlir                     |   4 +-
 mlir/test/Dialect/Tensor/canonicalize.mlir         |  27 +
 mlir/test/Dialect/Vector/canonicalize.mlir         |  14 +
 mlir/test/Dialect/Vector/invalid.mlir              |   2 +-
 .../Dialect/Vector/vector-reduce-to-contract.mlir  |  35 +
 mlir/test/IR/affine-set.mlir                       |  81 +++
 mlir/test/IR/invalid.mlir                          |  18 +-
 mlir/test/Target/LLVMIR/openmp-llvm.mlir           |  88 +++
 utils/bazel/llvm-project-overlay/clang/BUILD.bazel |   6 +-
 utils/bazel/llvm-project-overlay/mlir/BUILD.bazel  |   2 +
 455 files changed, 11835 insertions(+), 5145 deletions(-)
 create mode 100644 clang-tools-extra/test/clang-tidy/checkers/bugprone/branch-clon [...]
 create mode 100644 clang/test/AST/ast-dump-pragma-json.c
 create mode 100644 clang/test/AST/ast-print-fp-pragmas.c
 delete mode 100644 clang/test/Modules/Inputs/concept/A.cppm
 delete mode 100644 clang/test/Modules/Inputs/concept/foo.h
 create mode 100644 compiler-rt/test/sanitizer_common/TestCases/Linux/malloc_usable_size.c
 create mode 100644 flang/test/Lower/extent_triplets.f90
 create mode 100644 libcxx/include/__algorithm/ranges_merge.h
 create mode 100644 libcxx/include/__debug_utils/randomize_range.h
 create mode 100644 libcxx/test/std/algorithms/alg.sorting/alg.merge/ranges_merge.pass.cpp
 copy llvm/docs/AMDGPU/{gfx10_opt.rst => gfx10_opt_0d447d.rst} (83%)
 rename llvm/docs/AMDGPU/{gfx10_opt.rst => gfx10_opt_847aed.rst} (91%)
 rename llvm/docs/AMDGPU/{gfx10_soffset_c40a5a.rst => gfx10_soffset_73dae7.rst} (72%)
 rename llvm/docs/AMDGPU/{gfx10_soffset_59fade.rst => gfx10_soffset_d01a5c.rst} (61%)
 rename llvm/docs/AMDGPU/{gfx10_vdata_c61803.rst => gfx10_vdata_0aba12.rst} (80%)
 rename llvm/docs/AMDGPU/{gfx10_vdata_87fb90.rst => gfx10_vdata_16d321.rst} (80%)
 rename llvm/docs/AMDGPU/{gfx10_vdata_325b78.rst => gfx10_vdata_35851e.rst} (81%)
 rename llvm/docs/AMDGPU/{gfx10_vdata_b2a787.rst => gfx10_vdata_890652.rst} (80%)
 rename llvm/docs/AMDGPU/{gfx10_vdata_4d8ecf.rst => gfx10_vdata_a9ff5a.rst} (81%)
 rename llvm/docs/AMDGPU/{gfx10_vdst_48d3a8.rst => gfx10_vdst_2ea017.rst} (76%)
 copy llvm/docs/AMDGPU/{gfx10_vdst_a49b76.rst => gfx10_vdst_322561.rst} (71%)
 rename llvm/docs/AMDGPU/{gfx10_vdst_5d50a1.rst => gfx10_vdst_709347.rst} (76%)
 delete mode 100644 llvm/docs/AMDGPU/gfx10_vdst_719833.rst
 rename llvm/docs/AMDGPU/{gfx10_vdst_a49b76.rst => gfx10_vdst_81a6ed.rst} (75%)
 rename llvm/docs/AMDGPU/{gfx10_vdst_d7c57e.rst => gfx10_vdst_d71f1c.rst} (75%)
 rename llvm/docs/AMDGPU/{gfx10_vdst_f47754.rst => gfx10_vdst_dd8a32.rst} (75%)
 delete mode 100644 llvm/test/Assembler/insertvalue-invalid-type-1.ll
 create mode 100644 llvm/test/Bitcode/Inputs/bitcode-parseconstant-delay-select.bc
 create mode 100644 llvm/test/CodeGen/LoongArch/ir-instruction/br.ll
 create mode 100644 llvm/test/CodeGen/LoongArch/ir-instruction/call.ll
 create mode 100644 llvm/test/CodeGen/LoongArch/ir-instruction/indirectbr.ll
 create mode 100644 llvm/test/CodeGen/LoongArch/ir-instruction/load-store.ll
 create mode 100644 llvm/test/CodeGen/PowerPC/aix-alias-alignment-2.ll
 create mode 100644 llvm/test/CodeGen/PowerPC/aix-alias-alignment.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/addi-rvv-stack-object.mir
 delete mode 100644 llvm/test/CodeGen/X86/nonconst-static-iv.ll
 create mode 100644 llvm/test/CodeGen/X86/pr56351.ll
 create mode 100644 llvm/test/DebugInfo/AArch64/debug-reg-bank.ll
 create mode 100644 llvm/test/DebugInfo/X86/debug-reg-bank.ll
 create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/load-partial-vector-shuffle.ll
 rename mlir/lib/Dialect/Linalg/Transforms/{FusePadOpWithLinalgConsumer.cpp => Fuse [...]
 create mode 100644 mlir/test/IR/affine-set.mlir
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[Tcwg-commits] [toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_bmk_llvm_tx1/llvm-master-aarch64-spec2k6-O3 updated (40d2ef841b68 -> 0c01f42fad41)