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from b5361254c902 Merge tag 'modules-6.13-rc1' of git://git.kernel.org/pub/s [...] new 4bb21dbb6728 mm: Use str_on_off() helper function in report_meminit() new 98b7beba1ee6 memblock: uniformly initialize all reserved pages to MIGRA [...] new ab952fc5c736 Merge tag 'memblock-v6.13-rc1' of git://git.kernel.org/pub [...] new 1b9bc4207e81 Merge tag 'sched-core-2024-11-18' into loongarch-next new e67e0eb6a98b LoongArch: Explicitly specify code model in Makefile new 947d5d036c78 LoongArch: Fix build failure with GCC 15 (-std=gnu23) new 73c359d1d356 LoongArch: BPF: Sign-extend return values new af4b67da6522 LoongArch: Reduce min_delta for the arch clockevent device new 88fd2b70120d LoongArch: Fix sleeping in atomic context for PREEMPT_RT new 826d2af6949f LoongArch: Select HAVE_POSIX_CPU_TIMERS_TASK_WORK new be2ea982bb83 LoongArch: Allow to enable PREEMPT_RT new 704f06eeff65 LoongArch: Allow to enable PREEMPT_LAZY new b7915af6e73b LoongArch: dts: Add I2S support to Loongson-2K1000 new 900f6267e9e3 LoongArch: dts: Add I2S support to Loongson-2K2000 new 3c272a7551af LoongArch: Update Loongson-3 default config file new c94696977527 Merge tag 'loongarch-6.13' of git://git.kernel.org/pub/scm [...] new 1b57747e978f riscv: Enable cbo.zero only when all harts support Zicboz new 5fc7355f0137 riscv: Add support for per-thread envcfg CSR values new 368546ebe7e7 riscv: Call riscv_user_isa_enable() only on the boot hart new 1540def11f0c Merge patch series "riscv: Per-thread envcfg CSR support" new 5fb0ecf73e7a riscv: defconfig: enable gpio support for TH1520 new f8a23e3b79d6 cpuidle: riscv-sbi: Move sbi_cpuidle_init to arch_initcall new 27b4d6aa29ab cpuidle: riscv-sbi: Add cpuidle_disabled() check new 77270206955d Merge patch series "cpuidle: riscv-sbi: Allow cpuidle pd u [...] new 8d20a739f17a RISC-V: Check scalar unaligned access on all CPUs new 9c528b5f7927 RISC-V: Scalar unaligned access emulated on hotplug CPUs new c05a62c92516 RISC-V: Replace RISCV_MISALIGNED with RISCV_SCALAR_MISALIGNED new d1703dc7bc8e RISC-V: Detect unaligned vector accesses supported new e7c9d66e313b RISC-V: Report vector unaligned access speed hwprobe new 40e09ebd791f RISC-V: hwprobe: Document unaligned vector perf key new 18efe86bf266 Merge patch series "RISC-V: Detect and report speed of una [...] new c6898d66fd19 riscv: Check that vdso does not contain any dynamic relocations new ce16531d48e3 Merge patch series "Prevent dynamic relocations in vDSO" new 8727163a1ae3 dt-bindings: riscv: Add pointer masking ISA extensions new 2e6f6ea452aa riscv: Add ISA extension parsing for pointer masking new 29eedc7d1587 riscv: Add CSR definitions for pointer masking new 09d6775f503b riscv: Add support for userspace pointer masking new 2e1743085887 riscv: Add support for the tagged address ABI new 78844482a1c9 riscv: Allow ptrace control of the tagged address ABI new 7470b5afd150 riscv: selftests: Add a pointer masking test new 3c2e0aff7b4f riscv: hwprobe: Export the Supm ISA extension new 1851e7836212 RISC-V: KVM: Allow Smnpm and Ssnpm extensions for guests new 036a1407b4d4 KVM: riscv: selftests: Add Smnpm and Ssnpm to get-reg-list test new 075fde581896 Merge patch series "riscv: Userspace pointer masking and t [...] new 010e12aa4925 riscv: Move cpufeature.h macros into their own header new af042c457db0 riscv: Do not fail to build on byte/halfword operations wi [...] new 38acdee32d23 riscv: Implement cmpxchg32/64() using Zacas new 51624ddcf59d dt-bindings: riscv: Add Zabha ISA extension description new 1658ef4314b3 riscv: Implement cmpxchg8/16() using Zabha new 6116e22ef33a riscv: Improve zacas fully-ordered cmpxchg() new f7bd2be7663c riscv: Implement arch_cmpxchg128() using Zacas new 97ddab7fbea8 riscv: Implement xchg8/16() using Zabha new cbe82e140bb7 asm-generic: ticket-lock: Reuse arch_spinlock_t of qspinlock new 22c33321e260 asm-generic: ticket-lock: Add separate ticket-lock.h new 2d36fe89d872 riscv: Add ISA extension parsing for Ziccrse new 447b2afbcde1 dt-bindings: riscv: Add Ziccrse ISA extension description new ab83647fadae riscv: Add qspinlock support new 64f7b77f0bd9 Merge patch series "Zacas/Zabha support and qspinlocks" new 0eb512779d64 riscv: Fix default misaligned access trap new 8d4f1e05ff82 RISC-V: Remove unnecessary include from compat.h new 91dbbe6c9ffe Merge tag 'riscv-for-linus-6.13-mw1' of git://git.kernel.o [...]
The 61 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.
Summary of changes: Documentation/arch/riscv/hwprobe.rst | 19 ++ Documentation/arch/riscv/uabi.rst | 16 + .../devicetree/bindings/riscv/extensions.yaml | 30 ++ .../locking/queued-spinlocks/arch-support.txt | 2 +- arch/loongarch/Kconfig | 3 + arch/loongarch/Makefile | 4 +- arch/loongarch/boot/dts/loongson-2k1000.dtsi | 17 +- arch/loongarch/boot/dts/loongson-2k2000.dtsi | 22 +- arch/loongarch/configs/loongson3_defconfig | 91 +++++- arch/loongarch/include/asm/thread_info.h | 8 +- arch/loongarch/kernel/time.c | 6 +- arch/loongarch/mm/tlb.c | 2 +- arch/loongarch/net/bpf_jit.c | 2 +- arch/loongarch/vdso/Makefile | 2 +- arch/riscv/Kconfig | 138 ++++++++- arch/riscv/Makefile | 6 + arch/riscv/configs/defconfig | 1 + arch/riscv/include/asm/Kbuild | 4 +- arch/riscv/include/asm/cmpxchg.h | 286 +++++++++++++----- arch/riscv/include/asm/compat.h | 1 - arch/riscv/include/asm/cpufeature-macros.h | 66 ++++ arch/riscv/include/asm/cpufeature.h | 73 +---- arch/riscv/include/asm/csr.h | 16 + arch/riscv/include/asm/entry-common.h | 1 + arch/riscv/include/asm/hwcap.h | 7 + arch/riscv/include/asm/hwprobe.h | 2 +- arch/riscv/include/asm/mmu.h | 7 + arch/riscv/include/asm/mmu_context.h | 13 + arch/riscv/include/asm/processor.h | 9 + arch/riscv/include/asm/spinlock.h | 47 +++ arch/riscv/include/asm/switch_to.h | 19 ++ arch/riscv/include/asm/uaccess.h | 43 ++- arch/riscv/include/asm/vector.h | 2 + arch/riscv/include/uapi/asm/hwprobe.h | 6 + arch/riscv/include/uapi/asm/kvm.h | 2 + arch/riscv/kernel/Makefile | 3 +- arch/riscv/kernel/copy-unaligned.h | 5 + arch/riscv/kernel/cpufeature.c | 16 +- arch/riscv/kernel/fpu.S | 4 +- arch/riscv/kernel/process.c | 154 ++++++++++ arch/riscv/kernel/ptrace.c | 42 +++ arch/riscv/kernel/setup.c | 37 +++ arch/riscv/kernel/smpboot.c | 2 - arch/riscv/kernel/suspend.c | 4 +- arch/riscv/kernel/sys_hwprobe.c | 44 +++ arch/riscv/kernel/traps_misaligned.c | 139 ++++++++- arch/riscv/kernel/unaligned_access_speed.c | 156 +++++++++- arch/riscv/kernel/vdso/Makefile | 9 +- arch/riscv/kernel/vec-copy-unaligned.S | 58 ++++ arch/riscv/kernel/vector.c | 2 +- arch/riscv/kvm/vcpu_onereg.c | 4 + drivers/cpuidle/cpuidle-riscv-sbi.c | 11 +- include/asm-generic/qspinlock.h | 2 + include/asm-generic/spinlock.h | 87 +----- include/asm-generic/spinlock_types.h | 12 +- .../asm-generic/{spinlock.h => ticket_spinlock.h} | 49 +-- include/uapi/linux/elf.h | 1 + include/uapi/linux/prctl.h | 5 +- mm/mm_init.c | 7 +- tools/testing/selftests/kvm/riscv/get-reg-list.c | 8 + tools/testing/selftests/riscv/Makefile | 2 +- tools/testing/selftests/riscv/abi/.gitignore | 1 + .../selftests/riscv/{sigreturn => abi}/Makefile | 6 +- .../testing/selftests/riscv/abi/pointer_masking.c | 332 +++++++++++++++++++++ 64 files changed, 1845 insertions(+), 330 deletions(-) create mode 100644 arch/riscv/include/asm/cpufeature-macros.h create mode 100644 arch/riscv/include/asm/spinlock.h create mode 100644 arch/riscv/kernel/vec-copy-unaligned.S copy include/asm-generic/{spinlock.h => ticket_spinlock.h} (57%) create mode 100644 tools/testing/selftests/riscv/abi/.gitignore copy tools/testing/selftests/riscv/{sigreturn => abi}/Makefile (50%) create mode 100644 tools/testing/selftests/riscv/abi/pointer_masking.c