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from 5cdc52d125e PR c++/64095 - auto... parameter pack. new b8408bbc21d RISC-V: Fix for combine bug with shift and AND operations.
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Summary of changes: gcc/ChangeLog | 11 +++ gcc/config/riscv/riscv.h | 4 +- gcc/config/riscv/riscv.md | 136 ++++++++++++++++++++++++++- gcc/config/riscv/sync.md | 5 +- gcc/testsuite/ChangeLog | 6 ++ gcc/testsuite/gcc.target/riscv/pr84660.c | 17 ++++ gcc/testsuite/gcc.target/riscv/shift-and-1.c | 10 ++ gcc/testsuite/gcc.target/riscv/shift-and-2.c | 41 ++++++++ 8 files changed, 223 insertions(+), 7 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/pr84660.c create mode 100644 gcc/testsuite/gcc.target/riscv/shift-and-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/shift-and-2.c