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from cfc8374c458 [CGP] add an IR builder to memcmp expansion class instead o [...] new e2d935510ce [AMDGPU] Combine and x, (sext cc from i1) => select cc, x, 0 new 197bda66359 [SROA] Fix APInt size when alloca address space is not 0 new d841eae40bb RenameIndependentSubregs: Fix infinite loop
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Summary of changes: lib/CodeGen/RenameIndependentSubregs.cpp | 3 ++- lib/Target/AMDGPU/SIISelLowering.cpp | 30 +++++++++++++++++++-- lib/Transforms/Scalar/SROA.cpp | 5 ++-- test/CodeGen/AMDGPU/combine-and-sext-bool.ll | 27 +++++++++++++++++++ test/CodeGen/AMDGPU/combine-cond-add-sub.ll | 20 ++++++++++++++ ...=> rename-independent-subregs-mac-operands.mir} | 19 +++++++++++++ test/Transforms/SROA/alloca-address-space.ll | 31 +++++++++++++++++++++- 7 files changed, 129 insertions(+), 6 deletions(-) create mode 100644 test/CodeGen/AMDGPU/combine-and-sext-bool.ll rename test/CodeGen/AMDGPU/{rename-independent-subregs-invalid-mac-operands.mir => [...]