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from ab6e2d9f6f2 [PATCH v2] RISC-V: Use vclmul for CRC expansion if available new ee7c0a5b70d i386/cygming: Decrease default preferred stack boundary for [...] new 36daa0da95f [V2][RISC-V] Synthesize more efficient IOR/XOR sequences
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Summary of changes: gcc/config/i386/cygming.h | 9 +- gcc/config/i386/i386.cc | 9 + gcc/config/riscv/iterators.md | 3 + gcc/config/riscv/predicates.md | 12 +- gcc/config/riscv/riscv-protos.h | 1 + gcc/config/riscv/riscv.cc | 199 +++++++++++++++++++++++ gcc/config/riscv/riscv.md | 11 +- gcc/testsuite/gcc.target/riscv/ior-synthesis-1.c | 8 + gcc/testsuite/gcc.target/riscv/ior-synthesis-2.c | 8 + gcc/testsuite/gcc.target/riscv/xor-synthesis-1.c | 8 + gcc/testsuite/gcc.target/riscv/xor-synthesis-2.c | 10 ++ gcc/testsuite/gcc.target/riscv/xor-synthesis-3.c | 8 + 12 files changed, 271 insertions(+), 15 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/ior-synthesis-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/ior-synthesis-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/xor-synthesis-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/xor-synthesis-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/xor-synthesis-3.c