This is an automated email from the git hooks/post-receive script.
unknown user pushed a change to branch master in repository gcc.
from 0df6d181230 i386: Emit compares between high registers and memory new 978e8f02e8e RISC-V: Align IOR optimization MODE_CLASS condition to AND. new 9fdea28d6ac RISC-V: Support 128 bit vector chunk
The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.
Summary of changes: gcc/config/riscv/riscv-modes.def | 89 ++-- gcc/config/riscv/riscv-v.cc | 17 +- gcc/config/riscv/riscv-vector-builtins.cc | 11 +- gcc/config/riscv/riscv-vector-builtins.def | 172 ++++--- gcc/config/riscv/riscv-vector-switch.def | 105 ++-- gcc/config/riscv/riscv.cc | 12 +- gcc/config/riscv/riscv.md | 14 +- gcc/config/riscv/vector-iterators.md | 571 ++++++++++++--------- gcc/config/riscv/vector.md | 233 +++++++-- gcc/simplify-rtx.cc | 4 +- .../gcc.target/riscv/rvv/base/mask_insn_shortcut.c | 3 +- .../gcc.target/riscv/rvv/base/pr108185-4.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/spill-1.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/spill-2.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/spill-3.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/spill-5.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c | 2 +- .../gcc.target/riscv/simplify_ior_optimization.c | 50 ++ 19 files changed, 836 insertions(+), 459 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/simplify_ior_optimization.c