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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allnoconfig in repository toolchain/ci/llvm-project.
from 805d59593f5 [Analysis, CodeGen, IR] Use contains (NFC) adds 195f44278c4 [ARM] Implement harden-sls-retbr for ARM mode adds c061cb521b9 [gn build] Port 195f44278c4 adds 320fd3314e3 [ARM] Implement harden-sls-retbr for Thumb mode adds a4c1f5160e6 [ARM] Harden indirect calls against SLS adds df8ed392837 [ARM] harden-sls-blr: avoid r12 and lr in indirect calls. adds 9c895aea118 [ARM] Add clang command line support for -mharden-sls= adds 9cf3b1b6665 [RISCV] Define vlxe/vsxe/vsuxe intrinsics. adds 5740f96d8ee [NFC][libc++] Fixes swapped comments. adds 1e785e92624 apply update_test_checks.py to a few files in llvm/test/Tra [...] adds 56edfcada90 [Target, Transforms] Use contains (NFC) adds a6516a820d3 [Analysis] Remove dead function getInstTypePair (NFC) adds f47b07315a3 [X86] Teach assembler to accept vmsave/vmload/vmrun/invlpga [...] adds c52bcf3a9b2 [IRSim][IROutliner] Limit to extracting regions that only r [...] adds b43b77ff9b8 [NFCI][SimlifyCFG] simplifyOnce(): also perform DomTree validation adds 4be8707e645 [SimplifyCFG] Teach FoldTwoEntryPHINode() to preserve DomTree adds 76e74d93950 [SimplifyCFG] Teach removeEmptyCleanup() to preserve DomTree adds c209b88dd43 [SimplifyCFG] Teach simplifyCommonResume() to preserve DomTree adds b7d00e29b77 [SimplifyCFG] Teach simplifySingleResume() to preserve DomTree adds 83659c70767 [SimplifyCFG] simplifySingleResume(): FoldReturnIntoUncondB [...] adds 4d87a6ad13c [NFCI][SimplifyCFG] SimplifyCondBranchToTwoReturns(): pull [...] adds b94520c9ee2 [SimplifyCFG] Teach SimplifyCondBranchToTwoReturns() to pre [...] adds 6a1617d67cc [SimplifyCFG] Teach SimplifyCondBranchToTwoReturns() to pre [...] adds 262ff9c23e7 [SimplifyCFG] Teach TryToMergeLandingPad() to preserve DomTree adds c043f5055e8 [SimplifyCFG] Teach FoldBranchToCommonDest() to preserve Do [...] adds 99930719c66 Handle overflow beyond the 127 common encodings limit adds 0cbceed27c4 [TableGen][ARM][X86] Detect combining IntrReadMem and IntrW [...] adds 5cdc4f57e50 [IROutliner] Deduplicating functions that only require inputs. adds b8a2b6af374 Revert "[IROutliner] Deduplicating functions that only requ [...] adds 7c6f28a438b [IROutliner] Deduplicating functions that only require inputs. adds 0985a8bfea4 Fix left shift overflow UB in PPC backend on LLP64 platforms adds c1d6de41a9d [mlir][CAPI] Add the missing <stdbool.h> in Support.h new 37974b493a4 [lldb/test] Enable reverse-connect on windows too new 62c94f06781 [RISCV] Define vector vfmul/vfdiv/vfrdiv intrinsics. new bd576ac8d4b [RISCV] Define vector vfsgnj/vfsgnjn/vfsgnjx intrinsics. new f86e61d8862 [RISCV] Define vector vfwadd/vfwsub intrinsics. new 41ab45d6624 [RISCV] Define vector vfwmul intrinsics. new 99562332e3d [lldb] [test] Update test status for NetBSD
The 6 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.
Summary of changes: clang/include/clang/Basic/DiagnosticDriverKinds.td | 2 + clang/lib/Driver/ToolChains/Arch/ARM.cpp | 45 + clang/lib/Driver/ToolChains/Arch/ARM.h | 1 + clang/test/Driver/aarch64-sls-hardening-options.c | 45 - clang/test/Driver/sls-hardening-options.c | 97 + .../libcxx/iterators/trivial_iterators.pass.cpp | 4 +- lld/MachO/UnwindInfoSection.cpp | 213 +- lld/MachO/UnwindInfoSection.h | 31 +- lld/test/MachO/tools/generate-cfi-funcs.py | 2 +- lld/test/MachO/tools/validate-unwind-info.py | 13 +- .../test/tools/lldb-server/gdbremote_testcase.py | 4 - .../api/multiple-targets/TestMultipleTargets.py | 1 + .../call-restarts/TestCallThatRestarts.py | 2 +- .../expression/ir-interpreter/TestIRInterpreter.py | 1 - .../expression/radar_9531204/TestPrintfAfterUp.py | 1 - .../save_jit_objects/TestSaveJITObjects.py | 1 - .../test/API/commands/expression/test/TestExprs.py | 1 - .../API/commands/gui/viewlarge/TestGuiViewLarge.py | 1 + .../commands/process/attach/TestProcessAttach.py | 1 + .../cpp_exception/TestCPPExceptionBreakpoint.py | 2 - .../TestBreakpointInGlobalConstructor.py | 1 - .../functionalities/completion/TestCompletion.py | 1 + .../TestDlopenOtherExecutable.py | 1 + .../inferior-assert/TestInferiorAssert.py | 4 - .../TestRecursiveInferiorStep.py | 1 + ...ConcurrentBreakpointDelayBreakpointOneSignal.py | 1 - .../TestConcurrentSignalDelayBreak.py | 2 +- .../TestConcurrentTwoBreakpointsOneDelaySignal.py | 2 +- .../TestConcurrentTwoBreakpointsOneSignal.py | 2 +- .../TestExitDuringExpression.py | 2 + .../TestStateAfterExpression.py | 1 + .../TestThreadSpecificBpPlusCondition.py | 2 +- .../unwind/noreturn/TestNoreturnUnwind.py | 1 - .../c/conflicting-symbol/TestConflictingSymbol.py | 1 - .../lang/c/const_variables/TestConstVariables.py | 1 - .../API/lang/c/function_types/TestFunctionTypes.py | 1 - .../lang/c/global_variables/TestGlobalVariables.py | 1 - lldb/test/API/lang/c/shared_lib/TestSharedLib.py | 2 - .../cpp/exceptions/TestCPPExceptionBreakpoints.py | 1 - .../TestNamespaceDefinitions.py | 1 - .../test/API/lang/cpp/stl/TestStdCXXDisassembly.py | 1 - lldb/test/API/lang/cpp/this/TestCPPThis.py | 1 - lldb/test/API/python_api/event/TestEvents.py | 2 +- .../lldbutil/iter/TestRegistersIterator.py | 1 + lldb/test/API/python_api/thread/TestThreadAPI.py | 1 - .../lldb-server/TestGdbRemote_vContThreads.py | 2 + .../TestVSCode_setExceptionBreakpoints.py | 1 - .../disconnect/TestVSCode_disconnect.py | 1 + lldb/test/Shell/Recognizer/assert.test | 1 + .../Functionalities/TestExpressionEvaluation.test | 2 +- .../ScriptInterpreter/Lua/watchpoint_callback.test | 1 + llvm/include/llvm/IR/IntrinsicsARM.td | 4 +- llvm/include/llvm/IR/IntrinsicsRISCV.td | 58 +- llvm/include/llvm/IR/IntrinsicsX86.td | 7 +- llvm/include/llvm/Transforms/IPO/IROutliner.h | 57 +- llvm/include/llvm/Transforms/Utils/Local.h | 3 +- llvm/lib/Analysis/MemDepPrinter.cpp | 3 - llvm/lib/Target/ARM/ARM.h | 3 + llvm/lib/Target/ARM/ARM.td | 14 + llvm/lib/Target/ARM/ARMAsmPrinter.cpp | 42 + llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 51 +- llvm/lib/Target/ARM/ARMBaseInstrInfo.h | 65 + llvm/lib/Target/ARM/ARMCallLowering.cpp | 9 +- llvm/lib/Target/ARM/ARMConstantIslandPass.cpp | 11 + llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp | 5 +- llvm/lib/Target/ARM/ARMFastISel.cpp | 14 +- llvm/lib/Target/ARM/ARMFeatures.h | 1 + llvm/lib/Target/ARM/ARMISelLowering.cpp | 2 +- llvm/lib/Target/ARM/ARMInstrInfo.td | 35 +- llvm/lib/Target/ARM/ARMInstrThumb.td | 13 +- llvm/lib/Target/ARM/ARMInstrThumb2.td | 9 + llvm/lib/Target/ARM/ARMPredicates.td | 3 + llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp | 12 +- llvm/lib/Target/ARM/ARMRegisterInfo.td | 17 + llvm/lib/Target/ARM/ARMSLSHardening.cpp | 416 ++ llvm/lib/Target/ARM/ARMSubtarget.h | 10 + llvm/lib/Target/ARM/ARMTargetMachine.cpp | 4 + llvm/lib/Target/ARM/CMakeLists.txt | 1 + llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 2 +- llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp | 2 +- llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td | 388 +- llvm/lib/Target/X86/X86InstrSVM.td | 28 +- llvm/lib/Transforms/IPO/IROutliner.cpp | 472 +- .../lib/Transforms/Scalar/DeadStoreElimination.cpp | 3 +- llvm/lib/Transforms/Utils/LoopSimplify.cpp | 2 +- llvm/lib/Transforms/Utils/SimplifyCFG.cpp | 134 +- llvm/test/CodeGen/ARM/O3-pipeline.ll | 4 + llvm/test/CodeGen/ARM/speculation-hardening-sls.ll | 246 + llvm/test/CodeGen/RISCV/rvv/vfdiv-rv32.ll | 881 +++ llvm/test/CodeGen/RISCV/rvv/vfdiv-rv64.ll | 1201 +++++ llvm/test/CodeGen/RISCV/rvv/vfmul-rv32.ll | 881 +++ llvm/test/CodeGen/RISCV/rvv/vfmul-rv64.ll | 1201 +++++ llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv32.ll | 441 ++ llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv64.ll | 601 +++ llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv32.ll | 881 +++ llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv64.ll | 1201 +++++ llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv32.ll | 881 +++ llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv64.ll | 1201 +++++ llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv32.ll | 881 +++ llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv64.ll | 1201 +++++ llvm/test/CodeGen/RISCV/rvv/vfwadd-rv32.ll | 401 ++ llvm/test/CodeGen/RISCV/rvv/vfwadd-rv64.ll | 721 +++ llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll | 401 ++ llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll | 721 +++ llvm/test/CodeGen/RISCV/rvv/vfwmul-rv32.ll | 401 ++ llvm/test/CodeGen/RISCV/rvv/vfwmul-rv64.ll | 721 +++ llvm/test/CodeGen/RISCV/rvv/vfwsub-rv32.ll | 401 ++ llvm/test/CodeGen/RISCV/rvv/vfwsub-rv64.ll | 721 +++ llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll | 401 ++ llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll | 721 +++ llvm/test/CodeGen/RISCV/rvv/vlxe-rv32.ll | 3281 ++++++++++++ llvm/test/CodeGen/RISCV/rvv/vlxe-rv64.ll | 5361 +++++++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vsuxe-rv32.ll | 3445 ++++++++++++ llvm/test/CodeGen/RISCV/rvv/vsuxe-rv64.ll | 5629 ++++++++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vsxe-rv32.ll | 3445 ++++++++++++ llvm/test/CodeGen/RISCV/rvv/vsxe-rv64.ll | 5629 ++++++++++++++++++++ llvm/test/MC/Disassembler/X86/simple-tests.txt | 10 +- llvm/test/MC/X86/SVM-32.s | 30 +- llvm/test/MC/X86/SVM-64.s | 30 +- llvm/test/MC/X86/x86-32-coverage.s | 10 +- llvm/test/MC/X86/x86-32.s | 10 +- llvm/test/Transforms/Coroutines/coro-heap-elide.ll | 2 +- llvm/test/Transforms/GVNSink/indirect-call.ll | 2 +- llvm/test/Transforms/GVNSink/sink-common-code.ll | 2 +- llvm/test/Transforms/IROutliner/extraction.ll | 50 +- llvm/test/Transforms/IROutliner/illegal-assumes.ll | 38 +- .../test/Transforms/IROutliner/illegal-branches.ll | 4 +- llvm/test/Transforms/IROutliner/illegal-callbr.ll | 8 +- llvm/test/Transforms/IROutliner/illegal-calls.ll | 8 +- .../test/Transforms/IROutliner/illegal-catchpad.ll | 4 +- llvm/test/Transforms/IROutliner/illegal-cleanup.ll | 4 +- llvm/test/Transforms/IROutliner/illegal-frozen.ll | 4 +- llvm/test/Transforms/IROutliner/illegal-gep.ll | 4 +- llvm/test/Transforms/IROutliner/illegal-invoke.ll | 4 +- .../Transforms/IROutliner/illegal-landingpad.ll | 4 +- llvm/test/Transforms/IROutliner/illegal-memcpy.ll | 40 +- llvm/test/Transforms/IROutliner/illegal-memmove.ll | 40 +- llvm/test/Transforms/IROutliner/illegal-memset.ll | 4 +- .../Transforms/IROutliner/illegal-phi-nodes.ll | 4 +- llvm/test/Transforms/IROutliner/illegal-vaarg.ll | 30 +- llvm/test/Transforms/IROutliner/legal-debug.ll | 4 +- .../IROutliner/outlining-address-taken.ll | 4 +- .../IROutliner/outlining-constants-vs-registers.ll | 78 + ...ructure.ll => outlining-different-constants.ll} | 30 +- .../IROutliner/outlining-different-globals.ll | 40 + .../IROutliner/outlining-different-structure.ll | 8 +- .../IROutliner/outlining-same-constants.ll | 11 +- .../IROutliner/outlining-same-globals.ll | 13 +- llvm/test/Transforms/InstCombine/X86/x86-sse4a.ll | 18 +- llvm/test/Transforms/InstCombine/bitcast.ll | 12 +- .../Transforms/InstCombine/insert-const-shuf.ll | 20 +- .../SimplifyCFG/2004-12-10-SimplifyCFGCrash.ll | 2 +- .../Transforms/SimplifyCFG/2005-06-16-PHICrash.ll | 2 +- .../SimplifyCFG/2005-08-01-PHIUpdateFail.ll | 2 +- .../Transforms/SimplifyCFG/2006-08-03-Crash.ll | 2 +- .../Transforms/SimplifyCFG/2008-12-16-DCECond.ll | 2 +- .../SimplifyCFG/2011-09-05-TrivialLPad.ll | 2 +- .../SimplifyCFG/ARM/speculate-vector-ops.ll | 4 +- llvm/test/Transforms/SimplifyCFG/BrUnwind.ll | 2 +- llvm/test/Transforms/SimplifyCFG/DeadSetCC.ll | 2 +- llvm/test/Transforms/SimplifyCFG/HoistCode.ll | 2 +- .../Transforms/SimplifyCFG/UncondBranchToReturn.ll | 2 +- .../Transforms/SimplifyCFG/UnreachableEliminate.ll | 2 +- .../SimplifyCFG/X86/2010-03-30-InvokeCrash.ll | 2 +- .../SimplifyCFG/X86/CoveredLookupTable.ll | 2 +- llvm/test/Transforms/SimplifyCFG/X86/bug-25299.ll | 2 +- .../SimplifyCFG/X86/disable-lookup-table.ll | 2 +- llvm/test/Transforms/SimplifyCFG/X86/pr39187-g.ll | 2 +- .../SimplifyCFG/X86/switch-covered-bug.ll | 2 +- .../Transforms/SimplifyCFG/X86/switch-table-bug.ll | 2 +- llvm/test/Transforms/SimplifyCFG/branch-fold.ll | 2 +- .../Transforms/SimplifyCFG/branch-phi-thread.ll | 2 +- .../SimplifyCFG/debug-info-thread-phi.ll | 2 +- .../SimplifyCFG/duplicate-ret-into-uncond-br.ll | 31 + llvm/test/Transforms/SimplifyCFG/extract-cost.ll | 2 +- .../SimplifyCFG/fold-branch-to-common-dest.ll | 2 +- .../Transforms/SimplifyCFG/hoist-common-code.ll | 2 +- .../Transforms/SimplifyCFG/hoist-with-range.ll | 2 +- llvm/test/Transforms/SimplifyCFG/indirectbr.ll | 2 +- llvm/test/Transforms/SimplifyCFG/invoke_unwind.ll | 2 +- .../Transforms/SimplifyCFG/lifetime-landingpad.ll | 2 +- .../merge-duplicate-conditional-ret-val.ll | 21 + llvm/test/Transforms/SimplifyCFG/pr39807.ll | 2 +- llvm/test/Transforms/SimplifyCFG/pr46638.ll | 2 +- .../SimplifyCFG/preserve-branchweights-partial.ll | 4 +- .../SimplifyCFG/preserve-branchweights.ll | 2 +- llvm/test/Transforms/SimplifyCFG/rangereduce.ll | 2 +- .../Transforms/SimplifyCFG/switch-masked-bits.ll | 2 +- .../SimplifyCFG/switch-on-const-select.ll | 2 +- .../Transforms/SimplifyCFG/switch-range-to-icmp.ll | 2 +- .../SimplifyCFG/switch-simplify-crash.ll | 2 +- .../SimplifyCFG/switch-to-select-two-case.ll | 2 +- .../Transforms/SimplifyCFG/switch_switch_fold.ll | 2 +- llvm/test/Transforms/SimplifyCFG/switch_thread.ll | 2 +- .../test/Transforms/SimplifyCFG/unprofitable-pr.ll | 2 +- llvm/test/tools/llvm-mca/X86/Atom/resources-sse1.s | 2 +- .../tools/llvm-mca/X86/Atom/resources-x86_64.s | 4 +- .../tools/llvm-mca/X86/Barcelona/resources-sse1.s | 2 +- .../llvm-mca/X86/Barcelona/resources-x86_64.s | 4 +- .../tools/llvm-mca/X86/BdVer2/resources-avx1.s | 2 +- .../tools/llvm-mca/X86/BdVer2/resources-sse1.s | 2 +- .../tools/llvm-mca/X86/BdVer2/resources-x86_64.s | 4 +- .../tools/llvm-mca/X86/Broadwell/resources-avx1.s | 2 +- .../tools/llvm-mca/X86/Broadwell/resources-sse1.s | 2 +- .../llvm-mca/X86/Broadwell/resources-x86_64.s | 4 +- .../tools/llvm-mca/X86/BtVer2/resources-avx1.s | 2 +- .../tools/llvm-mca/X86/BtVer2/resources-sse1.s | 2 +- .../tools/llvm-mca/X86/BtVer2/resources-x86_64.s | 4 +- .../tools/llvm-mca/X86/BtVer2/stmxcsr-ldmxcsr.s | 10 +- .../tools/llvm-mca/X86/Generic/resources-avx1.s | 2 +- .../tools/llvm-mca/X86/Generic/resources-sse1.s | 2 +- .../tools/llvm-mca/X86/Generic/resources-x86_64.s | 4 +- .../tools/llvm-mca/X86/Haswell/resources-avx1.s | 2 +- .../tools/llvm-mca/X86/Haswell/resources-sse1.s | 2 +- .../tools/llvm-mca/X86/Haswell/resources-x86_64.s | 4 +- .../tools/llvm-mca/X86/Haswell/stmxcsr-ldmxcsr.s | 26 +- llvm/test/tools/llvm-mca/X86/SLM/resources-sse1.s | 2 +- .../test/tools/llvm-mca/X86/SLM/resources-x86_64.s | 4 +- .../llvm-mca/X86/SandyBridge/resources-avx1.s | 2 +- .../llvm-mca/X86/SandyBridge/resources-sse1.s | 2 +- .../llvm-mca/X86/SandyBridge/resources-x86_64.s | 4 +- .../llvm-mca/X86/SkylakeClient/resources-avx1.s | 2 +- .../llvm-mca/X86/SkylakeClient/resources-sse1.s | 2 +- .../llvm-mca/X86/SkylakeClient/resources-x86_64.s | 4 +- .../llvm-mca/X86/SkylakeServer/resources-avx1.s | 2 +- .../llvm-mca/X86/SkylakeServer/resources-sse1.s | 2 +- .../llvm-mca/X86/SkylakeServer/resources-x86_64.s | 4 +- .../tools/llvm-mca/X86/Znver1/resources-avx1.s | 2 +- .../tools/llvm-mca/X86/Znver1/resources-sse1.s | 2 +- .../tools/llvm-mca/X86/Znver1/resources-x86_64.s | 4 +- .../tools/llvm-mca/X86/Znver2/resources-avx1.s | 2 +- .../tools/llvm-mca/X86/Znver2/resources-sse1.s | 2 +- .../tools/llvm-mca/X86/Znver2/resources-x86_64.s | 4 +- llvm/utils/TableGen/CodeGenTarget.cpp | 14 +- .../gn/secondary/llvm/lib/Target/ARM/BUILD.gn | 1 + mlir/include/mlir-c/Support.h | 1 + 236 files changed, 46679 insertions(+), 708 deletions(-) delete mode 100644 clang/test/Driver/aarch64-sls-hardening-options.c create mode 100644 clang/test/Driver/sls-hardening-options.c create mode 100644 llvm/lib/Target/ARM/ARMSLSHardening.cpp create mode 100644 llvm/test/CodeGen/ARM/speculation-hardening-sls.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfdiv-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfdiv-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmul-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmul-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwadd-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwadd-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwmul-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwmul-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwsub-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwsub-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vlxe-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vlxe-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vsuxe-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vsuxe-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vsxe-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vsxe-rv64.ll create mode 100644 llvm/test/Transforms/IROutliner/outlining-constants-vs-registers.ll copy llvm/test/Transforms/IROutliner/{outlining-different-structure.ll => outlinin [...] create mode 100644 llvm/test/Transforms/IROutliner/outlining-different-globals.ll create mode 100644 llvm/test/Transforms/SimplifyCFG/duplicate-ret-into-uncond-br.ll create mode 100644 llvm/test/Transforms/SimplifyCFG/merge-duplicate-conditional-re [...]