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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-defconfig in repository toolchain/ci/llvm-project.
from 3ab3f3c5d58 After 09158252f777c2e2f06a86b154c44abcbcf9bb74, fix build w [...] adds e8743c0f389 Const-initialize ParsedAttrInfos adds b1f78baeaa1 [InstCombine] Reduce code duplication in GEP of PHI transform; NFC adds 30d712103fa [InstCombine] Use replaceOperand() API in GEP transforms adds e5bf5037d86 [CodeGen] Fix sinking local values in lpads with phis adds 347e31c052d Remove constexpr that MSVC doesn't like adds 4065e92195b Upgrade some instances of std::sort to llvm::sort. NFC. adds ced0d1f42b3 [BPF] support 128bit int explicitly in layout spec adds 2d24d74b859 [AMDGPU] Stabilize sort order adds d3b6e1f1f93 [ADT] Automatically forward llvm::sort to array_pod_sort if safe adds 97cc1275c7d [InstCombine] Merge two functions; NFC adds 2215dcf1d75 [InstCombine] Remove unreachable blocks before DCE adds ba2e72c54ec [MDBuilder] Don't use stable sort for sorting integers. adds b578f130a72 [COFF] Stabilize sort adds dd030036f0a Put back initializers that were dropped in 0ab5b5b8581d9f29 [...] adds 9564f46766f AMDGPU: Make use of default operands adds 09d40218539 Fix compatibility for __builtin_stdarg_start adds fc93787d7e8 [MC][PowerPC] Make .reloc support arbitrary relocation types adds c0aa97b6327 [X86] Add cost model test cases for fmin/fmax reduction. adds 4bf015c035e [AlignmentFromAssumptions] Fix a SCEV assertion resulting f [...] adds 6dab8067123 [mlir] Add exp2 conversion to llvm.intr.exp2 adds a7115d51be0 [X86] X86CallFrameOptimization - generalize slow push code path adds 6ba63510720 [PostOrderIterator] Use SmallVector to store stack; NFC adds 49d00824bbb [VPlan] Use one VPWidenRecipe per original IR instruction. (NFC). adds b632bd88a63 [mlir] NFC: fix trivial typo in documents adds 10439f9e32e [X86][AVX] Add X86ISD::VALIGN target shuffle decode support adds da4c7db793a [X86] Rename matchShuffleAsByteRotate to matchShuffleAsElem [...] adds 7734e4b3a36 [X86][AVX] Combine 128-bit lane shuffles with a zeroable up [...] adds 1e363023b82 [InstCombine] Use replaceOperand() in a few more places adds 6f07a9e80ab [InstCombine] Erase original add when creating saddo adds 28f67bd5c56 [InstCombine] Fix worklist management in varargs transform adds 99913ef3d14 [OpenMP] set_bits iterator yields unsigned elements, no ref [...] adds 26fa33755f1 [InstCombine] Simplify select of cmpxchg transform new b44f07045c5 Remove unnecessary empty comments from test check lines. NFC. new 443dcc0e008 [X86][AVX] Add tests for 512-bit shuffle patterns that coul [...]
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Summary of changes: clang-tools-extra/clang-doc/Representation.cpp | 6 +- clang-tools-extra/clang-tidy/ClangTidy.cpp | 2 +- .../clang-tidy/ClangTidyDiagnosticConsumer.cpp | 4 +- clang-tools-extra/clangd/index/Relation.cpp | 2 +- clang-tools-extra/modularize/CoverageChecker.cpp | 2 +- clang-tools-extra/modularize/Modularize.cpp | 2 +- clang/examples/Attribute/Attribute.cpp | 7 +- clang/include/clang/Basic/Builtins.def | 2 +- clang/include/clang/Sema/ParsedAttr.h | 4 +- clang/lib/Basic/Targets/BPF.h | 4 +- clang/lib/Sema/ParsedAttr.cpp | 4 +- clang/test/CodeGen/target-data.c | 4 +- clang/test/SemaCXX/vararg-non-pod.cpp | 7 + clang/tools/clang-scan-deps/ClangScanDeps.cpp | 30 +- clang/utils/TableGen/ClangAttrEmitter.cpp | 35 +- clang/utils/TableGen/ClangOpenCLBuiltinEmitter.cpp | 2 +- clang/utils/TableGen/SveEmitter.cpp | 2 +- lld/COFF/PDB.cpp | 2 + llvm/include/llvm/ADT/PostOrderIterator.h | 3 +- llvm/include/llvm/ADT/STLExtras.h | 22 +- llvm/include/llvm/Target/TargetOptions.h | 2 + llvm/lib/CodeGen/SelectionDAG/FastISel.cpp | 17 +- llvm/lib/Frontend/OpenMP/OMPContext.cpp | 16 +- llvm/lib/IR/MDBuilder.cpp | 2 +- llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp | 8 +- llvm/lib/Target/AMDGPU/GCNRegPressure.h | 2 +- llvm/lib/Target/AMDGPU/SIInstructions.td | 46 +- llvm/lib/Target/AMDGPU/VOP1Instructions.td | 4 +- llvm/lib/Target/BPF/BPFTargetMachine.cpp | 4 +- .../Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp | 47 +- .../PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp | 6 +- llvm/lib/Target/X86/X86CallFrameOptimization.cpp | 2 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 43 +- .../Transforms/InstCombine/InstCombineCalls.cpp | 2 +- .../Transforms/InstCombine/InstCombineCompares.cpp | 10 +- .../Transforms/InstCombine/InstCombineInternal.h | 6 + .../InstCombine/InstCombineMulDivRem.cpp | 24 +- .../Transforms/InstCombine/InstCombineSelect.cpp | 30 +- .../InstCombine/InstCombineSimplifyDemanded.cpp | 4 +- .../InstCombine/InstructionCombining.cpp | 76 +-- .../Transforms/Scalar/AlignmentFromAssumptions.cpp | 5 + llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 17 +- llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h | 5 +- llvm/lib/Transforms/Vectorize/VPlan.cpp | 3 +- llvm/lib/Transforms/Vectorize/VPlan.h | 25 +- llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp | 15 +- llvm/test/Analysis/CostModel/X86/reduce-fmax.ll | 110 +++++ llvm/test/Analysis/CostModel/X86/reduce-fmin.ll | 110 +++++ llvm/test/CodeGen/BPF/i128.ll | 67 +++ llvm/test/CodeGen/X86/atomic-idempotent.ll | 547 ++++++++++++++++----- llvm/test/CodeGen/X86/avx-vperm2x128.ll | 10 +- llvm/test/CodeGen/X86/sink-local-value.ll | 36 ++ llvm/test/CodeGen/X86/vector-reduce-mul.ll | 84 ++-- llvm/test/CodeGen/X86/vector-shuffle-128-v4.ll | 17 +- llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll | 17 +- llvm/test/CodeGen/X86/vector-shuffle-512-v8.ll | 211 ++++---- .../CodeGen/X86/vector-shuffle-combining-avx2.ll | 45 +- llvm/test/CodeGen/X86/vector-shuffle-v1.ll | 10 +- llvm/test/MC/PowerPC/ppc32-reloc-directive.s | 9 + llvm/test/MC/PowerPC/ppc64-reloc-directive.s | 9 + .../AlignmentFromAssumptions/amdgpu-crash.ll | 33 ++ llvm/test/Transforms/InstCombine/gepphigep.ll | 2 +- .../Transforms/Vectorize/VPlanHCFGTest.cpp | 26 +- mlir/docs/ConversionToLLVMDialect.md | 2 +- mlir/docs/CreatingADialect.md | 2 +- mlir/docs/Diagnostics.md | 4 +- mlir/docs/OpDefinitions.md | 2 +- mlir/docs/RationaleLinalgDialect.md | 2 +- mlir/include/mlir/Dialect/GPU/GPUOps.td | 2 +- mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td | 3 +- .../mlir/Dialect/Linalg/IR/LinalgStructuredOps.td | 2 +- .../Linalg/IR/LinalgStructuredOpsInterface.td | 13 +- mlir/include/mlir/Dialect/Quant/QuantOps.td | 4 +- mlir/include/mlir/Dialect/SPIRV/SPIRVBase.td | 2 +- mlir/include/mlir/Dialect/Shape/IR/ShapeOps.td | 2 +- mlir/include/mlir/Dialect/StandardOps/IR/Ops.td | 8 + mlir/include/mlir/Dialect/Vector/VectorOps.td | 4 +- .../mlir/Interfaces/InferTypeOpInterface.td | 3 +- .../Conversion/StandardToLLVM/StandardToLLVM.cpp | 2 + .../StandardToLLVM/convert-to-llvmir.mlir | 22 +- .../StandardToSPIRV/std-types-to-spirv.mlir | 2 +- mlir/test/IR/attribute.mlir | 2 +- mlir/test/Target/llvmir-intrinsics.mlir | 9 + mlir/test/mlir-tblgen/llvm-intrinsics.td | 2 +- 84 files changed, 1383 insertions(+), 621 deletions(-) create mode 100644 llvm/test/Analysis/CostModel/X86/reduce-fmax.ll create mode 100644 llvm/test/Analysis/CostModel/X86/reduce-fmin.ll create mode 100644 llvm/test/CodeGen/BPF/i128.ll create mode 100644 llvm/test/Transforms/AlignmentFromAssumptions/amdgpu-crash.ll