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from 93312b1fb7d [llvm-nm] Allow --size-sort to print symbols with only Symbol size new 43448ef0fe9 [SLP] Fix PR40310: The reduction nodes should stay scalar. new 73f9f91f2ab AMDGPU: Add llvm.amdgcn.ds.ordered.add & swap
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Summary of changes: include/llvm/IR/IntrinsicsAMDGPU.td | 18 ++ lib/Target/AMDGPU/AMDGPU.h | 2 +- lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 1 + lib/Target/AMDGPU/AMDGPUISelLowering.h | 1 + lib/Target/AMDGPU/AMDGPUSearchableTables.td | 2 + lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp | 2 + lib/Target/AMDGPU/DSInstructions.td | 5 + lib/Target/AMDGPU/GCNHazardRecognizer.cpp | 22 +- lib/Target/AMDGPU/SIISelLowering.cpp | 61 +++++ lib/Target/AMDGPU/SIInsertWaitcnts.cpp | 14 +- lib/Target/AMDGPU/SIInstrInfo.cpp | 13 +- lib/Target/AMDGPU/SIInstrInfo.h | 2 + lib/Target/AMDGPU/SIInstrInfo.td | 5 + lib/Transforms/Vectorize/SLPVectorizer.cpp | 3 +- test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add.ll | 96 ++++++++ test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.swap.ll | 45 ++++ test/Transforms/SLPVectorizer/X86/PR39774.ll | 266 ++++++++++++++------- test/Transforms/SLPVectorizer/X86/PR40310.ll | 18 +- 18 files changed, 466 insertions(+), 110 deletions(-) create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.swap.ll