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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_bootstrap/master-aarch64-bootstrap in repository toolchain/ci/binutils-gdb.
from 19c26da69d Add code to display the contents of .debug_loclists sections [...] adds 9716aa0a27 gdb: make interp_add static adds 7fb56b9893 gdb: LoongArch: prepend tramp frame unwinder for signal adds 49fffa58f7 Fix "bins" simulation for v850e3v5 adds 477904ca75 Fix for v850e divq instruction new 6d088eb92e gdb: don't copy entirely optimized out values in value_copy
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Summary of changes: gdb/interps.c | 2 +- gdb/interps.h | 2 -- gdb/loongarch-linux-tdep.c | 50 +++++++++++++++++++++++++++++++++++ gdb/testsuite/gdb.python/py-value.exp | 3 +++ gdb/value.c | 27 +++++++++++++++---- sim/testsuite/v850/allinsns.exp | 2 +- sim/testsuite/v850/bins.cgs | 12 +++++++++ sim/testsuite/v850/divq.cgs | 11 ++++++++ sim/v850/simops.c | 13 ++++++--- 9 files changed, 110 insertions(+), 12 deletions(-) create mode 100644 sim/testsuite/v850/bins.cgs create mode 100644 sim/testsuite/v850/divq.cgs