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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-next-allnoconfig in repository toolchain/ci/llvm-project.
from cdd43eac4fe [Codegen] TargetLowering::SimplifySetCC(): omit urem when possible adds ecd9348aa17 [docs][llvm-cxxfilt] Write llvm-cxxfilt documentation adds a6fd919cb3f [ARM] DLS/LE low-overhead loop code generation adds 47b7d13459a [PowerPC] Emit XXSEL for vec_sel and code that has the same [...] adds 49b3778e32c [TargetLowering] SimplifyDemandedBits - legal checks for SI [...] adds e6824160dd6 [ARM] Add MVE vector load/store instructions. adds 86b7a1e660b [ARM] Add remaining miscellaneous MVE instructions. adds d9654723ad8 [ARM] Extra MVE-related testing. adds 4cf18c28495 [ARM] Explicit lowering of half <-> double conversions. adds b23c942ce43 [VectorLegalizer] ExpandANY_EXTEND_VECTOR_INREG/ExpandZERO_ [...] adds 08e8cb57602 AMDGPU/MC: Add .amdgpu_lds directive adds 2710171a15e AMDGPU: Write LDS objects out as global symbols in code generation adds 74ec25a197a [ARM] MVE VPT Blocks adds 69fc111184f [TargetLowering] SimplifyDemandedBits SIGN_EXTEND_VECTOR_IN [...] adds 287f0403e31 [ARM] Fix buildbot failure due to -Werror. adds 42f44b387e4 Fix frame.s test dir-separator checks adds e4ef62291b4 [SDAG] improve expansion of ctpop+setcc adds 36953ce7696 [TargetLowering] SimplifyDemandedBits ZERO_EXTEND_VECTOR_IN [...] adds d1dc1f4901a AMDGPU: Make amdgcn.s.get.waveid.in.workgroup inaccessiblememonly adds ec18f0f64c5 [ARM] Re-enable misspelled RUN: lines in fullfp16.s. adds b96d9d8bdad [docs][llvm-readobj] Improve llvm-readobj documentation adds 083d9490360 [llvm-objcopy][llvm-strip] Fix help text typo for --allow-b [...] adds d7ffa2a9483 AMDGPU: Select G_SEXT/G_ZEXT/G_ANYEXT adds dcd8b72e1a7 AMDGPU/GlobalISel: Fix duplicated test adds 7c1deeff4a6 Expand cloneLoopWithPreheader() to support cloning loop nest adds 1a18bb6f25f [TargetLowering] SimplifyDemandedBits - add ANY_EXTEND_VECT [...] adds 807d2f442ad [ARM] Fix -Wunused-variable in -DLLVM_ENABLE_ASSERTIONS=off [...] adds aae4b68703b [X86] lowerShuffleAsSpecificZeroOrAnyExtend - add ANY_EXTEND TODO. adds 0baacea2c7e [AArch64][x86] add tests for ctpop != 1; NFC adds 181f252d537 [clang-tidy] Update documentation for Qt Creator integration. adds f4e51dd2cd5 AMDGPU/GlobalISel: Fix broken test adds 34cac0955d7 Options: Correctly check for missing arguments adds f0a665afca7 [AMDGPU] Null checking on TS to avoid crashing in clang tests. adds 685c5cbc654 [SDAG] expand ctpop != 1 adds e98f8cf78f3 [SLPVectorizer] Precommit of supernode.ll test for D63661 adds 36c23cad151 Revert r362743 "Revert "Revert "Reland D61583 [ELF] Error o [...] adds ece53d0ae50 Improve zero-size allocation with safe_malloc, etc. adds bcf0eb7a640 [ARM] Fix for DLS/LE CodeGen adds 96a192ea537 [PPC32] Support PLT calls for -msecure-plt -fpic adds 635eb80662d [Python 3] Decode check_ouput result as UTF-8 adds 9762b26032c [DAGCombine] combineRepeatedFPDivisors - recognize -1.0 / X [...] adds a90fc6617fb [OPENMP]Fix PR41966: type mismatch in runtime functions. adds d0f96be2c78 [FPEnv] A missing crucial step was undocumented. adds a4b415a6839 [ARM] Code-generation infrastructure for MVE. adds 88139c143c5 [AVR] Adjust to Register class change adds e8de8ba6a63 [ARM] Support inline assembler constraints for MVE. adds 37340e3cd62 [scudo][standalone] Introduce the C & C++ wrappers adds 14ea14ae859 [X86] Add a DAG combine to turn vzmovl+load into vzload if [...] adds 97017a8ef9c [CMake] Check that a certificate for lldb is present at bui [...] adds 99a44915275 [Python] Flush prompt before reading input adds be0dedb2e13 [Peephole] Allow folding loads into instructions w/multiple [...] adds 4577b8c17c1 [X86] Remove isel patterns that look for (vzext_movl (scala [...] adds 61d70e4a93d [WebAssembly] Error on archives without a symbol index adds 4be636ebb31 [AMDGPU] Removed dead SIMachineFunctionInfo::getWorkItemIDVGPR() adds 30519a68d5b Add regression test for PR41576 (which is already fixed in [...] adds fcfa056cebf [InstCombine] reduce checks for power-of-2-or-zero using ctpop adds 688afeb8844 Update phis in AMDGPUUnifyDivergentExitNodes adds 7803eac24f3 [llvm-shlib] Do not use version script when building with MinGW adds 510f4098ae0 Add a defensive check for nullptr as in the block above. adds 3ad32a037ef [scudo] Correct a behavior on the shared TSD registry adds c42a3571786 [LFTR] Adjust debug output to include extensions (if any) adds dcd7eb710bc Remove redundant expression evaluation context when substit [...] adds b90cb57b63a [InstCombine] Simplify icmp ult/uge (shl %x, C2), C1 iff C1 [...] adds 8fcc70f1414 Don't look for the TargetFrameLowering in the implementation adds bc7fc3ecb67 [PowerPC][NFC]Add a test for MachinePipeliner bug adds c8e450a9179 [dotest] Remove unused function adds c32d307a49f android: enable double-word CAS on x64 adds fee855b5bc1 [MachinePipeliner] Fix risky iterator usage R++, --R adds 1fa0f4b9424 Change the ABI version and ABI namespace to be `_LIBCPP_VER [...] adds 9c10b620c06 Revert "Add ReadCStringFromMemory for faster string reads" adds 05d1a2bd1bf [GWP-ASan] Guard against recursive allocs. Pack TLS for perf. adds a3eeca333b4 Dump what value failed byval attribute verification adds b37f2f33916 Add github lockdown app to auto-close pull requests. adds a1d688dfdd0 Revert Devirtualize destructor of final class. adds 65d8d6357b8 [WebAssembly] Remove catch_all from AsmParser adds 17c18a9e816 Fix a typo in help text. adds de94ac93577 print-supported-cpus quality of life patch. adds ae9e42f614f Revert "Change the ABI version and ABI namespace to be `_LI [...] adds ad28befcf49 Teach TableGen Intrin Emitter to handle LLVMPointerType<llv [...] adds 628f36ff700 [analyzer] exploded-graph-rewriter: Prettier location conte [...] adds 5242fbde5a2 Add USan+ASan and UBSan+TSan tests to shadow-memory lit par [...] adds cadcb9eb613 [WebAssembly] Fix list of relocations with addends in lld adds c5b8e1c538d [lld/WebAssembly] Slightly nicer error message for malforme [...] adds d38e251bf2f Follow up fix for r364366. adds 06036dbc6e9 MC: correct the emission of weak aliases in COFF adds 5bb0dcd96ec [WebAssembly] Fix accidental omission from rLLD364367 adds 174b4ff781a [PowerPC][NFC] Move peephole optimization of RLDICR into a method. adds 8265e8ff365 [PowerPC] Mark FCOPYSIGN legal for FP vectors adds 169355811dd gn build: Merge r364288. adds 69822ae1060 [PowerPC][NFC] Add a TOC save test case prior to posting a [...] adds 6a4c68e1874 [ARM] Fix -Wimplicit-fallthrough after D60709/r364331 adds 4c64c62b9af [NFC] Fix buildbot breaks due to r364375 adds 4e3f00e9998 Revert [llvm-objcopy][NFCI] Fix build failure with GCC adds 4ee933c76bf Revert [llvm-objcopy][NFC] Refactor output target parsing adds d325eb3b56d Fix build failure due to missing break adds c3dfe9082bc [HIP] Support attribute hip_pinned_shadow adds e0e7d4c3662 Teach the DAGCombine to fold this pattern(c1 and c2 is constant). adds d6a8bc7a125 [PowerPC] Fixed missing change flag of emitRLDICWhenLowerin [...] adds be98e0ab789 [ExpandMemCmp] Honor prefer-vector-width. adds 5dff8ca26a9 [Metadata] Add GNU extensions for call site DWARF symbols adds c3a73023977 [clang][Tooling] Infer target and mode from argv[0] when us [...] adds 84f7377dd99 [clangd] Link and initialize target infos adds 256247cfb73 [clangd] Enable extraction of system includes from custom t [...] adds 8bfe0fc1d9b [clangd] Add Value field to HoverInfo adds ba51fd5664e Reland D61583 [ELF] Error on relocations to STT_SECTION sym [...] adds 442a120567a [clangd] Don't rename the namespace. adds 567eea44c25 [NFC][InstCombine] Add shift amount reassociation tests (PR42391) adds e6474e682aa [compiler-rt][test] Set shared_libasan_path in test/asan/li [...] adds a5bbe8c8b93 [TargetOption] Add option to ebanble the debug entry values adds 0a43d1fa719 [clang][Tooling] Fix windows build-bots after rL364386 new 46ce9e4fff4 [HardwareLoops] NFC - move loop with irreducible control fl [...] new 4c11b5268ca [LoopUnroll] Add support for loops with exiting headers and [...] new 639d36b34e6 [CC1Option] Add the option to enable the debug entry values new 1a0810407ed Revert r364332 "[scudo][standalone] Introduce the C & C++ w [...] new 3845a4f8493 [X86][AVX] truncateVectorWithPACK - avoid bitcasted shuffles
The 5 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.
Summary of changes: .github/lockdown.yml | 33 + clang-tools-extra/clangd/CMakeLists.txt | 2 + clang-tools-extra/clangd/ClangdLSPServer.cpp | 8 +- clang-tools-extra/clangd/ClangdServer.h | 4 + .../clangd/GlobalCompilationDatabase.h | 7 + clang-tools-extra/clangd/QueryDriverDatabase.cpp | 265 +++ clang-tools-extra/clangd/XRefs.cpp | 15 + clang-tools-extra/clangd/XRefs.h | 2 + clang-tools-extra/clangd/refactor/Rename.cpp | 5 + .../clangd/test/system-include-extractor.test | 50 + clang-tools-extra/clangd/test/target_info.test | 34 + clang-tools-extra/clangd/tool/ClangdMain.cpp | 12 + clang-tools-extra/clangd/unittests/RenameTests.cpp | 34 +- clang-tools-extra/clangd/unittests/TestTU.cpp | 5 +- clang-tools-extra/clangd/unittests/XRefsTests.cpp | 73 +- clang-tools-extra/docs/clang-tidy/Integrations.rst | 6 +- clang/bindings/python/tests/cindex/test_cdb.py | 14 +- clang/docs/ClangCommandLineReference.rst | 4 + clang/docs/CommandGuide/clang.rst | 4 + clang/include/clang/Basic/Attr.td | 8 + clang/include/clang/Basic/AttrDocs.td | 12 + clang/include/clang/Basic/CodeGenOptions.def | 1 + clang/include/clang/Driver/CC1Options.td | 2 + clang/include/clang/Driver/Options.td | 2 + clang/include/clang/Tooling/CompilationDatabase.h | 6 + clang/lib/Basic/Targets/ARM.cpp | 13 + clang/lib/CodeGen/BackendUtil.cpp | 1 + clang/lib/CodeGen/CGDebugInfo.cpp | 5 +- clang/lib/CodeGen/CGExprCXX.cpp | 30 +- clang/lib/CodeGen/CGOpenMPRuntime.cpp | 122 +- clang/lib/CodeGen/CGStmtOpenMP.cpp | 3 +- clang/lib/CodeGen/CodeGenModule.cpp | 16 +- clang/lib/CodeGen/TargetInfo.cpp | 16 +- clang/lib/Driver/Driver.cpp | 12 +- clang/lib/Driver/ToolChains/Arch/X86.cpp | 1 + clang/lib/Driver/ToolChains/HIP.cpp | 5 +- clang/lib/Frontend/CompilerInvocation.cpp | 7 + clang/lib/Sema/SemaDeclAttr.cpp | 4 + clang/lib/Sema/TreeTransform.h | 12 +- clang/lib/Tooling/CMakeLists.txt | 1 + .../GuessTargetAndModeCompilationDatabase.cpp | 57 + clang/lib/Tooling/JSONCompilationDatabase.cpp | 6 +- clang/test/AST/ast-dump-hip-pinned-shadow.cu | 13 + .../exploded-graph-rewriter/environment.dot | 2 +- clang/test/CodeGen/arm-asm.c | 18 + clang/test/CodeGenCUDA/hip-pinned-shadow.cu | 23 + .../CodeGenCXX/dbg-info-all-calls-described.cpp | 13 + clang/test/CodeGenCXX/devirtualize-dtor-final.cpp | 23 - clang/test/Driver/clang-translation.c | 1 + clang/test/Driver/hip-toolchain-no-rdc.hip | 8 +- clang/test/Driver/hip-toolchain-rdc.hip | 4 +- clang/test/Driver/print-supported-cpus.c | 19 +- ...pragma-attribute-supported-attributes-list.test | 1 + clang/test/OpenMP/target_codegen.cpp | 106 +- clang/test/OpenMP/target_codegen_registration.cpp | 24 +- clang/test/OpenMP/target_data_codegen.cpp | 9 +- clang/test/OpenMP/target_depend_codegen.cpp | 10 +- clang/test/OpenMP/target_enter_data_codegen.cpp | 11 +- .../OpenMP/target_enter_data_depend_codegen.cpp | 180 +- clang/test/OpenMP/target_exit_data_codegen.cpp | 7 +- .../OpenMP/target_exit_data_depend_codegen.cpp | 180 +- clang/test/OpenMP/target_firstprivate_codegen.cpp | 7 +- clang/test/OpenMP/target_map_codegen.cpp | 572 +++--- clang/test/OpenMP/target_parallel_codegen.cpp | 94 +- .../target_parallel_codegen_registration.cpp | 24 +- .../test/OpenMP/target_parallel_depend_codegen.cpp | 10 +- clang/test/OpenMP/target_parallel_for_codegen.cpp | 98 +- .../target_parallel_for_codegen_registration.cpp | 24 +- .../OpenMP/target_parallel_for_depend_codegen.cpp | 10 +- .../OpenMP/target_parallel_for_simd_codegen.cpp | 98 +- ...rget_parallel_for_simd_codegen_registration.cpp | 24 +- .../target_parallel_for_simd_depend_codegen.cpp | 10 +- clang/test/OpenMP/target_simd_codegen.cpp | 98 +- .../OpenMP/target_simd_codegen_registration.cpp | 24 +- clang/test/OpenMP/target_simd_depend_codegen.cpp | 10 +- clang/test/OpenMP/target_teams_codegen.cpp | 98 +- .../OpenMP/target_teams_codegen_registration.cpp | 24 +- clang/test/OpenMP/target_teams_depend_codegen.cpp | 10 +- .../OpenMP/target_teams_distribute_codegen.cpp | 104 +- ...arget_teams_distribute_codegen_registration.cpp | 24 +- .../target_teams_distribute_depend_codegen.cpp | 10 +- ...eams_distribute_parallel_for_depend_codegen.cpp | 10 +- ...bute_parallel_for_simd_codegen_registration.cpp | 24 +- ...distribute_parallel_for_simd_depend_codegen.cpp | 10 +- .../target_teams_distribute_simd_codegen.cpp | 100 +- ..._teams_distribute_simd_codegen_registration.cpp | 24 +- ...target_teams_distribute_simd_depend_codegen.cpp | 10 +- clang/test/OpenMP/target_update_codegen.cpp | 8 +- clang/test/OpenMP/target_update_depend_codegen.cpp | 180 +- clang/test/SemaCUDA/hip-pinned-shadow.cu | 25 + clang/test/SemaTemplate/lambda-capture-pack.cpp | 10 +- .../unittests/Tooling/CompilationDatabaseTest.cpp | 36 +- clang/utils/analyzer/exploded-graph-rewriter.py | 3 +- .../lib/gwp_asan/guarded_pool_allocator.cpp | 33 +- compiler-rt/lib/gwp_asan/guarded_pool_allocator.h | 33 +- compiler-rt/lib/scudo/scudo_tsd_shared.cpp | 4 +- compiler-rt/lib/scudo/standalone/tsd_shared.h | 4 +- compiler-rt/test/asan/lit.cfg | 2 +- compiler-rt/test/ubsan/lit.common.cfg | 4 + debuginfo-tests/lit.cfg.py | 2 +- lld/ELF/DWARF.cpp | 28 +- lld/test/ELF/gdb-index-ranges-discarded.s | 51 + lld/test/ELF/undef-broken-debug.test | 8 +- lld/test/wasm/archive-no-index.ll | 13 + lld/test/wasm/corrupted.wasm.test | Bin 0 -> 251 bytes lld/test/wasm/emit-relocs-fpic.s | 20 + lld/test/wasm/lit.local.cfg | 2 +- lld/wasm/Driver.cpp | 16 +- lld/wasm/InputChunks.cpp | 9 +- lld/wasm/InputFiles.cpp | 4 +- .../lldb/Host/common/NativeProcessProtocol.h | 25 - lldb/packages/Python/lldbsuite/test/lldbtest.py | 10 +- lldb/source/Host/common/NativeProcessProtocol.cpp | 54 - lldb/source/Interpreter/CommandInterpreter.cpp | 2 +- lldb/source/Interpreter/Options.cpp | 8 +- lldb/source/Interpreter/embedded_interpreter.py | 1 + .../Plugins/Process/Linux/NativeProcessLinux.cpp | 2 +- .../Plugins/Process/POSIX/NativeProcessELF.cpp | 11 +- lldb/source/Target/CPPLanguageRuntime.cpp | 2 +- lldb/tools/debugserver/source/CMakeLists.txt | 15 + lldb/unittests/Host/NativeProcessProtocolTest.cpp | 51 - llvm/docs/AMDGPUUsage.rst | 27 +- llvm/docs/AddingConstrainedIntrinsics.rst | 8 + llvm/docs/CommandGuide/llvm-cxxfilt.md | 10 - llvm/docs/CommandGuide/llvm-cxxfilt.rst | 79 + llvm/docs/CommandGuide/llvm-readobj.rst | 259 ++- llvm/docs/LangRef.rst | 2 + llvm/include/llvm/Analysis/LoopInfo.h | 34 + llvm/include/llvm/Analysis/LoopInfoImpl.h | 13 +- llvm/include/llvm/Analysis/TargetTransformInfo.h | 3 +- llvm/include/llvm/BinaryFormat/Dwarf.def | 6 + llvm/include/llvm/BinaryFormat/ELF.h | 5 + llvm/include/llvm/BinaryFormat/Wasm.h | 1 + llvm/include/llvm/CodeGen/CommandFlags.inc | 6 + llvm/include/llvm/CodeGen/MachineRegisterInfo.h | 7 +- llvm/include/llvm/IR/IntrinsicsAMDGPU.td | 2 +- llvm/include/llvm/MC/MCSymbol.h | 26 +- llvm/include/llvm/Support/MemAlloc.h | 24 +- llvm/include/llvm/Target/TargetOptions.h | 6 +- llvm/lib/Analysis/TargetTransformInfo.cpp | 10 +- llvm/lib/BinaryFormat/Wasm.cpp | 14 + llvm/lib/CodeGen/HardwareLoops.cpp | 10 +- llvm/lib/CodeGen/MachinePipeliner.cpp | 10 +- llvm/lib/CodeGen/MachineRegisterInfo.cpp | 7 + llvm/lib/CodeGen/PeepholeOptimizer.cpp | 6 +- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 34 +- .../lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 26 + llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 70 +- llvm/lib/IR/Verifier.cpp | 2 +- llvm/lib/MC/ELFObjectWriter.cpp | 10 +- llvm/lib/MC/WasmObjectWriter.cpp | 14 +- llvm/lib/MC/WinCOFFObjectWriter.cpp | 2 +- llvm/lib/ObjectYAML/ELFYAML.cpp | 1 + llvm/lib/Target/AArch64/AArch64FrameLowering.cpp | 3 +- llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp | 32 +- llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 10 + llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h | 1 + .../Target/AMDGPU/AMDGPUInstructionSelector.cpp | 137 +- llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h | 1 + llvm/lib/Target/AMDGPU/AMDGPURegisterBanks.td | 2 +- .../AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp | 11 +- .../Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 58 + .../AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp | 27 + .../AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h | 7 + llvm/lib/Target/AMDGPU/SIFoldOperands.cpp | 22 +- llvm/lib/Target/AMDGPU/SIFrameLowering.cpp | 3 +- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 26 +- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 8 +- llvm/lib/Target/AMDGPU/SIInstrInfo.td | 4 + llvm/lib/Target/AMDGPU/SIInstructions.td | 10 + llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp | 17 - llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h | 3 - llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp | 4 + llvm/lib/Target/ARM/ARM.h | 3 +- llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 121 +- llvm/lib/Target/ARM/ARMBaseInstrInfo.h | 7 + llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp | 62 + llvm/lib/Target/ARM/ARMISelLowering.cpp | 139 +- llvm/lib/Target/ARM/ARMISelLowering.h | 1 + llvm/lib/Target/ARM/ARMInstrFormats.td | 2 + llvm/lib/Target/ARM/ARMInstrInfo.td | 9 + llvm/lib/Target/ARM/ARMInstrMVE.td | 700 +++++++ llvm/lib/Target/ARM/ARMInstrThumb2.td | 60 +- llvm/lib/Target/ARM/ARMInstrVFP.td | 8 +- llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp | 296 +++ llvm/lib/Target/ARM/ARMRegisterInfo.td | 7 +- llvm/lib/Target/ARM/ARMTargetMachine.cpp | 5 + llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 328 +++- llvm/lib/Target/ARM/CMakeLists.txt | 1 + .../Target/ARM/Disassembler/ARMDisassembler.cpp | 180 +- .../Target/ARM/MCTargetDesc/ARMAddressingModes.h | 4 +- llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h | 4 + .../lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp | 34 + llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h | 5 + .../Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp | 88 +- llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp | 16 +- llvm/lib/Target/ARM/Thumb2InstrInfo.cpp | 14 +- llvm/lib/Target/AVR/AVRFrameLowering.cpp | 3 +- llvm/lib/Target/AVR/AVRRegisterInfo.cpp | 2 +- llvm/lib/Target/AVR/AVRRegisterInfo.h | 2 +- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp | 45 +- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 9 +- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 2 + llvm/lib/Target/PowerPC/PPCInstrVSX.td | 4 + llvm/lib/Target/PowerPC/PPCMCInstLower.cpp | 10 +- llvm/lib/Target/PowerPC/PPCMIPeephole.cpp | 105 +- .../WebAssembly/AsmParser/WebAssemblyAsmParser.cpp | 4 - llvm/lib/Target/X86/X86FrameLowering.cpp | 3 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 28 +- llvm/lib/Target/X86/X86InstrAVX512.td | 46 - llvm/lib/Target/X86/X86InstrFragmentsSIMD.td | 7 - llvm/lib/Target/X86/X86InstrSSE.td | 70 - llvm/lib/Target/X86/X86TargetTransformInfo.cpp | 5 +- .../Transforms/InstCombine/InstCombineCompares.cpp | 43 +- llvm/lib/Transforms/Scalar/IndVarSimplify.cpp | 15 +- llvm/lib/Transforms/Utils/CloneFunction.cpp | 41 +- llvm/lib/Transforms/Utils/LoopUnroll.cpp | 230 ++- .../ScalarEvolution/scev-expander-reuse-unroll.ll | 6 +- llvm/test/CodeGen/AArch64/arm64-popcnt.ll | 34 + .../CodeGen/AMDGPU/32-bit-local-address-space.ll | 4 +- .../AMDGPU/GlobalISel/inst-select-anyext.mir | 171 ++ .../AMDGPU/GlobalISel/inst-select-implicit-def.mir | 6 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir | 187 ++ .../CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir | 187 ++ llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll | 3 +- llvm/test/CodeGen/AMDGPU/ds_read2.ll | 28 +- llvm/test/CodeGen/AMDGPU/ds_write2.ll | 54 +- llvm/test/CodeGen/AMDGPU/inst-select-load-flat.mir | 28 - llvm/test/CodeGen/AMDGPU/inst-select-load-smrd.mir | 159 -- llvm/test/CodeGen/AMDGPU/lds-initializer.ll | 2 +- llvm/test/CodeGen/AMDGPU/lds-relocs.ll | 63 + llvm/test/CodeGen/AMDGPU/lds-size.ll | 1 - llvm/test/CodeGen/AMDGPU/lds-zero-initializer.ll | 2 +- llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.dec.ll | 12 +- llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.inc.ll | 10 +- .../CodeGen/AMDGPU/llvm.amdgcn.groupstaticsize.ll | 15 +- llvm/test/CodeGen/AMDGPU/local-memory.amdgcn.ll | 7 +- llvm/test/CodeGen/AMDGPU/local-memory.ll | 4 +- llvm/test/CodeGen/AMDGPU/merge-store-crash.ll | 3 +- llvm/test/CodeGen/AMDGPU/over-max-lds-size.ll | 14 - llvm/test/CodeGen/AMDGPU/promote-alloca-globals.ll | 3 +- llvm/test/CodeGen/AMDGPU/shl_add_ptr.ll | 18 +- llvm/test/CodeGen/AMDGPU/si-sgpr-spill.ll | 22 +- llvm/test/CodeGen/AMDGPU/target-cpu.ll | 1 - llvm/test/CodeGen/AMDGPU/update-phi.ll | 39 + llvm/test/CodeGen/ARM/O3-pipeline.ll | 7 + llvm/test/CodeGen/ARM/fast-isel-call.ll | 6 +- llvm/test/CodeGen/ARM/fp16-promote.ll | 2 +- llvm/test/CodeGen/ARM/half.ll | 4 + llvm/test/CodeGen/ARM/inlineasm.ll | 24 + llvm/test/CodeGen/ARM/mve-vpt-block2.mir | 77 + llvm/test/CodeGen/ARM/mve-vpt-block3.mir | 82 + llvm/test/CodeGen/ARM/mve-vpt-block4.mir | 90 + llvm/test/CodeGen/ARM/mve-vpt-block5.mir | 88 + llvm/test/CodeGen/ARM/mve-vpt-block6.mir | 84 + llvm/test/CodeGen/ARM/no-fpu.ll | 4 +- .../CodeGen/MIR/AMDGPU/machine-function-info.ll | 2 +- llvm/test/CodeGen/PowerPC/bool-math.ll | 4 +- llvm/test/CodeGen/PowerPC/combine-fneg.ll | 32 + llvm/test/CodeGen/PowerPC/ppc32-pic.ll | 28 +- llvm/test/CodeGen/PowerPC/ppc32-secure-plt-tls2.ll | 18 + llvm/test/CodeGen/PowerPC/select_const.ll | 269 +-- llvm/test/CodeGen/PowerPC/sms-iterator.ll | 36 + llvm/test/CodeGen/PowerPC/tocSaveInPrologue.ll | 68 + llvm/test/CodeGen/PowerPC/vec-select.ll | 72 + llvm/test/CodeGen/PowerPC/vector-copysign.ll | 27 + .../Thumb2/inlineasm-error-t-toofewregs-mve.ll | 14 + llvm/test/CodeGen/Thumb2/inlineasm-mve.ll | 48 + llvm/test/CodeGen/Thumb2/mve-basic.ll | 31 + llvm/test/CodeGen/Thumb2/mve-bitcasts.ll | 449 +++++ llvm/test/CodeGen/X86/addr-mode-matcher-2.ll | 3 +- llvm/test/CodeGen/X86/avx512-ext.ll | 84 +- llvm/test/CodeGen/X86/avx512-fma.ll | 6 +- llvm/test/CodeGen/X86/avx512-insert-extract.ll | 80 +- llvm/test/CodeGen/X86/avx512-mask-op.ll | 64 +- llvm/test/CodeGen/X86/avx512-masked-memop-64-32.ll | 14 +- llvm/test/CodeGen/X86/avx512-vec-cmp.ll | 3 +- llvm/test/CodeGen/X86/bitcast-setcc-512.ll | 3 - llvm/test/CodeGen/X86/bitcast-vector-bool.ll | 3 - llvm/test/CodeGen/X86/cmov-promotion.ll | 71 +- llvm/test/CodeGen/X86/combine-pmuldq.ll | 17 +- llvm/test/CodeGen/X86/ctpop-combine.ll | 25 + llvm/test/CodeGen/X86/masked_compressstore.ll | 16 +- llvm/test/CodeGen/X86/masked_expandload.ll | 4 +- llvm/test/CodeGen/X86/masked_gather_scatter.ll | 64 +- llvm/test/CodeGen/X86/masked_load.ll | 12 +- llvm/test/CodeGen/X86/memcmp.ll | 71 + llvm/test/CodeGen/X86/movmsk-cmp.ll | 18 - llvm/test/CodeGen/X86/or-branch.ll | 3 +- llvm/test/CodeGen/X86/peephole-fold-testrr.mir | 88 + llvm/test/CodeGen/X86/pmul.ll | 101 +- llvm/test/CodeGen/X86/pr30284.ll | 2 +- .../test/CodeGen/X86/prefer-avx256-mask-shuffle.ll | 8 +- llvm/test/CodeGen/X86/select.ll | 12 +- llvm/test/CodeGen/X86/setcc-lowering.ll | 2 +- llvm/test/CodeGen/X86/sibcall.ll | 6 +- llvm/test/CodeGen/X86/vector-reduce-and-bool.ll | 10 +- llvm/test/CodeGen/X86/vector-reduce-or-bool.ll | 10 +- llvm/test/CodeGen/X86/vector-reduce-xor-bool.ll | 10 +- llvm/test/CodeGen/X86/vector-shuffle-512-v16.ll | 4 +- llvm/test/CodeGen/X86/vector-shuffle-512-v8.ll | 12 +- llvm/test/CodeGen/X86/vector-shuffle-v1.ll | 12 +- llvm/test/CodeGen/X86/vector-zmov.ll | 36 +- llvm/test/CodeGen/X86/vselect.ll | 26 +- llvm/test/CodeGen/X86/x86-shrink-wrapping.ll | 6 +- llvm/test/MC/AMDGPU/elf-lds-error.s | 19 + llvm/test/MC/AMDGPU/elf-lds.s | 82 + llvm/test/MC/ARM/fp-armv8-m.s | 140 ++ llvm/test/MC/ARM/fullfp16.s | 2 + llvm/test/MC/ARM/mve-fp-registers.s | 25 +- llvm/test/MC/ARM/mve-load-store.s | 1944 ++++++++++++++++++++ llvm/test/MC/ARM/mve-misc.s | 176 ++ llvm/test/MC/ARM/no-mve.s | 16 + llvm/test/MC/ARM/ras-extension.s | 3 + llvm/test/MC/COFF/alias.s | 2 +- llvm/test/MC/COFF/weak-alias-local.s | 2 +- llvm/test/MC/COFF/weak-val.s | 2 +- llvm/test/MC/COFF/weak.s | 4 +- llvm/test/MC/Disassembler/ARM/mve-load-store.txt | 1378 ++++++++++++++ llvm/test/MC/Disassembler/ARM/mve-misc.txt | 111 ++ .../MC/Disassembler/ARM/ras-extension-thumb.txt | 3 + llvm/test/Object/X86/nm-coff.s | 11 +- llvm/test/TableGen/intrinsic-pointer-to-any.td | 53 + llvm/test/Transforms/HardwareLoops/ARM/calls.ll | 28 +- .../test/Transforms/HardwareLoops/ARM/cond-mov.mir | 115 ++ llvm/test/Transforms/HardwareLoops/ARM/massive.mir | 145 ++ .../HardwareLoops/ARM/multiblock-massive.mir | 160 ++ .../HardwareLoops/ARM/revert-after-call.mir | 130 ++ .../HardwareLoops/ARM/revert-after-spill.mir | 130 ++ .../test/Transforms/HardwareLoops/ARM/simple-do.ll | 37 + .../Transforms/HardwareLoops/ARM/size-limit.mir | 155 ++ .../test/Transforms/HardwareLoops/ARM/structure.ll | 177 ++ llvm/test/Transforms/HardwareLoops/ARM/switch.mir | 198 ++ llvm/test/Transforms/InstCombine/ispow2.ll | 75 +- llvm/test/Transforms/InstCombine/pr17827.ll | 8 +- .../InstCombine/shift-amount-reassociation.ll | 167 ++ .../InstCombine/shl-unsigned-cmp-const.ll | 44 +- .../partially-unroll-unconditional-latch.ll | 65 + llvm/test/Transforms/LoopUnroll/runtime-li.ll | 7 +- llvm/test/Transforms/LoopUnroll/unloop.ll | 2 +- .../LoopUnroll/unroll-unconditional-latch.ll | 277 +++ .../test/Transforms/SLPVectorizer/X86/supernode.ll | 327 ++++ llvm/test/tools/llvm-symbolizer/frame.s | 20 +- llvm/tools/llvm-objcopy/CopyConfig.cpp | 67 +- llvm/tools/llvm-objcopy/CopyConfig.h | 11 +- llvm/tools/llvm-objcopy/ELF/ELFObjcopy.cpp | 14 +- llvm/tools/llvm-objcopy/ELF/Object.cpp | 27 +- llvm/tools/llvm-objcopy/ELF/Object.h | 1 + llvm/tools/llvm-objcopy/ObjcopyOpts.td | 2 +- llvm/tools/llvm-objcopy/StripOpts.td | 2 +- llvm/tools/llvm-objcopy/llvm-objcopy.cpp | 32 +- llvm/tools/llvm-shlib/CMakeLists.txt | 2 +- llvm/utils/TableGen/IntrinsicEmitter.cpp | 3 + .../gn/secondary/llvm/lib/Target/ARM/BUILD.gn | 1 + 354 files changed, 14520 insertions(+), 3123 deletions(-) create mode 100644 .github/lockdown.yml create mode 100644 clang-tools-extra/clangd/QueryDriverDatabase.cpp create mode 100644 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