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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-next-allmodconfig in repository toolchain/ci/llvm-project.
from 706b48251f6 [InstCombine] canonicalize fcmp+select to minnum/maxnum intrinsics adds 135cf982e8e Revert "[GDBRemote] Remove code that flushes GDB remote packets" adds bb0b44deaab Clean up MSVC visualization of LLVM pointer types adds fb133b0aabe Various tweaks to MSVC natvis visualizers adds d1728f89878 [X86] Add MOVHPDrm/MOVLPDrm patterns that use VZEXT_LOAD. adds fc233c9108d [X86] Add some additional load folding tests to vec_int_to_ [...] adds 4ca81a9b994 [X86] Add a DAG combine to replace vector loads feeding a v [...] adds 29fff0797b2 [X86] Improve the type checking fast-isel handling of vecto [...] adds fcda45a9eb8 [X86] Add more load folding tests for vcvt(t)ps2(u)qq showi [...] adds b739b91cd3a [clangd] Make FixIt message be consistent with the clang-ti [...] adds 0384a780549 [libcxx] [test] Add void cast to result of compare_exchange [...] adds 98722691b0b [ARM] WLS/LE Code Generation adds d4097b4a93a [SimpleLoopUnswitch] Implement handling of prof branch_weig [...] adds 9d34f4569b4 [clangd] Show better message when we rename macros. adds d2b6665e339 [DebugInfo] Avoid adding too much indirection to pointer-va [...] adds 0f82f64c832 [NFC][InstCombine] Copy test for omit urem when possible fr [...] adds f55818e3a72 [InstCombine] Omit 'urem' where possible adds 4f878fe3a7d [NFC][InstCombine] Tests for x - ~(y) -> x + y + 1 fold ( [...] adds 9cca81344c8 [clangd] Make PreambleStatusCache handle filenames more carefully adds 60300c9c7d6 [clangd] Fix unused var from r364735 adds d74f2d0a860 [benchmark] Disable CMake get_git_version adds ed13fef4774 [SelectionDAG] Do minnum->minimum at legalization time inst [...] adds 0f73709cb71 Remove null checks of results of new expressions adds 172fe5dd191 [X86] CombineShuffleWithExtract - updated description comme [...] adds 92e78b7bedb [RISCV] Add break; to the last switch case adds 881aab4dc3d [clangd] No longer getting template instantiations from hea [...] adds 4f0a3772805 Fix TestGdbRemoteLibrariesSvr4Support adds d5c3e34cb7e [NFC][InstCombine] Tests for ((~x) + y) + 1 -> y - x fold [...] adds 33c8c0ea275 [AMDGPU] Call isLoopExiting for blocks in the loop. adds 08c38f77c5f Revert "Implement xfer:libraries-svr4:read packet" adds 17c3eafb2e3 [ASTImporter] Propagate error from ImportDeclContext adds 77c04c3a577 @skipIfXmlSupportMissing TestRecognizeBreakpoint adds c12dfcf1f56 Don't check the validity of newly contructed data buffers adds 3a10810b7ab [mips] Add missing schedinfo for ADJCALLSTACKDOWN, ADJCALLSTACKUP adds c0121bf8741 [mips] Add missing schedinfo for atomic instructions adds ceb9da5bc79 [mips] Add missing schedinfo for MSA and ASE instructions adds fbf67d88de2 GlobalISel: Add DAG compat for G_FCANONICALIZE adds 01bb075c1f9 GlobalISel: Add GINodeEquiv for min/max adds 5dafcb9b118 AMDGPU/GlobalISel: Use and instead of BFE with inline immediate adds 9f992c238ab AMDGPU/GlobalISel: Fix scc->vcc copy handling adds facf69e8449 AMDGPU/GlobalISel: Use vcc reg bank for amdgcn.wqm.vote adds c23149f612d AMDGPU/GlobalISel: RegBankSelect for WWM/WQM adds 9f3645869cf [NFC][InstCombine] Improve test coverage for ((~x) + y) + [...] adds 3b7668ae4bb AMDGPU/GlobalISel: Improve icmp selection coverage. adds 89fc8bcdd6d AMDGPU/GlobalISel: Fail on store to 32-bit address space adds b5fc94f3e74 AMDGPU/GlobalISel: Fix RegBankSelect for G_BUILD_VECTOR adds 5bf850d52e0 AMDGPU/GlobalISel: Fix RegBankSelect for G_FCANONICALIZE adds 1b317685e9b AMDGPU: Convert some places to Register adds 511ad50db41 [Hexagon] Rework VLCR algorithm adds 1ad4b99d948 [ASTImporter] Mark erroneous nodes in from ctx adds 34a0b16e290 [NFC][InstCombine] Better commutative tests for "shift amou [...] adds 3f594ed1686 Fix lookup of symbols at the same address with no size vs. size adds 4f769361e35 [ASTImporter] Silence unused variable warning in Release bu [...] adds ee6539341bf [UpdateTestChecks][PowerPC] Avoid empty string when scrubbi [...] adds 535f39ce521 Revert "[lldb] [Process/NetBSD] Fix constructor after r363707" adds 28145735f7b [RISCV] Avoid save-restore target feature warning adds 2ba16011c13 Fixup r364512 adds 2b2ad9342e6 [lldb] [Process/NetBSD] Support reading YMM registers via P [...] adds baf64b65056 [lldb] [Process/NetBSD] Fix segfault when handling watchpoint adds 0856721e3a0 [lldb] [Process/NetBSD] Use global enable bits for watchpoints adds 4f64ade04cb AMDGPU/GlobalISel: Select src modifiers adds fb99fc7a689 AMDGPU: Fix tests using the default alloca address space adds 1daad91af69 AMDGPU/GlobalISel: Tolerate copies with no type set adds 2afbfb6b226 [ASTImporter] Mark erroneous nodes in shared st adds 6464280eb04 AMDGPU/GlobalISel: Select G_BRCOND for scc conditions adds fdf36729c71 AMDGPU/GlobalISel: Make s16 select legal adds 7cfd99ab15d AMDGPU/GFX10: fix scratch resource descriptor adds cda82f0bb6f AMDGPU/GlobalISel: Select G_FRAME_INDEX adds 5abf80cdfa3 [Hexagon] Custom-lower UADDO(x, 1) and USUBO(x, 1) adds 72b8d41ce81 [InstCombine] Shift amount reassociation in bittest (PR42399) adds 04d3d3bbff5 [InstCombine] (Y + ~X) + 1 --> Y - X fold (PR42459) adds 657f8c16c19 Update email address in CODE_OWNERS adds 4a9e3f15bbb [ARM] MVE: support QQPRRegClass and QQQQPRRegClass adds 2ab25f9ceb1 AMDGPU/GlobalISel: Select G_BRCOND for vcc adds 8b2e304bc57 [ARM] Fix MVE_VQxDMLxDH instruction class adds 9e9dd30de3a AMDGPU/GlobalISel: Implement select for 32-bit G_ADD
No new revisions were added by this update.
Summary of changes: clang-tools-extra/clangd/ClangdUnit.cpp | 3 +- clang-tools-extra/clangd/Diagnostics.cpp | 2 + clang-tools-extra/clangd/FS.cpp | 19 +- clang-tools-extra/clangd/SourceCode.cpp | 27 + clang-tools-extra/clangd/SourceCode.h | 8 + clang-tools-extra/clangd/XRefs.cpp | 76 +- clang-tools-extra/clangd/refactor/Rename.cpp | 43 +- .../clangd/unittests/ClangdUnitTests.cpp | 20 + .../clangd/unittests/DiagnosticsTests.cpp | 22 +- clang-tools-extra/clangd/unittests/FSTests.cpp | 12 +- clang-tools-extra/clangd/unittests/RenameTests.cpp | 7 + .../clangd/unittests/SourceCodeTests.cpp | 17 + clang/include/clang/AST/ASTImporter.h | 144 +++- clang/include/clang/AST/ASTImporterSharedState.h | 80 +++ clang/include/clang/CrossTU/CrossTranslationUnit.h | 6 +- clang/lib/AST/ASTImporter.cpp | 112 ++- clang/lib/CrossTU/CrossTranslationUnit.cpp | 10 +- clang/lib/Driver/ToolChains/Arch/RISCV.cpp | 8 +- clang/lib/Frontend/ASTMerge.cpp | 6 +- clang/test/Driver/riscv-features.c | 8 +- clang/unittests/AST/ASTImporterFixtures.cpp | 45 +- clang/unittests/AST/ASTImporterFixtures.h | 28 +- clang/unittests/AST/ASTImporterTest.cpp | 367 +++++++++- clang/utils/ClangVisualizers/clang.natvis | 54 +- .../atomics.general/replace_failure_order.pass.cpp | 8 +- .../lldb/Host/common/NativeProcessProtocol.h | 14 - lldb/lit/SymbolFile/Inputs/sizeless-symbol.s | 8 + lldb/lit/SymbolFile/sizeless-symbol.test | 14 + .../gdb_remote_client/TestRecognizeBreakpoint.py | 1 + .../hello_watchlocation/TestWatchLocation.py | 1 - .../hello_watchpoint/TestMyFirstWatchpoint.py | 1 - .../watchpoint/multiple_hits/TestMultipleHits.py | 1 - .../TestWatchpointMultipleThreads.py | 2 - .../step_over_watchpoint/TestStepOverWatchpoint.py | 1 - .../watchpoint_commands/TestWatchpointCommands.py | 4 - .../command/TestWatchpointCommandLLDB.py | 2 - .../command/TestWatchpointCommandPython.py | 2 - .../condition/TestWatchpointConditionCmd.py | 1 - .../watchpoint_disable/TestWatchpointDisable.py | 1 - .../TestWatchLocationWithWatchSet.py | 1 - .../watchpoint_size/TestWatchpointSizes.py | 3 - .../test/tools/lldb-server/gdbremote_testcase.py | 29 +- .../test/tools/lldb-server/libraries-svr4/Makefile | 17 - .../TestGdbRemoteLibrariesSvr4Support.py | 130 ---- .../test/tools/lldb-server/libraries-svr4/main.cpp | 15 - .../tools/lldb-server/libraries-svr4/svr4lib_a.cpp | 9 - .../tools/lldb-server/libraries-svr4/svr4lib_a.mk | 9 - .../lldb-server/libraries-svr4/svr4lib_b_quote.cpp | 9 - .../lldb-server/libraries-svr4/svr4lib_b_quote.mk | 9 - .../Plugins/ObjectFile/JIT/ObjectFileJIT.cpp | 14 +- .../RegisterContextPOSIXProcessMonitor_arm.cpp | 2 +- .../RegisterContextPOSIXProcessMonitor_arm64.cpp | 2 +- .../RegisterContextPOSIXProcessMonitor_mips64.cpp | 2 +- .../RegisterContextPOSIXProcessMonitor_powerpc.cpp | 2 +- .../RegisterContextPOSIXProcessMonitor_x86.cpp | 2 +- .../Plugins/Process/Linux/NativeProcessLinux.cpp | 2 +- .../Linux/NativeRegisterContextLinux_arm.cpp | 11 - .../Linux/NativeRegisterContextLinux_arm64.cpp | 11 - .../Linux/NativeRegisterContextLinux_mips64.cpp | 14 - .../Linux/NativeRegisterContextLinux_ppc64le.cpp | 11 - .../Linux/NativeRegisterContextLinux_s390x.cpp | 14 - .../Plugins/Process/NetBSD/NativeProcessNetBSD.cpp | 33 +- .../Plugins/Process/NetBSD/NativeProcessNetBSD.h | 4 +- .../NetBSD/NativeRegisterContextNetBSD_x86_64.cpp | 107 ++- .../NetBSD/NativeRegisterContextNetBSD_x86_64.h | 10 +- .../Plugins/Process/POSIX/NativeProcessELF.cpp | 69 -- .../Plugins/Process/POSIX/NativeProcessELF.h | 7 - .../Utility/RegisterContextDarwin_arm64.cpp | 4 +- .../Process/Utility/RegisterContextDarwin_i386.cpp | 3 +- .../Utility/RegisterContextDarwin_x86_64.cpp | 3 +- .../gdb-remote/GDBRemoteCommunicationClient.cpp | 7 + .../GDBRemoteCommunicationServerCommon.cpp | 1 - .../GDBRemoteCommunicationServerLLGS.cpp | 43 -- .../gdb-remote/GDBRemoteCommunicationServerLLGS.h | 2 - lldb/source/Symbol/Symtab.cpp | 10 +- llvm/CODE_OWNERS.TXT | 2 +- llvm/include/llvm/IR/DebugInfoMetadata.h | 4 + .../llvm/Target/GlobalISel/SelectionDAGCompat.td | 5 + llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 22 +- llvm/lib/CodeGen/HardwareLoops.cpp | 1 + llvm/lib/CodeGen/PrologEpilogInserter.cpp | 13 +- .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 22 +- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 11 + llvm/lib/IR/DebugInfoMetadata.cpp | 21 + llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h | 15 +- llvm/lib/Target/AMDGPU/AMDGPUGISel.td | 3 + .../Target/AMDGPU/AMDGPUInstructionSelector.cpp | 260 +++++-- llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h | 10 + llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 4 +- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 8 +- .../Target/AMDGPU/AMDGPUTargetTransformInfo.cpp | 6 +- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 4 +- llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h | 4 +- llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 4 +- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp | 10 + llvm/lib/Target/ARM/ARMISelLowering.cpp | 47 +- llvm/lib/Target/ARM/ARMISelLowering.h | 2 + llvm/lib/Target/ARM/ARMInstrInfo.td | 8 + llvm/lib/Target/ARM/ARMInstrMVE.td | 15 +- llvm/lib/Target/ARM/ARMInstrThumb2.td | 10 +- llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp | 116 ++- llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp | 2 + llvm/lib/Target/Hexagon/HexagonISelLowering.cpp | 43 +- llvm/lib/Target/Hexagon/HexagonISelLowering.h | 1 + .../Hexagon/HexagonVectorLoopCarriedReuse.cpp | 220 ++++-- llvm/lib/Target/Mips/MipsDSPInstrInfo.td | 1 + llvm/lib/Target/Mips/MipsInstrInfo.td | 11 +- llvm/lib/Target/Mips/MipsMSAInstrInfo.td | 7 +- llvm/lib/Target/Mips/MipsScheduleP5600.td | 22 + llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 1 + llvm/lib/Target/X86/X86FastISel.cpp | 21 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 36 +- llvm/lib/Target/X86/X86InstrAVX512.td | 22 + llvm/lib/Target/X86/X86InstrSSE.td | 12 + .../Transforms/InstCombine/InstCombineAddSub.cpp | 5 +- .../Transforms/InstCombine/InstCombineCompares.cpp | 84 ++- llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp | 56 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-add.mir | 43 ++ .../AMDGPU/GlobalISel/inst-select-anyext.mir | 36 + .../CodeGen/AMDGPU/GlobalISel/inst-select-br.mir | 21 + .../AMDGPU/GlobalISel/inst-select-brcond.mir | 198 +++++ .../CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir | 170 ++++- .../GlobalISel/inst-select-fcanonicalize.mir | 164 +++++ .../CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir | 190 ++++- .../AMDGPU/GlobalISel/inst-select-frame-index.mir | 38 + .../AMDGPU/GlobalISel/inst-select-icmp.s64.mir | 595 +++++++++++++++ .../AMDGPU/GlobalISel/inst-select-implicit-def.mir | 6 +- .../AMDGPU/GlobalISel/inst-select-select.mir | 176 +++++ .../CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir | 39 + .../CodeGen/AMDGPU/GlobalISel/inst-select-smax.mir | 83 +++ .../CodeGen/AMDGPU/GlobalISel/inst-select-smin.mir | 83 +++ .../CodeGen/AMDGPU/GlobalISel/inst-select-umax.mir | 83 +++ .../CodeGen/AMDGPU/GlobalISel/inst-select-umin.mir | 83 +++ .../CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir | 48 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir | 8 +- .../CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir | 20 +- .../CodeGen/AMDGPU/GlobalISel/legalize-select.mir | 110 +-- .../AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir | 31 + ...-vote.mir => regbankselect-amdgcn.wqm.vote.mir} | 10 +- .../AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir | 31 + .../GlobalISel/regbankselect-build-vector.mir | 69 ++ .../GlobalISel/regbankselect-fcanonicalize.mir | 35 + llvm/test/CodeGen/AMDGPU/loop-idiom.ll | 13 +- llvm/test/CodeGen/AMDGPU/scratch-simple.ll | 65 +- llvm/test/CodeGen/AMDGPU/unroll.ll | 17 +- ...exagon_vector_loop_carried_reuse_commutative.ll | 82 +++ llvm/test/CodeGen/Hexagon/isel-uaddo-1.ll | 37 + llvm/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll | 178 +++-- .../Thumb2/LowOverheadLoops}/cond-mov.mir | 0 .../CodeGen/Thumb2/LowOverheadLoops/loop-guards.ll | 213 ++++++ .../Thumb2/LowOverheadLoops}/massive.mir | 0 .../LowOverheadLoops}/multiblock-massive.mir | 0 .../Thumb2/LowOverheadLoops}/revert-after-call.mir | 0 .../LowOverheadLoops}/revert-after-spill.mir | 0 .../Thumb2/LowOverheadLoops/revert-while.mir | 130 ++++ .../Thumb2/LowOverheadLoops}/size-limit.mir | 0 .../Thumb2/LowOverheadLoops}/switch.mir | 0 .../test/CodeGen/Thumb2/LowOverheadLoops/while.mir | 131 ++++ llvm/test/CodeGen/WebAssembly/f32.ll | 18 + llvm/test/CodeGen/WebAssembly/simd-arith.ll | 22 + llvm/test/CodeGen/X86/avx512dqvl-intrinsics.ll | 747 +++++++++++++++++++ .../CodeGen/X86/merge-consecutive-loads-128.ll | 3 +- llvm/test/CodeGen/X86/pr42452.ll | 37 + llvm/test/CodeGen/X86/vec_fp_to_int-widen.ll | 152 ++++ llvm/test/CodeGen/X86/vec_fp_to_int.ll | 152 ++++ llvm/test/CodeGen/X86/vec_int_to_fp-widen.ll | 794 +++++++++++++++++---- llvm/test/CodeGen/X86/vec_int_to_fp.ll | 472 ++++++++---- .../MIR/X86/prolog-epilog-indirection.mir | 130 ++++ llvm/test/Transforms/HardwareLoops/ARM/do-rem.ll | 32 +- .../Transforms/HardwareLoops/ARM/fp-emulation.ll | 23 +- .../test/Transforms/HardwareLoops/ARM/simple-do.ll | 42 +- .../test/Transforms/HardwareLoops/ARM/structure.ll | 95 ++- llvm/test/Transforms/InstCombine/add.ll | 10 +- ...ld-inc-of-add-of-not-x-and-y-to-sub-x-from-y.ll | 213 ++++++ .../InstCombine/fold-sub-of-not-to-inc-of-add.ll | 94 +++ ...ower-of-two-or-zero-when-comparing-with-zero.ll | 166 +++++ .../shift-amount-reassociation-in-bittest.ll | 318 ++++++--- .../SimpleLoopUnswitch/basictest-profmd.ll | 34 + .../SimpleLoopUnswitch/trivial-unswitch-profmd.ll | 228 ++++++ llvm/utils/LLVMVisualizers/llvm.natvis | 19 +- llvm/utils/UpdateTestChecks/asm.py | 4 +- llvm/utils/benchmark/CMakeLists.txt | 7 +- llvm/utils/benchmark/README.LLVM | 2 + 183 files changed, 8380 insertions(+), 1647 deletions(-) create mode 100644 clang/include/clang/AST/ASTImporterSharedState.h create mode 100644 lldb/lit/SymbolFile/Inputs/sizeless-symbol.s create mode 100644 lldb/lit/SymbolFile/sizeless-symbol.test delete mode 100644 lldb/packages/Python/lldbsuite/test/tools/lldb-server/libraries [...] delete mode 100644 lldb/packages/Python/lldbsuite/test/tools/lldb-server/libraries [...] delete mode 100644 lldb/packages/Python/lldbsuite/test/tools/lldb-server/libraries [...] delete mode 100644 lldb/packages/Python/lldbsuite/test/tools/lldb-server/libraries [...] delete mode 100644 lldb/packages/Python/lldbsuite/test/tools/lldb-server/libraries [...] delete mode 100644 lldb/packages/Python/lldbsuite/test/tools/lldb-server/libraries [...] delete mode 100644 lldb/packages/Python/lldbsuite/test/tools/lldb-server/libraries [...] create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-br.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcanonicalize.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-frame-index.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s64.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-select.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smax.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smin.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umax.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umin.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir rename llvm/test/CodeGen/AMDGPU/GlobalISel/{regbankselect-amdgcn-wqm-vote.mir => r [...] create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcanonicalize.mir create mode 100644 llvm/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse_com [...] create mode 100644 llvm/test/CodeGen/Hexagon/isel-uaddo-1.ll rename llvm/test/{Transforms/HardwareLoops/ARM => CodeGen/Thumb2/LowOverheadLoops} [...] create mode 100644 llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-guards.ll rename llvm/test/{Transforms/HardwareLoops/ARM => CodeGen/Thumb2/LowOverheadLoops} [...] rename llvm/test/{Transforms/HardwareLoops/ARM => CodeGen/Thumb2/LowOverheadLoops} [...] rename llvm/test/{Transforms/HardwareLoops/ARM => CodeGen/Thumb2/LowOverheadLoops} [...] rename llvm/test/{Transforms/HardwareLoops/ARM => CodeGen/Thumb2/LowOverheadLoops} [...] create mode 100644 llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir rename llvm/test/{Transforms/HardwareLoops/ARM => CodeGen/Thumb2/LowOverheadLoops} [...] rename llvm/test/{Transforms/HardwareLoops/ARM => CodeGen/Thumb2/LowOverheadLoops} [...] create mode 100644 llvm/test/CodeGen/Thumb2/LowOverheadLoops/while.mir create mode 100644 llvm/test/CodeGen/X86/pr42452.ll create mode 100644 llvm/test/DebugInfo/MIR/X86/prolog-epilog-indirection.mir create mode 100644 llvm/test/Transforms/InstCombine/fold-inc-of-add-of-not-x-and-y [...] create mode 100644 llvm/test/Transforms/InstCombine/fold-sub-of-not-to-inc-of-add.ll create mode 100644 llvm/test/Transforms/InstCombine/omit-urem-of-power-of-two-or-z [...] create mode 100644 llvm/test/Transforms/SimpleLoopUnswitch/basictest-profmd.ll create mode 100644 llvm/test/Transforms/SimpleLoopUnswitch/trivial-unswitch-profmd.ll