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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-defconfig in repository toolchain/ci/llvm-monorepo.
from fa2588a7788 [X86] Use GetDemandedBits to simplify the operands of PMULD [...] adds bf4e9868875 [gn build] Make NOSORT line actually work adds 9181cfa61f7 [PowerPC] Fix the bug of ISD::ADDE to set its second return [...] adds b78f9a06fdd [NFC] Reuse variables instead of re-calling getParent adds 62368bc223e [MIPS GlobalISel] Select G_SELECT
No new revisions were added by this update.
Summary of changes: llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 19 ++- llvm/lib/Target/Mips/MipsInstructionSelector.cpp | 9 ++ llvm/lib/Target/Mips/MipsLegalizerInfo.cpp | 5 + llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp | 7 + llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 2 +- llvm/lib/Transforms/Scalar/GuardWidening.cpp | 3 +- .../Mips/GlobalISel/instruction-select/select.mir | 72 +++++++++ .../CodeGen/Mips/GlobalISel/legalizer/select.mir | 172 +++++++++++++++++++++ .../test/CodeGen/Mips/GlobalISel/llvm-ir/select.ll | 83 ++++++++++ .../Mips/GlobalISel/regbankselect/select.mir | 70 +++++++++ llvm/test/CodeGen/PowerPC/adde_return_type.ll | 11 ++ llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn | 2 +- 12 files changed, 443 insertions(+), 12 deletions(-) create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/instruction-select/select.mir create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/legalizer/select.mir create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/select.ll create mode 100644 llvm/test/CodeGen/Mips/GlobalISel/regbankselect/select.mir create mode 100644 llvm/test/CodeGen/PowerPC/adde_return_type.ll