[Tcwg-commits] [gcc] branch master updated (b14af304965 -> 340cd371d63)

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unknown user pushed a change to branch master in repository gcc.

from b14af304965 Machine_Mode: Extend machine_mode from 8 to 16 bits new ebce8ee8993 arm: Mve testsuite improvements new ae180f26109 arm: Fix vstrwq* backend + testsuite new f2dd012ae6c arm: Mve backend + testsuite fixes 2 new 8eedd1e1d6a arm: Stop vadcq, vsbcq intrinsics from overwriting the FPSC [...] new 64a38e2f7c8 arm: Fix overloading of MVE scalar constant parameters on vbicq new 10a0ee8a9c0 arm: Fix MVE header pointer overloads this time (and a bit [...] new 8c0c310a4f6 arm testsuite: Remove reduntant tests new 7587c2e3844 arm testsuite: XFAIL or relax registers in some tests [PR109697] new 340cd371d63 arm testsuite: Shifts and get_FPSCR ACLE optimisation fixes

The 9 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.

Summary of changes: gcc/config/arm/arm_mve.h | 930 +++++++++++---------- gcc/config/arm/constraints.md | 20 +- gcc/config/arm/mve.md | 76 +- gcc/config/arm/predicates.md | 14 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/asrl.c | 21 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/lsll.c | 33 +- .../gcc.target/arm/mve/intrinsics/mve_fp_vaddq_n.c | 47 -- .../intrinsics/mve_intrinsic_type_overloads-fp.c | 55 +- .../intrinsics/mve_intrinsic_type_overloads-int.c | 74 +- .../gcc.target/arm/mve/intrinsics/mve_vaddq_m.c | 48 -- .../gcc.target/arm/mve/intrinsics/mve_vaddq_n.c | 31 - .../arm/mve/intrinsics/mve_vddupq_m_n_u16.c | 13 - .../arm/mve/intrinsics/mve_vddupq_m_n_u32.c | 13 - .../arm/mve/intrinsics/mve_vddupq_m_n_u8.c | 13 - .../arm/mve/intrinsics/mve_vddupq_n_u16.c | 13 - .../arm/mve/intrinsics/mve_vddupq_n_u32.c | 13 - .../arm/mve/intrinsics/mve_vddupq_n_u8.c | 13 - .../arm/mve/intrinsics/mve_vddupq_x_n_u16.c | 12 - .../arm/mve/intrinsics/mve_vddupq_x_n_u32.c | 12 - .../arm/mve/intrinsics/mve_vddupq_x_n_u8.c | 12 - .../arm/mve/intrinsics/mve_vdwdupq_x_n_u16.c | 13 - .../arm/mve/intrinsics/mve_vdwdupq_x_n_u32.c | 13 - .../arm/mve/intrinsics/mve_vdwdupq_x_n_u8.c | 13 - .../arm/mve/intrinsics/mve_vidupq_m_n_u16.c | 13 - .../arm/mve/intrinsics/mve_vidupq_m_n_u32.c | 12 - .../arm/mve/intrinsics/mve_vidupq_m_n_u8.c | 13 - .../arm/mve/intrinsics/mve_vidupq_n_u16.c | 13 - .../arm/mve/intrinsics/mve_vidupq_n_u32.c | 12 - .../arm/mve/intrinsics/mve_vidupq_n_u8.c | 13 - .../arm/mve/intrinsics/mve_vidupq_x_n_u16.c | 12 - .../arm/mve/intrinsics/mve_vidupq_x_n_u32.c | 12 - .../arm/mve/intrinsics/mve_vidupq_x_n_u8.c | 12 - .../arm/mve/intrinsics/mve_viwdupq_x_n_u16.c | 13 - .../arm/mve/intrinsics/mve_viwdupq_x_n_u32.c | 13 - .../arm/mve/intrinsics/mve_viwdupq_x_n_u8.c | 13 - .../mve/intrinsics/mve_vldrdq_gather_offset_s64.c | 12 - .../mve/intrinsics/mve_vldrdq_gather_offset_u64.c | 12 - .../intrinsics/mve_vldrdq_gather_offset_z_s64.c | 12 - .../intrinsics/mve_vldrdq_gather_offset_z_u64.c | 12 - .../mve_vldrdq_gather_shifted_offset_s64.c | 12 - .../mve_vldrdq_gather_shifted_offset_u64.c | 12 - .../mve_vldrdq_gather_shifted_offset_z_s64.c | 12 - .../mve_vldrdq_gather_shifted_offset_z_u64.c | 12 - .../mve/intrinsics/mve_vldrhq_gather_offset_f16.c | 12 - .../mve/intrinsics/mve_vldrhq_gather_offset_s16.c | 12 - .../mve/intrinsics/mve_vldrhq_gather_offset_s32.c | 12 - .../mve/intrinsics/mve_vldrhq_gather_offset_u16.c | 12 - .../mve/intrinsics/mve_vldrhq_gather_offset_u32.c | 13 - .../intrinsics/mve_vldrhq_gather_offset_z_f16.c | 12 - .../intrinsics/mve_vldrhq_gather_offset_z_s16.c | 12 - .../intrinsics/mve_vldrhq_gather_offset_z_s32.c | 12 - .../intrinsics/mve_vldrhq_gather_offset_z_u16.c | 13 - .../intrinsics/mve_vldrhq_gather_offset_z_u32.c | 13 - .../mve_vldrhq_gather_shifted_offset_f16.c | 12 - .../mve_vldrhq_gather_shifted_offset_s16.c | 13 - .../mve_vldrhq_gather_shifted_offset_s32.c | 13 - .../mve_vldrhq_gather_shifted_offset_u16.c | 13 - .../mve_vldrhq_gather_shifted_offset_u32.c | 13 - .../mve_vldrhq_gather_shifted_offset_z_f16.c | 13 - .../mve_vldrhq_gather_shifted_offset_z_s16.c | 13 - .../mve_vldrhq_gather_shifted_offset_z_s32.c | 12 - .../mve_vldrhq_gather_shifted_offset_z_u16.c | 12 - .../mve_vldrhq_gather_shifted_offset_z_u32.c | 12 - .../mve/intrinsics/mve_vldrwq_gather_offset_f32.c | 12 - .../mve/intrinsics/mve_vldrwq_gather_offset_s32.c | 13 - .../mve/intrinsics/mve_vldrwq_gather_offset_u32.c | 13 - .../intrinsics/mve_vldrwq_gather_offset_z_f32.c | 12 - .../intrinsics/mve_vldrwq_gather_offset_z_s32.c | 13 - .../intrinsics/mve_vldrwq_gather_offset_z_u32.c | 13 - .../mve_vldrwq_gather_shifted_offset_f32.c | 12 - .../mve_vldrwq_gather_shifted_offset_s32.c | 13 - .../mve_vldrwq_gather_shifted_offset_u32.c | 13 - .../mve_vldrwq_gather_shifted_offset_z_f32.c | 12 - .../mve_vldrwq_gather_shifted_offset_z_s32.c | 13 - .../mve_vldrwq_gather_shifted_offset_z_u32.c | 13 - .../intrinsics/mve_vstore_scatter_shifted_offset.c | 141 ---- .../mve_vstore_scatter_shifted_offset_p.c | 142 ---- .../gcc.target/arm/mve/intrinsics/sqrshr.c | 21 +- .../gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c | 21 +- .../gcc.target/arm/mve/intrinsics/sqshl.c | 21 +- .../gcc.target/arm/mve/intrinsics/sqshll.c | 21 +- .../gcc.target/arm/mve/intrinsics/srshr.c | 21 +- .../gcc.target/arm/mve/intrinsics/srshrl.c | 21 +- .../gcc.target/arm/mve/intrinsics/uqrshl.c | 33 +- .../gcc.target/arm/mve/intrinsics/uqrshll_sat48.c | 33 +- .../gcc.target/arm/mve/intrinsics/uqshl.c | 21 +- .../gcc.target/arm/mve/intrinsics/uqshll.c | 21 +- .../gcc.target/arm/mve/intrinsics/urshr.c | 35 +- .../gcc.target/arm/mve/intrinsics/urshrl.c | 33 +- .../gcc.target/arm/mve/intrinsics/vadciq_m_s32.c | 46 +- .../gcc.target/arm/mve/intrinsics/vadciq_m_u32.c | 46 +- .../gcc.target/arm/mve/intrinsics/vadciq_s32.c | 36 +- .../gcc.target/arm/mve/intrinsics/vadciq_u32.c | 36 +- .../gcc.target/arm/mve/intrinsics/vadcq_m_s32.c | 58 +- .../gcc.target/arm/mve/intrinsics/vadcq_m_u32.c | 58 +- .../gcc.target/arm/mve/intrinsics/vadcq_s32.c | 48 +- .../gcc.target/arm/mve/intrinsics/vadcq_u32.c | 48 +- .../arm/mve/intrinsics/vaddq_m_n_f16-1.c | 12 - .../arm/mve/intrinsics/vaddq_m_n_f32-1.c | 12 - .../arm/mve/intrinsics/vaddq_x_n_f16-1.c | 12 - .../arm/mve/intrinsics/vaddq_x_n_f32-1.c | 12 - .../gcc.target/arm/mve/intrinsics/vandq_f16.c | 24 +- .../gcc.target/arm/mve/intrinsics/vandq_f32.c | 24 +- .../gcc.target/arm/mve/intrinsics/vandq_m_f16.c | 34 +- .../gcc.target/arm/mve/intrinsics/vandq_m_f32.c | 34 +- .../gcc.target/arm/mve/intrinsics/vandq_m_s16.c | 34 +- .../gcc.target/arm/mve/intrinsics/vandq_m_s32.c | 34 +- .../gcc.target/arm/mve/intrinsics/vandq_m_s8.c | 34 +- .../gcc.target/arm/mve/intrinsics/vandq_m_u16.c | 34 +- .../gcc.target/arm/mve/intrinsics/vandq_m_u32.c | 34 +- .../gcc.target/arm/mve/intrinsics/vandq_m_u8.c | 34 +- .../gcc.target/arm/mve/intrinsics/vandq_s16.c | 24 +- .../gcc.target/arm/mve/intrinsics/vandq_s32.c | 24 +- .../gcc.target/arm/mve/intrinsics/vandq_s8.c | 24 +- .../gcc.target/arm/mve/intrinsics/vandq_u16.c | 24 +- .../gcc.target/arm/mve/intrinsics/vandq_u32.c | 24 +- .../gcc.target/arm/mve/intrinsics/vandq_u8.c | 24 +- .../gcc.target/arm/mve/intrinsics/vandq_x_f16.c | 33 +- .../gcc.target/arm/mve/intrinsics/vandq_x_f32.c | 33 +- .../gcc.target/arm/mve/intrinsics/vandq_x_s16.c | 33 +- .../gcc.target/arm/mve/intrinsics/vandq_x_s32.c | 33 +- .../gcc.target/arm/mve/intrinsics/vandq_x_s8.c | 33 +- .../gcc.target/arm/mve/intrinsics/vandq_x_u16.c | 33 +- .../gcc.target/arm/mve/intrinsics/vandq_x_u32.c | 33 +- .../gcc.target/arm/mve/intrinsics/vandq_x_u8.c | 33 +- .../gcc.target/arm/mve/intrinsics/vbicq_f16.c | 23 +- .../gcc.target/arm/mve/intrinsics/vbicq_f32.c | 23 +- .../gcc.target/arm/mve/intrinsics/vbicq_m_f16.c | 34 +- .../gcc.target/arm/mve/intrinsics/vbicq_m_f32.c | 34 +- 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23 +- .../gcc.target/arm/mve/intrinsics/vbicq_u32.c | 23 +- .../gcc.target/arm/mve/intrinsics/vbicq_u8.c | 23 +- .../gcc.target/arm/mve/intrinsics/vbicq_x_f16.c | 33 +- .../gcc.target/arm/mve/intrinsics/vbicq_x_f32.c | 33 +- .../gcc.target/arm/mve/intrinsics/vbicq_x_s16.c | 33 +- .../gcc.target/arm/mve/intrinsics/vbicq_x_s32.c | 33 +- .../gcc.target/arm/mve/intrinsics/vbicq_x_s8.c | 33 +- .../gcc.target/arm/mve/intrinsics/vbicq_x_u16.c | 33 +- .../gcc.target/arm/mve/intrinsics/vbicq_x_u32.c | 33 +- .../gcc.target/arm/mve/intrinsics/vbicq_x_u8.c | 33 +- .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c | 34 +- .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c | 34 +- .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c | 34 +- .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c | 34 +- .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c | 34 +- .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c | 34 +- .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c | 34 +- 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| 30 +- .../gcc.target/arm/mve/intrinsics/vorrq_n_s32.c | 30 +- .../gcc.target/arm/mve/intrinsics/vorrq_n_u16.c | 30 +- .../gcc.target/arm/mve/intrinsics/vorrq_n_u32.c | 32 +- .../gcc.target/arm/mve/intrinsics/vorrq_s16.c | 24 +- .../gcc.target/arm/mve/intrinsics/vorrq_s32.c | 24 +- .../gcc.target/arm/mve/intrinsics/vorrq_s8.c | 24 +- .../gcc.target/arm/mve/intrinsics/vorrq_u16.c | 24 +- .../gcc.target/arm/mve/intrinsics/vorrq_u32.c | 24 +- .../gcc.target/arm/mve/intrinsics/vorrq_u8.c | 24 +- .../gcc.target/arm/mve/intrinsics/vorrq_x_f16.c | 33 +- .../gcc.target/arm/mve/intrinsics/vorrq_x_f32.c | 33 +- .../gcc.target/arm/mve/intrinsics/vorrq_x_s16.c | 33 +- .../gcc.target/arm/mve/intrinsics/vorrq_x_s32.c | 33 +- .../gcc.target/arm/mve/intrinsics/vorrq_x_s8.c | 33 +- .../gcc.target/arm/mve/intrinsics/vorrq_x_u16.c | 33 +- .../gcc.target/arm/mve/intrinsics/vorrq_x_u32.c | 33 +- .../gcc.target/arm/mve/intrinsics/vorrq_x_u8.c | 33 +- .../gcc.target/arm/mve/intrinsics/vpnot.c | 25 +- .../gcc.target/arm/mve/intrinsics/vpselq_f16.c | 28 +- .../gcc.target/arm/mve/intrinsics/vpselq_f32.c | 28 +- .../gcc.target/arm/mve/intrinsics/vpselq_s16.c | 28 +- .../gcc.target/arm/mve/intrinsics/vpselq_s32.c | 28 +- .../gcc.target/arm/mve/intrinsics/vpselq_s64.c | 28 +- .../gcc.target/arm/mve/intrinsics/vpselq_s8.c | 28 +- .../gcc.target/arm/mve/intrinsics/vpselq_u16.c | 28 +- .../gcc.target/arm/mve/intrinsics/vpselq_u32.c | 28 +- .../gcc.target/arm/mve/intrinsics/vpselq_u64.c | 28 +- .../gcc.target/arm/mve/intrinsics/vpselq_u8.c | 28 +- .../gcc.target/arm/mve/intrinsics/vqmovnbq_m_s16.c | 33 +- .../gcc.target/arm/mve/intrinsics/vqmovnbq_m_s32.c | 33 +- .../gcc.target/arm/mve/intrinsics/vqmovnbq_m_u16.c | 33 +- .../gcc.target/arm/mve/intrinsics/vqmovnbq_m_u32.c | 33 +- .../gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c | 24 +- .../gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c | 24 +- .../gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c | 24 +- .../gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c | 24 +- .../gcc.target/arm/mve/intrinsics/vqmovntq_m_s16.c | 33 +- .../gcc.target/arm/mve/intrinsics/vqmovntq_m_s32.c | 33 +- .../gcc.target/arm/mve/intrinsics/vqmovntq_m_u16.c | 33 +- .../gcc.target/arm/mve/intrinsics/vqmovntq_m_u32.c | 33 +- .../gcc.target/arm/mve/intrinsics/vqmovntq_s16.c | 24 +- .../gcc.target/arm/mve/intrinsics/vqmovntq_s32.c | 24 +- .../gcc.target/arm/mve/intrinsics/vqmovntq_u16.c | 24 +- .../gcc.target/arm/mve/intrinsics/vqmovntq_u32.c | 24 +- .../arm/mve/intrinsics/vqmovunbq_m_s16.c | 33 +- .../arm/mve/intrinsics/vqmovunbq_m_s32.c | 33 +- .../gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c | 24 +- .../gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c | 24 +- .../arm/mve/intrinsics/vqmovuntq_m_s16.c | 33 +- .../arm/mve/intrinsics/vqmovuntq_m_s32.c | 33 +- .../gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c | 24 +- .../gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c | 24 +- .../arm/mve/intrinsics/vqrdmladhq_m_s16.c | 2 +- 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.../arm/mve/intrinsics/vqrdmulhq_m_s16.c | 2 +- .../arm/mve/intrinsics/vqrdmulhq_m_s32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c | 2 +- .../arm/mve/intrinsics/vqrdmulhq_n_s16.c | 2 +- .../arm/mve/intrinsics/vqrdmulhq_n_s32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c | 2 +- .../arm/mve/intrinsics/vqrshlq_m_n_s16.c | 33 +- .../arm/mve/intrinsics/vqrshlq_m_n_s32.c | 33 +- .../gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s8.c | 33 +- .../arm/mve/intrinsics/vqrshlq_m_n_u16.c | 33 +- .../arm/mve/intrinsics/vqrshlq_m_n_u32.c | 33 +- .../gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u8.c | 33 +- .../gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c | 34 +- .../gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c | 34 +- .../gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c | 34 +- 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34 +- .../arm/mve/intrinsics/vqrshrnbq_m_n_u32.c | 34 +- .../arm/mve/intrinsics/vqrshrnbq_n_s16.c | 24 +- .../arm/mve/intrinsics/vqrshrnbq_n_s32.c | 24 +- .../arm/mve/intrinsics/vqrshrnbq_n_u16.c | 24 +- .../arm/mve/intrinsics/vqrshrnbq_n_u32.c | 24 +- .../arm/mve/intrinsics/vqrshrntq_m_n_s16.c | 34 +- .../arm/mve/intrinsics/vqrshrntq_m_n_s32.c | 34 +- .../arm/mve/intrinsics/vqrshrntq_m_n_u16.c | 34 +- .../arm/mve/intrinsics/vqrshrntq_m_n_u32.c | 34 +- .../arm/mve/intrinsics/vqrshrntq_n_s16.c | 24 +- .../arm/mve/intrinsics/vqrshrntq_n_s32.c | 24 +- .../arm/mve/intrinsics/vqrshrntq_n_u16.c | 24 +- .../arm/mve/intrinsics/vqrshrntq_n_u32.c | 24 +- .../arm/mve/intrinsics/vqrshrunbq_m_n_s16.c | 34 +- .../arm/mve/intrinsics/vqrshrunbq_m_n_s32.c | 34 +- .../arm/mve/intrinsics/vqrshrunbq_n_s16.c | 24 +- .../arm/mve/intrinsics/vqrshrunbq_n_s32.c | 24 +- .../arm/mve/intrinsics/vqrshruntq_m_n_s16.c | 34 +- .../arm/mve/intrinsics/vqrshruntq_m_n_s32.c | 34 +- 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