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from 78e2fb2 Add optimization bisect opt-in calls for ARM passes new 185caef [LVI] Make a precondition explicit rather than handling a cas [...] new 1ca1fca Optimize store of "bitcast" from vector to aggregate. new 217903d Comment formating. NFC new 3c50cf9 Reformat LLVMConstPointerNull. NFC new c7ca130 Add optimization bisect opt-in calls for AMDGPU passes
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Summary of changes: include/llvm/IR/Value.h | 3 +- lib/Analysis/LazyValueInfo.cpp | 3 +- lib/IR/Core.cpp | 3 +- lib/Target/AMDGPU/AMDGPUAnnotateUniformValues.cpp | 3 + lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp | 2 +- lib/Target/AMDGPU/R600ClauseMergePass.cpp | 3 + lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp | 3 + lib/Target/AMDGPU/SIFoldOperands.cpp | 3 + lib/Target/AMDGPU/SILoadStoreOptimizer.cpp | 3 + lib/Target/AMDGPU/SIShrinkInstructions.cpp | 3 + .../InstCombine/InstCombineLoadStoreAlloca.cpp | 60 ++++++++++++++++++ .../InstCombine/insert-val-extract-elem.ll | 74 ++++++++++++++++++++++ 12 files changed, 157 insertions(+), 6 deletions(-) create mode 100644 test/Transforms/InstCombine/insert-val-extract-elem.ll