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from 2e9c70af234 [AArch64][GlobalISel] Implement selection for G_UNMERGE of [...] new 4a50374b480 [AArch64][GlobalISel] Add isel support for G_UADDO on s32s [...] new d8706fcd747 MIR: Allow targets to serialize MachineFunctionInfo
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Summary of changes: {lib => include/llvm}/CodeGen/MIRParser/MIParser.h | 4 +- include/llvm/CodeGen/MIRYamlMapping.h | 17 +++ include/llvm/CodeGen/MachineModuleInfo.h | 2 + include/llvm/Target/TargetMachine.h | 28 ++++ lib/CodeGen/MIRParser/MIParser.cpp | 2 +- lib/CodeGen/MIRParser/MIRParser.cpp | 21 ++- lib/CodeGen/MIRPrinter.cpp | 5 + lib/Target/AArch64/AArch64InstructionSelector.cpp | 37 +++++ lib/Target/AArch64/AArch64LegalizerInfo.cpp | 2 +- lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 73 ++++++++++ lib/Target/AMDGPU/AMDGPUTargetMachine.h | 8 ++ lib/Target/AMDGPU/LLVMBuild.txt | 2 +- lib/Target/AMDGPU/SIISelLowering.cpp | 19 ++- lib/Target/AMDGPU/SIMachineFunctionInfo.cpp | 39 ++++++ lib/Target/AMDGPU/SIMachineFunctionInfo.h | 54 +++++++- .../GlobalISel/legalizer-info-validation.mir | 2 +- test/CodeGen/AArch64/GlobalISel/select-uaddo.mir | 62 +++++++++ test/CodeGen/AArch64/arm64-xaluo.ll | 9 ++ test/CodeGen/AMDGPU/scalar-store-cache-flush.mir | 14 ++ test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir | 5 + test/CodeGen/AMDGPU/spill-before-exec.mir | 4 + test/CodeGen/AMDGPU/spill-empty-live-interval.mir | 10 ++ .../AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir | 7 +- test/CodeGen/AMDGPU/subreg-split-live-in-error.mir | 5 + .../MIR/AMDGPU/machine-function-info-no-ir.mir | 151 +++++++++++++++++++++ ...machine-function-info-register-parse-error1.mir | 12 ++ ...machine-function-info-register-parse-error2.mir | 12 ++ test/CodeGen/MIR/AMDGPU/machine-function-info.ll | 83 +++++++++++ .../MIR/AMDGPU/mfi-frame-offset-reg-class.mir | 13 ++ .../AMDGPU/mfi-parse-error-frame-offset-reg.mir | 12 ++ .../AMDGPU/mfi-parse-error-scratch-rsrc-reg.mir | 12 ++ .../mfi-parse-error-scratch-wave-offset-reg.mir | 12 ++ .../mfi-parse-error-stack-ptr-offset-reg.mir | 12 ++ .../MIR/AMDGPU/mfi-scratch-rsrc-reg-reg-class.mir | 13 ++ .../AMDGPU/mfi-scratch-wave-offset-reg-class.mir | 13 ++ .../MIR/AMDGPU/mfi-stack-ptr-offset-reg-class.mir | 13 ++ 36 files changed, 775 insertions(+), 14 deletions(-) rename {lib => include/llvm}/CodeGen/MIRParser/MIParser.h (98%) create mode 100644 test/CodeGen/AArch64/GlobalISel/select-uaddo.mir create mode 100644 test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir create mode 100644 test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-er [...] create mode 100644 test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-er [...] create mode 100644 test/CodeGen/MIR/AMDGPU/machine-function-info.ll create mode 100644 test/CodeGen/MIR/AMDGPU/mfi-frame-offset-reg-class.mir create mode 100644 test/CodeGen/MIR/AMDGPU/mfi-parse-error-frame-offset-reg.mir create mode 100644 test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-rsrc-reg.mir create mode 100644 test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-wave-offset-reg.mir create mode 100644 test/CodeGen/MIR/AMDGPU/mfi-parse-error-stack-ptr-offset-reg.mir create mode 100644 test/CodeGen/MIR/AMDGPU/mfi-scratch-rsrc-reg-reg-class.mir create mode 100644 test/CodeGen/MIR/AMDGPU/mfi-scratch-wave-offset-reg-class.mir create mode 100644 test/CodeGen/MIR/AMDGPU/mfi-stack-ptr-offset-reg-class.mir