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from 38b58f1b4f4 [Hexagon] Improve scheduling based on register pressure new a07f460d529 [RISCV] Add codegen for RV32F arithmetic and conversion operations
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Summary of changes: lib/Target/RISCV/RISCVISelLowering.cpp | 53 ++++++++- lib/Target/RISCV/RISCVInstrInfoF.td | 56 ++++++++++ test/CodeGen/RISCV/float-arith.ll | 190 +++++++++++++++++++++++++++++++++ test/CodeGen/RISCV/float-convert.ll | 72 +++++++++++++ 4 files changed, 366 insertions(+), 5 deletions(-) create mode 100644 test/CodeGen/RISCV/float-arith.ll create mode 100644 test/CodeGen/RISCV/float-convert.ll