[Tcwg-commits] [toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-allyesconfig updated (70a8027c60f -> 6293cd05045)

29 Jun 2019


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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-allyesconfig
in repository toolchain/ci/llvm-project.
from  70a8027c60f [llvm-ar] Document response file support in --help
      adds  d900ef0a5b1 [clang-doc] Handle anonymous namespaces
      adds  4b733ca617e Default to Secure PLT on PPC for musl libc.
      adds  1c6337ca5ab [TSan] Fix build build breakage on Android
      adds  9a6cef74d8a [demangle] Support for C++2a char8_t
      adds  ab4b2364e56 [GVNSink] Add unary FNeg support to GVNSink pass
      adds  642fe780abe Revert enabling frame pointer elimination on OpenBSD for now.
      adds  30e5cf1d8f3 [NewGVN] Add unary FNeg support to NewGVN pass
      adds  597ba180086 [WebAssembly] Assembler: Improve section parsing.
      adds  fc222e23cae [WebAssembly] Assembler: Allow offsets and p2align in symbol load.
      adds  1242d8f333a [OPENMP]Improve analysis of implicit captures.
      adds  573b241c68a [Lanai] auto-generate complete test checks; NFC
      adds  b671535983f [NFC][NewGVN] Explicitly check fpmath metadata in fpmath.ll
      adds  f2128b28cdb Get the expression parser to handle missing weak symbols. M [...]
      adds  9126c84f50f [x86] remove stale comment about cmov; NFC
      adds  35bcba4fae8 [WebAssembly] Allow @object in .type directives.
      adds  319c87d94fd [WebAssembly] Assembler: support .int16/32/64 directives.
      adds  caf4cee6fe8 [clang][test][NFC] Explicitly specify clang ABI in AST Dumper test
      adds  69d9c314337 AMDGPU: Add baseline test for packed shufflevector
      adds  da47e2cac38 Revert "[clang][NewPM] Fix broken profile test"
      adds  1504b6ee7ea [IndVars] Remove a bit of manual constant folding [NFC]
      adds  ade51624327 AMDGPU/GlobalISel: RegBankSelect for some simple leaf intrinsics
      adds  6aafb3068f9 AMDGPU/GlobalISel: RegBankSelect for amdgcn.div.fmas
      adds  5ea3c9adb27 AMDGPU/GlobalISel: RegBankSelect for icmp/fcmp intrinsics
      adds  b416d5fc8b8 AMDGPU/GlobalISel: RegBankSelect for some easy intrinsics
      adds  adb1f21e521 AMDGPU/GlobalISel: RegBankSelect for some DS intrinsics
      adds  fd82cf4f4d0 AMDGPU/GlobalISel: RegBankSelect for atomic.inc/atomic.dec
      adds  be4148062b1 [TSan] Attempt to fix linker error for Linux on AArch64
      adds  0d452097571 AMDGPU/GlobalISel: RegBankSelect for update.dpp
      adds  a83e94ebf26 Use const auto *
      adds  7889d4ce66f AMDGPU/GlobalISel: Add some more tests for icmp select
      adds  765eba38c8d [Driver] Fix style issues of --print-supported-cpus after D63105
      adds  b72664fd21c Partial revert of "[llvm-ar] Document response file support [...]
      adds  2d756c4feb6 [LFTR] Fix post-inc pointer IV with truncated exit count (PR41998)
      adds  9e9eb62f9fd [APInt] Fix getBitsNeeded for INT_MIN values
      adds  fe107fcde4d [IR][Patternmatch] Add m_SpecificInt_ULT() predicate
      adds  e3a94ba4a92 [InstCombine] Shift amount reassociation (PR42391)
      adds  61a8b62b4c9 [LFTR] Remove unnecessary latch check; NFCI
      adds  77dc1e85683 [InstCombine] canonicalize fmin/fmax to LLVM intrinsics min [...]
      adds  8023c844338 [LFTR] Rephrase getLoopTest into "based-on" check; NFCI
       new  6293cd05045 Replace tabs with spaces.
The 1 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails.  The revisions
listed as "adds" were already present in the repository and have only
been added to this reference.
Summary of changes:
 clang-tools-extra/clang-doc/Representation.cpp     |  33 +
 clang-tools-extra/clang-doc/Representation.h       |   2 +
 clang-tools-extra/clang-doc/Serialize.cpp          |  75 +-
 clang-tools-extra/clang-doc/tool/ClangDocMain.cpp  |   7 +-
 .../unittests/clang-doc/SerializeTest.cpp          |   1 +
 clang/include/clang/Driver/Options.td              |   6 +-
 clang/lib/CodeGen/BackendUtil.cpp                  |   6 -
 clang/lib/Driver/Driver.cpp                        |  20 +-
 clang/lib/Driver/ToolChains/Clang.cpp              |  13 -
 clang/lib/Frontend/CompilerInvocation.cpp          |   2 +-
 clang/lib/Sema/SemaOpenMP.cpp                      |  58 +-
 .../AST/ast-dump-record-definition-data-json.cpp   |   2 +-
 clang/test/Driver/frame-pointer-elim.c             |  13 -
 clang/test/Driver/print-supported-cpus.c           |  36 +-
 .../distribute_parallel_for_default_messages.cpp   |   8 +-
 ...stribute_parallel_for_simd_default_messages.cpp |   8 +-
 clang/test/OpenMP/nvptx_lambda_capturing.cpp       |   4 +-
 .../target_parallel_for_default_messages.cpp       |   4 +-
 .../target_parallel_for_simd_default_messages.cpp  |   4 +-
 ...rget_teams_distribute_firstprivate_messages.cpp |   2 +-
 .../teams_distribute_firstprivate_messages.cpp     |   2 +-
 .../teams_distribute_lastprivate_messages.cpp      |   2 +-
 ...stribute_parallel_for_firstprivate_messages.cpp |   2 +-
 ...istribute_parallel_for_lastprivate_messages.cpp |   2 +-
 ..._distribute_parallel_for_reduction_messages.cpp |   4 +-
 ...stribute_parallel_for_simd_aligned_messages.cpp |   2 +-
 ...ute_parallel_for_simd_firstprivate_messages.cpp |   2 +-
 ...bute_parallel_for_simd_lastprivate_messages.cpp |   2 +-
 ...istribute_parallel_for_simd_linear_messages.cpp |   4 +-
 ...ribute_parallel_for_simd_reduction_messages.cpp |   4 +-
 .../OpenMP/teams_distribute_reduction_messages.cpp |   4 +-
 .../teams_distribute_simd_aligned_messages.cpp     |   2 +-
 ...teams_distribute_simd_firstprivate_messages.cpp |   2 +-
 .../teams_distribute_simd_lastprivate_messages.cpp |   2 +-
 .../teams_distribute_simd_linear_messages.cpp      |   4 +-
 .../teams_distribute_simd_reduction_messages.cpp   |   4 +-
 clang/test/OpenMP/teams_firstprivate_messages.cpp  |   2 +-
 clang/test/OpenMP/teams_reduction_messages.cpp     |   4 +-
 clang/test/Profile/gcc-flag-compatibility.c        |  12 +-
 clang/tools/driver/cc1_main.cpp                    |   9 +-
 compiler-rt/lib/tsan/rtl/tsan_platform_linux.cc    |   3 +-
 compiler-rt/lib/tsan/rtl/tsan_rtl_aarch64.S        |   8 -
 libcxxabi/src/demangle/ItaniumDemangle.h           |   4 +
 libcxxabi/test/test_demangle.pass.cpp              |   3 +
 lldb/include/lldb/Expression/IRExecutionUnit.h     |  12 +-
 lldb/include/lldb/Symbol/Symbol.h                  |   7 +-
 lldb/include/lldb/lldb-enumerations.h              |   2 +
 .../test/expression_command/weak_symbols/Makefile  |  26 +
 .../weak_symbols/TestWeakSymbols.py                |  83 ++
 .../test/expression_command/weak_symbols/dylib.c   |  14 +
 .../test/expression_command/weak_symbols/dylib.h   |   8 +
 .../test/expression_command/weak_symbols/main.c    |  23 +
 .../weak_symbols/module.modulemap                  |   3 +
 .../gdb_remote_client/TestRecognizeBreakpoint.py   |   4 +-
 lldb/source/Expression/IRExecutionUnit.cpp         |  91 +-
 lldb/source/Expression/IRInterpreter.cpp           |   5 +-
 .../Plugins/ExpressionParser/Clang/IRForTarget.cpp |  18 +-
 .../Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp  |   2 +
 .../SymbolFile/DWARF/DWARFDebugInfoEntry.cpp       |  10 +-
 lldb/source/Symbol/Block.cpp                       |   4 +-
 lldb/source/Symbol/Symbol.cpp                      |  15 +-
 llvm/include/llvm/Demangle/ItaniumDemangle.h       |   4 +
 llvm/include/llvm/IR/PatternMatch.h                |  14 +
 llvm/lib/MC/MCParser/WasmAsmParser.cpp             |  45 +-
 llvm/lib/Support/APInt.cpp                         |   5 +-
 llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp  |  93 ++-
 llvm/lib/Target/PowerPC/PPCSubtarget.cpp           |   3 +-
 .../WebAssembly/AsmParser/WebAssemblyAsmParser.cpp |  35 +-
 llvm/lib/Target/X86/X86ISelLowering.h              |   3 +-
 .../Transforms/InstCombine/InstCombineShifts.cpp   |  48 ++
 llvm/lib/Transforms/Scalar/GVNSink.cpp             |   1 +
 llvm/lib/Transforms/Scalar/IndVarSimplify.cpp      | 143 ++--
 llvm/lib/Transforms/Scalar/NewGVN.cpp              |   1 +
 llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp     |  38 +-
 .../CodeGen/AMDGPU/GlobalISel/inst-select-icmp.mir | 112 ++-
 .../GlobalISel/regbankselect-amdgcn.atomic.dec.mir |  80 ++
 .../GlobalISel/regbankselect-amdgcn.atomic.inc.mir |  80 ++
 .../GlobalISel/regbankselect-amdgcn.div.fmas.mir   | 106 +++
 .../GlobalISel/regbankselect-amdgcn.ds.append.mir  |  36 +
 .../regbankselect-amdgcn.ds.bpermute.mir           |  24 +
 .../GlobalISel/regbankselect-amdgcn.ds.consume.mir |  36 +
 .../GlobalISel/regbankselect-amdgcn.ds.fmax.mir    |  83 ++
 .../GlobalISel/regbankselect-amdgcn.ds.fmin.mir    |  83 ++
 .../GlobalISel/regbankselect-amdgcn.ds.permute.mir |  24 +
 .../GlobalISel/regbankselect-amdgcn.fcmp.mir       |  67 ++
 .../regbankselect-amdgcn.groupstaticsize.mir       |  14 +
 .../GlobalISel/regbankselect-amdgcn.icmp.mir       |  67 ++
 ...bankselect-amdgcn.s.get.waveid.in.workgroup.mir |  14 +
 .../GlobalISel/regbankselect-amdgcn.s.getpc.mir    |  14 +
 .../GlobalISel/regbankselect-amdgcn.s.getreg.mir   |  14 +
 .../regbankselect-amdgcn.s.memrealtime.mir         |  14 +
 .../GlobalISel/regbankselect-amdgcn.s.memtime.mir  |  14 +
 .../GlobalISel/regbankselect-amdgcn.update.dpp.mir |  82 ++
 llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll  | 928 +++++++++++++++++++++
 llvm/test/CodeGen/Lanai/sub-cmp-peephole.ll        | 117 ++-
 llvm/test/CodeGen/PowerPC/ppc32-pic-large.ll       |   2 +
 llvm/test/MC/WebAssembly/basic-assembly.s          |  13 +-
 llvm/test/Transforms/GVNSink/fpmath.ll             |   3 +-
 .../IndVarSimplify/2011-11-01-lftrptr.ll           |   7 +-
 .../test/Transforms/IndVarSimplify/lftr-pr41998.ll |   5 +-
 .../InstCombine/double-float-shrink-1.ll           |  11 +-
 llvm/test/Transforms/InstCombine/fast-math.ll      |  53 +-
 .../Transforms/InstCombine/float-shrink-compare.ll |  37 +-
 .../InstCombine/shift-amount-reassociation.ll      |  60 +-
 llvm/test/Transforms/NewGVN/fpmath.ll              |  14 +-
 llvm/test/tools/llvm-ar/response-file.test         |   9 -
 llvm/unittests/ADT/APIntTest.cpp                   |  17 +-
 llvm/unittests/IR/PatternMatch.cpp                 |  21 +
 108 files changed, 2854 insertions(+), 560 deletions(-)
 create mode 100644 lldb/packages/Python/lldbsuite/test/expression_command/weak_sym [...]
 create mode 100644 lldb/packages/Python/lldbsuite/test/expression_command/weak_sym [...]
 create mode 100644 lldb/packages/Python/lldbsuite/test/expression_command/weak_sym [...]
 create mode 100644 lldb/packages/Python/lldbsuite/test/expression_command/weak_sym [...]
 create mode 100644 lldb/packages/Python/lldbsuite/test/expression_command/weak_sym [...]
 create mode 100644 lldb/packages/Python/lldbsuite/test/expression_command/weak_sym [...]
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.atomic [...]
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.atomic [...]
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.append.mir
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.bpe [...]
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.con [...]
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.fmax.mir
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.fmin.mir
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.per [...]
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fcmp.mir
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.groups [...]
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.icmp.mir
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.get. [...]
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getpc.mir
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getreg.mir
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memr [...]
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memtime.mir
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.update [...]
 create mode 100644 llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
 delete mode 100644 llvm/test/tools/llvm-ar/response-file.test
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[Tcwg-commits] [toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-allyesconfig updated (70a8027c60f -> 6293cd05045)