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Yvan Roux pushed a change to branch linaro-local/gcc-6-integration-branch in repository toolchain/gcc.
from faa305b gcc/ Backport from trunk r240791. 2016-10-05 Kyrylo Tkach [...] new fe89a30 gcc/ Backport from trunk r240398. 2016-09-23 Matthew Waha [...]
The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.
Summary of changes: gcc/config.gcc | 2 +- gcc/config/arm/arm-arches.def | 10 +- gcc/config/arm/arm-builtins.c | 361 ++++---- gcc/config/arm/arm-c.c | 5 + gcc/config/arm/arm-protos.h | 4 + gcc/config/arm/arm-tables.opt | 16 +- gcc/config/arm/arm.c | 46 +- gcc/config/arm/arm.h | 14 + gcc/config/arm/arm.md | 88 +- gcc/config/arm/arm_fp16.h | 255 ++++++ gcc/config/arm/arm_neon.h | 850 +++++++++++++++++++ gcc/config/arm/arm_neon_builtins.def | 63 +- gcc/config/arm/arm_vfp_builtins.def | 51 ++ gcc/config/arm/bpabi.h | 4 + gcc/config/arm/iterators.md | 204 +++-- gcc/config/arm/neon.md | 574 ++++++++++++- gcc/config/arm/t-aprofile | 2 + gcc/config/arm/t-arm | 4 +- gcc/config/arm/unspecs.md | 26 +- gcc/config/arm/vec-common.md | 14 + gcc/config/arm/vfp.md | 665 ++++++++++++++- gcc/doc/invoke.texi | 13 + gcc/doc/sourcebuild.texi | 47 ++ gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-3.C | 1 + gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-4.C | 1 + .../gcc.dg/torture/arm-fp16-int-convert-alt.c | 1 + gcc/testsuite/gcc.dg/torture/arm-fp16-ops-3.c | 1 + gcc/testsuite/gcc.dg/torture/arm-fp16-ops-4.c | 1 + .../advsimd-intrinsics/advsimd-intrinsics.exp | 5 +- .../aarch64/advsimd-intrinsics/arm-neon-ref.h | 17 +- .../aarch64/advsimd-intrinsics/binary_op_float.inc | 170 ++++ .../aarch64/advsimd-intrinsics/binary_op_no64.inc | 57 +- .../advsimd-intrinsics/binary_scalar_op.inc | 160 ++++ .../aarch64/advsimd-intrinsics/cmp_fp_op.inc | 41 + .../aarch64/advsimd-intrinsics/cmp_op.inc | 80 ++ .../aarch64/advsimd-intrinsics/cmp_zero_op.inc | 111 +++ .../advsimd-intrinsics/ternary_scalar_op.inc | 206 +++++ .../aarch64/advsimd-intrinsics/unary_scalar_op.inc | 200 +++++ .../gcc.target/aarch64/advsimd-intrinsics/vabd.c | 57 +- .../aarch64/advsimd-intrinsics/vabdh_f16_1.c | 44 + .../gcc.target/aarch64/advsimd-intrinsics/vabs.c | 28 + .../aarch64/advsimd-intrinsics/vabsh_f16_1.c | 40 + .../gcc.target/aarch64/advsimd-intrinsics/vadd.c | 31 + .../aarch64/advsimd-intrinsics/vaddh_f16_1.c | 40 + .../gcc.target/aarch64/advsimd-intrinsics/vbsl.c | 28 + .../gcc.target/aarch64/advsimd-intrinsics/vcage.c | 10 + .../aarch64/advsimd-intrinsics/vcageh_f16_1.c | 22 + .../gcc.target/aarch64/advsimd-intrinsics/vcagt.c | 10 + .../aarch64/advsimd-intrinsics/vcagth_f16_1.c | 21 + .../gcc.target/aarch64/advsimd-intrinsics/vcale.c | 10 + .../aarch64/advsimd-intrinsics/vcaleh_f16_1.c | 22 + .../gcc.target/aarch64/advsimd-intrinsics/vcalt.c | 10 + .../aarch64/advsimd-intrinsics/vcalth_f16_1.c | 22 + .../gcc.target/aarch64/advsimd-intrinsics/vceq.c | 18 + .../aarch64/advsimd-intrinsics/vceqh_f16_1.c | 21 + .../aarch64/advsimd-intrinsics/vceqz_1.c | 27 + .../aarch64/advsimd-intrinsics/vceqzh_f16_1.c | 21 + .../gcc.target/aarch64/advsimd-intrinsics/vcge.c | 22 + .../aarch64/advsimd-intrinsics/vcgeh_f16_1.c | 22 + .../aarch64/advsimd-intrinsics/vcgez_1.c | 30 + .../aarch64/advsimd-intrinsics/vcgezh_f16_1.c | 22 + .../gcc.target/aarch64/advsimd-intrinsics/vcgt.c | 21 + .../aarch64/advsimd-intrinsics/vcgth_f16_1.c | 22 + .../aarch64/advsimd-intrinsics/vcgtz_1.c | 28 + .../aarch64/advsimd-intrinsics/vcgtzh_f16_1.c | 22 + .../gcc.target/aarch64/advsimd-intrinsics/vcle.c | 22 + .../aarch64/advsimd-intrinsics/vcleh_f16_1.c | 22 + .../aarch64/advsimd-intrinsics/vclez_1.c | 29 + .../aarch64/advsimd-intrinsics/vclezh_f16_1.c | 21 + .../gcc.target/aarch64/advsimd-intrinsics/vclt.c | 21 + .../aarch64/advsimd-intrinsics/vclth_f16_1.c | 22 + .../aarch64/advsimd-intrinsics/vcltz_1.c | 27 + .../aarch64/advsimd-intrinsics/vcltzh_f16_1.c | 21 + .../gcc.target/aarch64/advsimd-intrinsics/vcvt.c | 189 ++++- .../aarch64/advsimd-intrinsics/vcvtX.inc | 113 +++ .../aarch64/advsimd-intrinsics/vcvta_1.c | 33 + .../aarch64/advsimd-intrinsics/vcvtah_s16_f16_1.c | 23 + .../aarch64/advsimd-intrinsics/vcvtah_s32_f16_1.c | 53 ++ .../aarch64/advsimd-intrinsics/vcvtah_s64_f16_1.c | 23 + .../aarch64/advsimd-intrinsics/vcvtah_u16_f16_1.c | 23 + .../aarch64/advsimd-intrinsics/vcvtah_u32_f16_1.c | 53 ++ .../aarch64/advsimd-intrinsics/vcvtah_u64_f16_1.c | 23 + .../aarch64/advsimd-intrinsics/vcvth_f16_s16_1.c | 25 + .../aarch64/advsimd-intrinsics/vcvth_f16_s32_1.c | 52 ++ .../aarch64/advsimd-intrinsics/vcvth_f16_s64_1.c | 25 + .../aarch64/advsimd-intrinsics/vcvth_f16_u16_1.c | 25 + .../aarch64/advsimd-intrinsics/vcvth_f16_u32_1.c | 52 ++ .../aarch64/advsimd-intrinsics/vcvth_f16_u64_1.c | 25 + .../aarch64/advsimd-intrinsics/vcvth_n_f16_s16_1.c | 46 ++ .../aarch64/advsimd-intrinsics/vcvth_n_f16_s32_1.c | 99 +++ .../aarch64/advsimd-intrinsics/vcvth_n_f16_s64_1.c | 46 ++ .../aarch64/advsimd-intrinsics/vcvth_n_f16_u16_1.c | 46 ++ .../aarch64/advsimd-intrinsics/vcvth_n_f16_u32_1.c | 99 +++ .../aarch64/advsimd-intrinsics/vcvth_n_f16_u64_1.c | 46 ++ .../aarch64/advsimd-intrinsics/vcvth_n_s16_f16_1.c | 29 + .../aarch64/advsimd-intrinsics/vcvth_n_s32_f16_1.c | 100 +++ .../aarch64/advsimd-intrinsics/vcvth_n_s64_f16_1.c | 29 + .../aarch64/advsimd-intrinsics/vcvth_n_u16_f16_1.c | 29 + .../aarch64/advsimd-intrinsics/vcvth_n_u32_f16_1.c | 100 +++ .../aarch64/advsimd-intrinsics/vcvth_n_u64_f16_1.c | 29 + .../aarch64/advsimd-intrinsics/vcvth_s16_f16_1.c | 23 + .../aarch64/advsimd-intrinsics/vcvth_s32_f16_1.c | 53 ++ .../aarch64/advsimd-intrinsics/vcvth_s64_f16_1.c | 23 + .../aarch64/advsimd-intrinsics/vcvth_u16_f16_1.c | 23 + .../aarch64/advsimd-intrinsics/vcvth_u32_f16_1.c | 53 ++ .../aarch64/advsimd-intrinsics/vcvth_u64_f16_1.c | 23 + .../aarch64/advsimd-intrinsics/vcvtm_1.c | 33 + .../aarch64/advsimd-intrinsics/vcvtmh_s16_f16_1.c | 23 + .../aarch64/advsimd-intrinsics/vcvtmh_s32_f16_1.c | 53 ++ .../aarch64/advsimd-intrinsics/vcvtmh_s64_f16_1.c | 23 + .../aarch64/advsimd-intrinsics/vcvtmh_u16_f16_1.c | 23 + .../aarch64/advsimd-intrinsics/vcvtmh_u32_f16_1.c | 53 ++ .../aarch64/advsimd-intrinsics/vcvtmh_u64_f16_1.c | 23 + .../aarch64/advsimd-intrinsics/vcvtnh_s16_f16_1.c | 23 + .../aarch64/advsimd-intrinsics/vcvtnh_s32_f16_1.c | 53 ++ .../aarch64/advsimd-intrinsics/vcvtnh_s64_f16_1.c | 23 + .../aarch64/advsimd-intrinsics/vcvtnh_u16_f16_1.c | 23 + .../aarch64/advsimd-intrinsics/vcvtnh_u32_f16_1.c | 53 ++ .../aarch64/advsimd-intrinsics/vcvtnh_u64_f16_1.c | 23 + .../aarch64/advsimd-intrinsics/vcvtp_1.c | 33 + .../aarch64/advsimd-intrinsics/vcvtph_s16_f16_1.c | 23 + .../aarch64/advsimd-intrinsics/vcvtph_s32_f16_1.c | 53 ++ .../aarch64/advsimd-intrinsics/vcvtph_s64_f16_1.c | 23 + .../aarch64/advsimd-intrinsics/vcvtph_u16_f16_1.c | 23 + .../aarch64/advsimd-intrinsics/vcvtph_u32_f16_1.c | 53 ++ .../aarch64/advsimd-intrinsics/vcvtph_u64_f16_1.c | 23 + .../aarch64/advsimd-intrinsics/vdiv_f16_1.c | 86 ++ .../aarch64/advsimd-intrinsics/vdivh_f16_1.c | 42 + .../aarch64/advsimd-intrinsics/vdup-vmov.c | 75 ++ .../aarch64/advsimd-intrinsics/vdup_lane.c | 142 +++- .../aarch64/advsimd-intrinsics/vduph_lane.c | 137 ++++ .../gcc.target/aarch64/advsimd-intrinsics/vext.c | 30 + .../gcc.target/aarch64/advsimd-intrinsics/vfma.c | 46 +- .../aarch64/advsimd-intrinsics/vfmah_f16_1.c | 40 + .../aarch64/advsimd-intrinsics/vfmas_lane_f16_1.c | 908 +++++++++++++++++++++ .../aarch64/advsimd-intrinsics/vfmas_n_f16_1.c | 469 +++++++++++ .../aarch64/advsimd-intrinsics/vfmash_lane_f16_1.c | 143 ++++ .../gcc.target/aarch64/advsimd-intrinsics/vfms.c | 45 +- .../aarch64/advsimd-intrinsics/vfmsh_f16_1.c | 40 + .../gcc.target/aarch64/advsimd-intrinsics/vmax.c | 33 + .../aarch64/advsimd-intrinsics/vmaxh_f16_1.c | 34 + .../aarch64/advsimd-intrinsics/vmaxnm_1.c | 47 ++ .../aarch64/advsimd-intrinsics/vmaxnmh_f16_1.c | 42 + .../aarch64/advsimd-intrinsics/vmaxnmv_f16_1.c | 131 +++ .../aarch64/advsimd-intrinsics/vmaxv_f16_1.c | 131 +++ .../gcc.target/aarch64/advsimd-intrinsics/vmin.c | 37 + .../aarch64/advsimd-intrinsics/vminh_f16_1.c | 34 + .../aarch64/advsimd-intrinsics/vminnm_1.c | 51 ++ .../aarch64/advsimd-intrinsics/vminnmh_f16_1.c | 42 + .../aarch64/advsimd-intrinsics/vminnmv_f16_1.c | 131 +++ .../aarch64/advsimd-intrinsics/vminv_f16_1.c | 131 +++ .../gcc.target/aarch64/advsimd-intrinsics/vmul.c | 35 + .../aarch64/advsimd-intrinsics/vmul_lane.c | 37 + .../aarch64/advsimd-intrinsics/vmul_lane_f16_1.c | 454 +++++++++++ .../gcc.target/aarch64/advsimd-intrinsics/vmul_n.c | 32 + .../aarch64/advsimd-intrinsics/vmulh_f16_1.c | 42 + .../aarch64/advsimd-intrinsics/vmulh_lane_f16_1.c | 90 ++ .../aarch64/advsimd-intrinsics/vmulx_f16_1.c | 84 ++ .../aarch64/advsimd-intrinsics/vmulx_lane_f16_1.c | 452 ++++++++++ .../aarch64/advsimd-intrinsics/vmulx_n_f16_1.c | 177 ++++ .../aarch64/advsimd-intrinsics/vmulxh_f16_1.c | 50 ++ .../aarch64/advsimd-intrinsics/vmulxh_lane_f16_1.c | 91 +++ .../gcc.target/aarch64/advsimd-intrinsics/vneg.c | 29 + .../aarch64/advsimd-intrinsics/vnegh_f16_1.c | 39 + .../aarch64/advsimd-intrinsics/vpXXX.inc | 15 + .../gcc.target/aarch64/advsimd-intrinsics/vpadd.c | 3 + .../gcc.target/aarch64/advsimd-intrinsics/vpmax.c | 3 + .../gcc.target/aarch64/advsimd-intrinsics/vpmin.c | 3 + .../aarch64/advsimd-intrinsics/vpminmaxnm_f16_1.c | 114 +++ .../gcc.target/aarch64/advsimd-intrinsics/vrecpe.c | 125 +++ .../aarch64/advsimd-intrinsics/vrecpeh_f16_1.c | 42 + .../gcc.target/aarch64/advsimd-intrinsics/vrecps.c | 98 +++ .../aarch64/advsimd-intrinsics/vrecpsh_f16_1.c | 50 ++ .../aarch64/advsimd-intrinsics/vrecpxh_f16_1.c | 32 + .../gcc.target/aarch64/advsimd-intrinsics/vrev.c | 20 + .../gcc.target/aarch64/advsimd-intrinsics/vrnd.c | 8 + .../aarch64/advsimd-intrinsics/vrndX.inc | 20 + .../gcc.target/aarch64/advsimd-intrinsics/vrnda.c | 9 + .../aarch64/advsimd-intrinsics/vrndah_f16_1.c | 40 + .../aarch64/advsimd-intrinsics/vrndh_f16_1.c | 40 + .../aarch64/advsimd-intrinsics/vrndi_f16_1.c | 71 ++ .../aarch64/advsimd-intrinsics/vrndih_f16_1.c | 40 + .../gcc.target/aarch64/advsimd-intrinsics/vrndm.c | 9 + .../aarch64/advsimd-intrinsics/vrndmh_f16_1.c | 40 + .../gcc.target/aarch64/advsimd-intrinsics/vrndn.c | 9 + .../aarch64/advsimd-intrinsics/vrndnh_f16_1.c | 40 + .../gcc.target/aarch64/advsimd-intrinsics/vrndp.c | 8 + .../aarch64/advsimd-intrinsics/vrndph_f16_1.c | 40 + .../gcc.target/aarch64/advsimd-intrinsics/vrndx.c | 8 + .../aarch64/advsimd-intrinsics/vrndxh_f16_1.c | 40 + .../aarch64/advsimd-intrinsics/vrsqrte.c | 91 +++ .../aarch64/advsimd-intrinsics/vrsqrteh_f16_1.c | 30 + .../aarch64/advsimd-intrinsics/vrsqrts.c | 97 +++ .../aarch64/advsimd-intrinsics/vrsqrtsh_f16_1.c | 50 ++ .../aarch64/advsimd-intrinsics/vshuffle.inc | 42 +- .../aarch64/advsimd-intrinsics/vsqrt_f16_1.c | 72 ++ .../aarch64/advsimd-intrinsics/vsqrth_f16_1.c | 40 + .../gcc.target/aarch64/advsimd-intrinsics/vsub.c | 31 + .../aarch64/advsimd-intrinsics/vsubh_f16_1.c | 42 + .../gcc.target/aarch64/advsimd-intrinsics/vtrn.c | 20 + .../aarch64/advsimd-intrinsics/vtrn_half.c | 263 ++++++ .../gcc.target/aarch64/advsimd-intrinsics/vuzp.c | 20 + .../aarch64/advsimd-intrinsics/vuzp_half.c | 259 ++++++ .../gcc.target/aarch64/advsimd-intrinsics/vzip.c | 20 + .../aarch64/advsimd-intrinsics/vzip_half.c | 263 ++++++ .../gcc.target/arm/armv8_2-fp16-arith-1.c | 105 +++ gcc/testsuite/gcc.target/arm/armv8_2-fp16-conv-1.c | 101 +++ gcc/testsuite/gcc.target/arm/armv8_2-fp16-move-1.c | 165 ++++ gcc/testsuite/gcc.target/arm/armv8_2-fp16-neon-1.c | 490 +++++++++++ .../gcc.target/arm/armv8_2-fp16-scalar-1.c | 203 +++++ .../gcc.target/arm/armv8_2-fp16-scalar-2.c | 71 ++ gcc/testsuite/gcc.target/arm/attr-fp16-arith-1.c | 58 ++ gcc/testsuite/gcc.target/arm/fp16-aapcs-1.c | 6 +- gcc/testsuite/gcc.target/arm/fp16-compile-alt-1.c | 1 + gcc/testsuite/gcc.target/arm/fp16-compile-alt-10.c | 1 + gcc/testsuite/gcc.target/arm/fp16-compile-alt-11.c | 1 + gcc/testsuite/gcc.target/arm/fp16-compile-alt-12.c | 1 + gcc/testsuite/gcc.target/arm/fp16-compile-alt-2.c | 1 + gcc/testsuite/gcc.target/arm/fp16-compile-alt-3.c | 1 + gcc/testsuite/gcc.target/arm/fp16-compile-alt-4.c | 1 + gcc/testsuite/gcc.target/arm/fp16-compile-alt-5.c | 1 + gcc/testsuite/gcc.target/arm/fp16-compile-alt-6.c | 1 + gcc/testsuite/gcc.target/arm/fp16-compile-alt-7.c | 1 + gcc/testsuite/gcc.target/arm/fp16-compile-alt-8.c | 1 + gcc/testsuite/gcc.target/arm/fp16-compile-alt-9.c | 1 + gcc/testsuite/gcc.target/arm/fp16-compile-none-1.c | 1 + gcc/testsuite/gcc.target/arm/fp16-compile-none-2.c | 1 + gcc/testsuite/gcc.target/arm/fp16-rounding-alt-1.c | 1 + gcc/testsuite/gcc.target/arm/short-vfp-1.c | 45 + gcc/testsuite/lib/target-supports.exp | 227 ++++++ 230 files changed, 15631 insertions(+), 300 deletions(-) create mode 100644 gcc/config/arm/arm_fp16.h create mode 100644 gcc/config/arm/arm_vfp_builtins.def create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_op_f [...] create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_scal [...] create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/cmp_zero_op.inc create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ternary_sca [...] create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/unary_scala [...] create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabdh_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabsh_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddh_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcageh_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcagth_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcaleh_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcalth_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqh_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqz_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqzh_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgeh_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgez_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgezh_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgth_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgtz_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcgtzh_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcleh_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclez_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclezh_f16_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vclth_f16_1.c create mode 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