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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-next-allyesconfig in repository toolchain/ci/llvm-project.
from 09468a91482 [RISCV] Sign extend constant arguments to V intrinsics when [...] adds 2af2f58ec09 [InstCombine] Regenerate test checks (NFC) adds 9c978dd6e12 [TableGen] Fix D90844 introduced non-determinism due to ite [...] adds 69c8d121f7f [RISCV] Add intrinsics for vsetvli instruction adds 08c4b4054b3 Rename files with same (case insensitive) name adds d4ed253d0b8 [RISCV] Assume no-op addrspacecasts by default adds b4c63ef6dd9 [c++20] Mark class type NTTPs as done and start defining th [...] adds 939ba0b501b Add tests for the absence of feature test macros for featur [...] adds 72d8f79f0c3 [c++2b] Add tests for feature test macros. adds ed13d8c6678 Fix memory leak complicated non-type template arguments. adds 37d0dda739a [SLP] fix typo; NFC adds 7948cd11d17 [RISCV] Address clang-tidy warnings in RISCVTargetMachine. NFC. adds f5cef870d11 [www] Remove '$Date$' marker from cxx_dr_status. adds adc55b5a5ae [X86] Avoid generating invalid R_X86_64_GOTPCRELX relocations adds b0615642f64 [clangd] Make our printing policies for Hover more consiste [...] adds af83b74dc2e [VE] Support copy of vector mask registers adds ffd982f7db5 [ObjC][ARC] Fix a bug where the inline-asm retain/claim RV [...] adds 2fced5a07b4 [clangd] Don't cancel requests based on "updates" with same [...] adds 1ab4db0f847 [HotColdSplit] Reflect full cost of parameters in split penalty adds 2b62e623288 [clangd] Fix windows path handling in .clang-tidy parsing adds 44f399ccc12 [FileCheck] Add a literal check directive modifier adds bf0870d8640 [flang] Fix bug in IMPLICIT NONE(EXTERNAL) adds a913a583f00 [lldb] Simplify the is_finalized logic in process and make [...] adds 805d59593f5 [Analysis, CodeGen, IR] Use contains (NFC) adds 195f44278c4 [ARM] Implement harden-sls-retbr for ARM mode adds c061cb521b9 [gn build] Port 195f44278c4 adds 320fd3314e3 [ARM] Implement harden-sls-retbr for Thumb mode adds a4c1f5160e6 [ARM] Harden indirect calls against SLS adds df8ed392837 [ARM] harden-sls-blr: avoid r12 and lr in indirect calls. adds 9c895aea118 [ARM] Add clang command line support for -mharden-sls= adds 9cf3b1b6665 [RISCV] Define vlxe/vsxe/vsuxe intrinsics. adds 5740f96d8ee [NFC][libc++] Fixes swapped comments. adds 1e785e92624 apply update_test_checks.py to a few files in llvm/test/Tra [...] adds 56edfcada90 [Target, Transforms] Use contains (NFC) adds a6516a820d3 [Analysis] Remove dead function getInstTypePair (NFC) adds f47b07315a3 [X86] Teach assembler to accept vmsave/vmload/vmrun/invlpga [...] adds c52bcf3a9b2 [IRSim][IROutliner] Limit to extracting regions that only r [...]
No new revisions were added by this update.
Summary of changes: clang-tools-extra/clangd/Hover.cpp | 107 +- clang-tools-extra/clangd/TUScheduler.cpp | 63 +- clang-tools-extra/clangd/TidyProvider.cpp | 11 +- clang-tools-extra/clangd/unittests/HoverTests.cpp | 12 +- .../clangd/unittests/TUSchedulerTests.cpp | 32 + clang/include/clang/AST/ASTContext.h | 4 +- clang/include/clang/Basic/DiagnosticDriverKinds.td | 2 + clang/lib/AST/TemplateBase.cpp | 1 + clang/lib/Driver/ToolChains/Arch/ARM.cpp | 45 + clang/lib/Driver/ToolChains/Arch/ARM.h | 1 + clang/lib/Frontend/InitPreprocessor.cpp | 2 +- clang/test/Driver/aarch64-sls-hardening-options.c | 45 - clang/test/Driver/sls-hardening-options.c | 97 + clang/test/Lexer/cxx-features.cpp | 170 +- clang/www/cxx_dr_status.html | 1 - clang/www/cxx_status.html | 2 +- clang/www/make_cxx_dr_status | 1 - flang/lib/Semantics/resolve-names.cpp | 19 +- flang/test/Semantics/implicit07.f90 | 3 + .../libcxx/iterators/trivial_iterators.pass.cpp | 4 +- lld/test/ELF/x86-64-gotpc-relax-nopic.s | 4 +- lldb/include/lldb/Target/Process.h | 13 +- lldb/source/Target/Process.cpp | 21 +- llvm/docs/CommandGuide/FileCheck.rst | 24 + llvm/include/llvm/FileCheck/FileCheck.h | 25 +- llvm/include/llvm/IR/IntrinsicsRISCV.td | 58 +- llvm/include/llvm/Transforms/IPO/IROutliner.h | 22 +- llvm/lib/Analysis/BranchProbabilityInfo.cpp | 3 +- llvm/lib/Analysis/DivergenceAnalysis.cpp | 6 +- llvm/lib/Analysis/IRSimilarityIdentifier.cpp | 10 +- llvm/lib/Analysis/MemDepPrinter.cpp | 3 - .../CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp | 2 +- llvm/lib/FileCheck/FileCheck.cpp | 118 +- llvm/lib/IR/ModuleSummaryIndex.cpp | 2 +- llvm/lib/Target/ARM/ARM.h | 3 + llvm/lib/Target/ARM/ARM.td | 14 + llvm/lib/Target/ARM/ARMAsmPrinter.cpp | 42 + llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 51 +- llvm/lib/Target/ARM/ARMBaseInstrInfo.h | 65 + llvm/lib/Target/ARM/ARMCallLowering.cpp | 9 +- llvm/lib/Target/ARM/ARMConstantIslandPass.cpp | 11 + llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp | 5 +- llvm/lib/Target/ARM/ARMFastISel.cpp | 14 +- llvm/lib/Target/ARM/ARMFeatures.h | 1 + llvm/lib/Target/ARM/ARMISelLowering.cpp | 2 +- llvm/lib/Target/ARM/ARMInstrInfo.td | 35 +- llvm/lib/Target/ARM/ARMInstrThumb.td | 13 +- llvm/lib/Target/ARM/ARMInstrThumb2.td | 9 + llvm/lib/Target/ARM/ARMPredicates.td | 3 + llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp | 12 +- llvm/lib/Target/ARM/ARMRegisterInfo.td | 17 + llvm/lib/Target/ARM/ARMSLSHardening.cpp | 416 ++ llvm/lib/Target/ARM/ARMSubtarget.h | 10 + llvm/lib/Target/ARM/ARMTargetMachine.cpp | 4 + llvm/lib/Target/ARM/CMakeLists.txt | 1 + llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp | 2 +- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 65 + llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td | 198 + llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 21 +- llvm/lib/Target/RISCV/RISCVTargetMachine.h | 5 +- llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp | 2 + llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h | 3 +- llvm/lib/Target/VE/VEInstrInfo.cpp | 15 + .../Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp | 13 +- llvm/lib/Target/X86/X86InstrSVM.td | 28 +- llvm/lib/Transforms/IPO/HotColdSplitting.cpp | 61 +- llvm/lib/Transforms/IPO/IROutliner.cpp | 226 +- llvm/lib/Transforms/ObjCARC/ObjCARCContract.cpp | 2 +- .../lib/Transforms/Scalar/DeadStoreElimination.cpp | 3 +- llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 6 +- llvm/test/CodeGen/ARM/O3-pipeline.ll | 4 + llvm/test/CodeGen/ARM/speculation-hardening-sls.ll | 246 + llvm/test/CodeGen/RISCV/addrspacecast.ll | 49 + .../CodeGen/RISCV/rvv/rv32-vsetvli-intrinsics.ll | 33 + .../CodeGen/RISCV/rvv/rv64-vsetvli-intrinsics.ll | 51 + llvm/test/CodeGen/RISCV/rvv/vlxe-rv32.ll | 3281 ++++++++++++ llvm/test/CodeGen/RISCV/rvv/vlxe-rv64.ll | 5361 +++++++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vsuxe-rv32.ll | 3445 ++++++++++++ llvm/test/CodeGen/RISCV/rvv/vsuxe-rv64.ll | 5629 ++++++++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vsxe-rv32.ll | 3445 ++++++++++++ llvm/test/CodeGen/RISCV/rvv/vsxe-rv64.ll | 5629 ++++++++++++++++++++ llvm/test/CodeGen/VE/Vector/fastcc_callee.ll | 17 + .../{dimodule.ll => dimodule-external-fortran.ll} | 0 llvm/test/FileCheck/check-literal.txt | 62 + llvm/test/MC/Disassembler/X86/simple-tests.txt | 10 +- llvm/test/MC/ELF/got-relaxed-rex.s | 36 - llvm/test/MC/X86/SVM-32.s | 30 +- llvm/test/MC/X86/SVM-64.s | 30 +- llvm/test/MC/X86/gotpcrelx.s | 65 + llvm/test/MC/X86/x86-32-coverage.s | 10 +- llvm/test/MC/X86/x86-32.s | 10 +- .../Transforms/CodeExtractor/extract-assume.ll | 2 +- .../HotColdSplit/apply-penalty-for-inputs.ll | 21 +- .../HotColdSplit/apply-penalty-for-outputs.ll | 8 +- .../HotColdSplit/apply-successor-penalty.ll | 13 +- .../HotColdSplit/assumption-cache-invalidation.ll | 7 +- llvm/test/Transforms/IROutliner/extraction.ll | 46 +- llvm/test/Transforms/IROutliner/illegal-assumes.ll | 22 +- llvm/test/Transforms/IROutliner/illegal-memcpy.ll | 40 +- llvm/test/Transforms/IROutliner/illegal-memmove.ll | 40 +- llvm/test/Transforms/IROutliner/illegal-vaarg.ll | 30 +- .../IROutliner/outlining-constants-vs-registers.ll | 78 + ...ructure.ll => outlining-different-constants.ll} | 28 +- .../IROutliner/outlining-different-globals.ll | 40 + .../IROutliner/outlining-different-structure.ll | 6 - .../IROutliner/outlining-same-constants.ll | 9 - llvm/test/Transforms/InstCombine/CPP_min_max.ll | 54 +- llvm/test/Transforms/InstCombine/X86/x86-sse4a.ll | 18 +- llvm/test/Transforms/InstCombine/bitcast.ll | 12 +- .../test/Transforms/InstCombine/clamp-to-minmax.ll | 102 +- .../Transforms/InstCombine/insert-const-shuf.ll | 20 +- llvm/test/Transforms/InstCombine/minmax-fp.ll | 68 +- llvm/test/Transforms/InstCombine/pr21199.ll | 19 +- .../Transforms/InstCombine/preserve-sminmax.ll | 24 +- llvm/test/Transforms/InstCombine/smax-icmp.ll | 48 +- llvm/test/Transforms/InstCombine/smin-icmp.ll | 48 +- llvm/test/Transforms/InstCombine/umax-icmp.ll | 48 +- llvm/test/Transforms/InstCombine/umin-icmp.ll | 48 +- llvm/test/Transforms/ObjCARC/contract-marker.ll | 20 + .../tools/llvm-mca/X86/Atom/resources-x86_64.s | 4 +- .../llvm-mca/X86/Barcelona/resources-x86_64.s | 4 +- .../tools/llvm-mca/X86/BdVer2/resources-x86_64.s | 4 +- .../llvm-mca/X86/Broadwell/resources-x86_64.s | 4 +- .../tools/llvm-mca/X86/BtVer2/resources-x86_64.s | 4 +- .../tools/llvm-mca/X86/Generic/resources-x86_64.s | 4 +- .../tools/llvm-mca/X86/Haswell/resources-x86_64.s | 4 +- .../test/tools/llvm-mca/X86/SLM/resources-x86_64.s | 4 +- .../llvm-mca/X86/SandyBridge/resources-x86_64.s | 4 +- .../llvm-mca/X86/SkylakeClient/resources-x86_64.s | 4 +- .../llvm-mca/X86/SkylakeServer/resources-x86_64.s | 4 +- .../tools/llvm-mca/X86/Znver1/resources-x86_64.s | 4 +- .../tools/llvm-mca/X86/Znver2/resources-x86_64.s | 4 +- llvm/utils/TableGen/CodeGenSchedule.cpp | 3 + llvm/utils/TableGen/CodeGenSchedule.h | 2 +- .../gn/secondary/llvm/lib/Target/ARM/BUILD.gn | 1 + 135 files changed, 29881 insertions(+), 859 deletions(-) delete mode 100644 clang/test/Driver/aarch64-sls-hardening-options.c create mode 100644 clang/test/Driver/sls-hardening-options.c create mode 100644 llvm/lib/Target/ARM/ARMSLSHardening.cpp create mode 100644 llvm/test/CodeGen/ARM/speculation-hardening-sls.ll create mode 100644 llvm/test/CodeGen/RISCV/addrspacecast.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/rv32-vsetvli-intrinsics.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/rv64-vsetvli-intrinsics.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vlxe-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vlxe-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vsuxe-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vsuxe-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vsxe-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vsxe-rv64.ll rename llvm/test/DebugInfo/X86/{dimodule.ll => dimodule-external-fortran.ll} (100%) create mode 100644 llvm/test/FileCheck/check-literal.txt delete mode 100644 llvm/test/MC/ELF/got-relaxed-rex.s create mode 100644 llvm/test/Transforms/IROutliner/outlining-constants-vs-registers.ll copy llvm/test/Transforms/IROutliner/{outlining-different-structure.ll => outlinin [...] create mode 100644 llvm/test/Transforms/IROutliner/outlining-different-globals.ll