[Tcwg-commits] [gcc] branch devel/rust/master updated (74913f718b0 -> e23e7f14a51)

This is an automated email from the git hooks/post-receive script.

unknown user pushed a change to branch devel/rust/master in repository gcc.

from 74913f718b0 Fix up DejaGnu directives in 'rust/compile/issue-1830_{byte [...] new 1bd1e466453 rename rust-hir-full-tests.cc new 332b8abe758 gccrs: add test case to show our query-type system is working new e9957814406 ast: Refactor TraitItem to keep Location info new 5752164328f diagnostic: Refactor Error class new 1774ff486a3 Added AST Node AST::InlineAsm new 0f736eb6259 Address unsafe with/without block handling ambiguity new 3448f0fa239 Fix issue with parsing unsafe block expression statements adds 7f583a33576 modula2/108462 - duplicate install of static modula2 target libs adds 99fda5de368 Properly set GORI relation trios. adds 809d661aff9 Utilize op1 == op2 when invoking range-ops folding. adds 1626ec53e8c Add op2_range to pointer_plus. adds 2bb444787ed vect: Fix single def-use cycle for ifn reductions [PR108608] adds a39c6ec9790 PR target/108589 - Check REG_P for AARCH64_FUSE_ADDSUB_2REG_CONST1 adds 623730d954a c++: fix ICE with -Wduplicated-cond [PR107593] adds 2a937fb5cf8 RISC-V: Add integer binary vv C/C++ API support adds 2db1fd76eba RISC-V: Add vxor.vv C API tests adds 88a4dc078ad RISC-V: Add vsub.vv C API tests adds 4703a573d11 RISC-V: Add srl.vv C API tests adds 79d1e60cb86 RISC-V: Add vsra.vv C API tests adds f9979ac8a2c RISC-V: Add vsll.vv C API tests adds 9d2fe103bfb RISC-V: Add vrem*.vv C API tests adds a581639528a RISC-V: Add vor.vv C API tests adds 7f51e62876c RISC-V: Add vmin*.vv C API tests adds aa89ce6a65a RISC-V: Add vmax*.vv C API tests adds a542b1feeb2 RISC-V: Add vdiv*.vv C API tests adds 817d8f2ec5a RISC-V: Add vand.vv C API tests adds c2674f5b913 RISC-V: Add vadd.vv C API tests adds e96482d84ec RISC-V: Add binop constraint tests adds 6344011ae32 RISC-V: Add vadd.vv C++ API tests adds e37c8f209e0 RISC-V: Add vxor.vv C++ API tests adds 768a8952539 RISC-V: Add vand.vv C++ API tests adds f4463ea86a4 RISC-V: Add vsrl.vv C++ API tests adds 38e152f84b0 RISC-V: Add vsra.vv C++ API tests adds 147e602a4dd RISC-V: Add vsll.vv C++ API tests adds f4f00e44fd3 RISC-V: Add vrem*.vv C++ API tests adds b928748686f RISC-V: Add vor.vv C++ API tests adds e2e93b9dee9 RISC-V: Add vmin*.vv C++ API tests adds a97767c30b1 RISC-V: Add vmax*.vv C++ API tests adds 77906341efc RISC-V: Add vdiv*.vv C++ API tests adds b2ec2504af7 c++: Add fixed test [PR102870] adds 94cacee20d8 For Modula-2 build-tree testing, also set up paths to compi [...] adds a9fbc6687fa libsanitizer: cherry-pick commit 742bcbf685bc from upstream adds b533084d756 c++: aggregate base and TARGET_EXPR_ELIDING_P [PR108559] adds 317525b03eb Daily bump. adds a90316c6ced doc: add notes about limitations of -fanalyzer adds 70d34f2a30a analyzer: fix -Wanalyzer-allocation-size false -ve on alloc [...] adds d03ae4be2c6 analyzer: fix uses of alloca in testsuite adds e2f939d30f5 c++: Add -Wno-changes-meaning adds 97258480438 middle-end/108500 - replace recursive domtree DFS traversal adds ef5f7b89bbc New reg note REG_CFA_NORESTORE adds 36ffb2e0293 IBM zSystems: Make stack_tie to work with hard frame pointer adds 8091199cdf4 IBM zSystems: Save argument registers to the stack -mpreserve-args adds bfc070595bf c++, openmp: Handle some OMP_*/OACC_* constructs during con [...] adds f3b1af49702 testsuite: Fix g++.dg/gomp warnings for aarch64 adds 3cef9dca57b compare-elim: Fix an RTL checking failure adds eda38850a79 libgomp.texi: Reverse-offload updates adds e4473d7cf87 ree: Fix -fcompare-debug issues in combine_reaching_defs [P [...] adds 1d77bfdf11f driver: fix -gz=none error message with missing zstd adds 5ce8961b46f c++: ICE with -Wlogical-op [PR107755] adds bf2cf6f3f18 Fortran: Extend align-clause checks of OpenMP's allocate directive adds 78589691ee1 ipa: check if cache_token != NULL before hash_set::add call adds 881bf8de9b0 Ranger cache - always use range_from_dom when updating. adds 8a7196977f6 ipa: silent -Wodr notes with -w adds dbc4db7e824 testsuite: Run __bos tests to completion adds a939dd83579 libstdc++ testsuite: Correct S0 in std/time/hh_mm_ss/1.cc adds 9fadd8dec79 Fixup noreturn attributes in modula-2 [PR108551] and [PR108612] adds a2c848c92c3 AArch64: Fix native detection in the presence of mandatory [...] adds 88a2a09dd45 Fortran: error recovery on invalid array section [PR108609] adds 7314558c938 libstdc++: Do not embed tzdata.zi for 8-bit and 16-bit targets adds 2d2e163d12f libstdc++: Fix build failures for avr adds 277dd6ea416 libstdc++: Fix std::random_device for avr adds 0a251e74976 Daily bump. adds d95e72b9c48 libstdc++: Fix link to online GDB manual adds 66d700af5bb libstdc++: Switch a www.open-std.org link to https adds 0f349928e16 nested, openmp: Wrap OMP_CLAUSE_*_GIMPLE_SEQ into GIMPLE_BI [...] adds 209f02b0a9e Don't peel nonlinear iv(mult or shift) for epilog when vf i [...] adds d2423144eb3 Replace IFN_TRAP with BUILT_IN_UNREACHABLE_TRAP [PR107300] adds 75b58e77706 arm: Fix sign of MVE predicate mve_pred16_t [PR 107674] adds d45ec8a732f arm: Remove unnecessary zero-extending of MVE predicates be [...] adds e0bc13d3960 arm: Fix MVE predicates synthesis [PR 108443] adds 8da7476c5fa libgomp.texi (OpenMP TR11 impl. status): Fix 'strict' item adds f6fff8a6fcd amdgcn, libgomp: Manually allocated stacks adds 605d1297b91 middle-end/108625 - wrong folding due to misinterpreted ! adds 465a9c51e7d sched-deps, cselib: Fix up some -fcompare-debug issues and [...] adds a02aacf55a3 RISC-V: Fix bug of TARGET_COMPUTE_MULTILIB implemented in riscv. adds 598e10cf415 analyzer: add deref-before-check-qemu-qtest_rsp_args.c test case adds d84dc419e69 analyzer: fix -Wanalyzer-fd-type-mismatch false +ve on "lis [...] adds 5b7b9d2da76 testsuite: Add case-values-threshold to pr107876.C adds f4e1b46618e rtl-ssa: Fix splitting of clobber groups [PR108508] adds cd41085a37b rtl-ssa: Extend m_num_defs to a full unsigned int [PR108086] adds 9c7e898bbd6 amdgcn: Add instruction pattern for conditional shift operations adds f25dd779d44 driver, toplevel: Avoid emitting the version information twice. adds 1395415fdc2 libstdc++: Use emplace in std::variant::operator=(T&&) as p [...] adds db8d6fc572e libstdc++: Fix std::filesystem errors with -fkeep-inline-fu [...] adds 331b4f168a0 libstdc++: Define std::basic_stringbuf::view() for old std: [...] adds 5c43f06c228 libstdc++: Use ENOSYS for unsupported filesystem ops on AVR adds 66337ff8a44 c: Update checks on constexpr floating-point initializers adds 07c87fce635 libstdc++: Tweak link to ABIcheck project adds 0b8693fc87b c: Update nullptr_t comparison checks adds a37a0cb303d Daily bump. adds 61122017132 RISC-V: Add RVV shift.vx C/C++ API support adds fae260ebfb1 RISC-V: Add vsrl.vx C API tests adds f890b9e76f9 RISC-V: Add vsra.vx C API tests adds 07fba8d6f2d RISC-V: Add vsll.vx C++ API tests adds 6c93c1fb396 RISC-V: Add shift constraint tests adds b0a2abcd79e RISC-V: Add vsrl.vx C++ API tests adds f08acad732e RISC-V: Add vsra.vx C++ API tests adds d8bd2c5f22e RISC-V: Add vsll.vx C++ API tests adds f3a10f4fff3 RISC-V: Fix constraint bug for binary operation adds 167b04b9b8a RISC-V: Remove unnecessary register class. adds f84fdb134de libgomp: enable reverse offload for AMDGCN adds 0b1ce70a813 libgomp: Fix reverse offload issues adds e8109bd8776 ipa: Avoid invalid gimple when IPA-CP and IPA-SRA disagree [...] adds e7930c6750d c++: excessive satisfaction in check_methods [PR108579] adds ed2b519e02e c++: ICE on unviable/ambiguous constrained dtors [PR96745] adds 59e0376f607 c++: unexpected ADDR_EXPR after overload set pruning [PR107461] adds 3dba5b2cf2d arm: Fix warning in libgcc/config/arm/pr-support.c adds 330d665ce6d arm: [MVE] Add missing length=8 attribute adds 6716822c541 libstdc++: Implement ranges::contains/contains_subrange fro [...] adds 28752bcbbfb libstdc++: Implement ranges::iota from P2440R1 adds c9aef107ce6 libstdc++: Implement ranges::find_last{,_if,_if_not} from P1223R5 adds 8d2c5b61014 [modula-2] Bugfix to allow html doc build and simplify targ [...] adds f0065f207cf libstdc++: Mark pieces of gnu-linux/os_support.h linux-specific adds 60fca1802a2 c++: Add fixed test [PR101071] adds 27ac6a707e7 c++: wrong error with constexpr array and value-init [PR108158] adds 093e2e1b201 Reset SCEV before removing unreachable globals. adds 10bd26d6efe range-ops: Handle undefined ranges in frange op[12]_range [ [...] adds e261fcefb71 irange: Compare nonzero bits in irange with widest_int [PR108639] adds 76f7f0eddcb fortran: Fix up hash table usage in gfc_trans_use_stmts [PR108451] adds e753080ab8a range-op: Handle op?.undefined_p () in op[12]_range of comp [...] adds 49e52115b09 Daily bump. adds 540a22d2439 libstdc++: Optimize basic_string move assignment adds 08fde093cab libstdc++: Adjust link to pdftex adds 72058eea9d4 libstdc++: Avoid use of naked int32_t in unseq_backend_simd [...] adds 057eb31bc32 Daily bump. adds f1a4c63c2f7 doc: Remove note on PW32 adds d042f118798 Fortran: prevent redundant integer division truncation warn [...] adds e4421a770d4 Daily bump. adds 31924665c86 c++: equivalence of non-dependent calls [PR107461] adds 5df573f76bb ubsan: Fix up another spot that should have been BUILT_IN_U [...] adds c490c7c0ef3 testsuite: remove broken AArch64 test adds 5ebfd7ba2f6 LoongArch: Generate bytepick.[wd] for suitable bit operatio [...] adds 4a910708fa2 ipa-sra: Fix a typo in a dump string. adds fb8e29a5fd9 libstdc++: Disable building additional archives for freestanding adds abdea447250 libstdc++: Enable building libstdc++.{a,so} when !HOSTED adds 4f49ae607cb libstdc++: Normalise _GLIBCXX20_DEPRECATED macro adds aa02a69e15d libstdc++: Implement P1413R3 'deprecate aligned_storage and [...] adds c76f55bf330 libstdc++: Fix testsuite warnings about new C++23 deprecations adds 0afcb713217 libstdc++: Fix non-reserved name for template parameter adds 277e1f30a5e aarch64: Fix up bfmlal lane pattern [PR104921] adds 74337475431 Remove unused variables and procedures. adds 45e01229af3 amdgcn: Pass -mstack-size through to runtime adds 17d0892d61a Format error in m2pp.cc (m2pp_integer_cst) [PR107234] adds 9f4baed6ac0 libstdc++: Document P1642 and extensions adds d5f933d2c04 Modula2 meets clang [PR108135] adds f0e73dd0311 Daily bump. adds a7502c4a614 Enable 512 bit vector for zen4 adds 64b5ca4345f testsuite: Expect -Wdeprecated warning in warn/Wstrict-alia [...] adds cad2412cc84 cgraph: Handle simd clones in cgraph_node::set_{const,pure} [...] adds 5321d53279a ipa-split: Don't split returns_twice functions [PR106923] adds 295adfc9ed2 tree-optimization/26854 - compile-time hog in SSA forwprop adds f661c0bb637 RA: Implement reuse of equivalent memory for caller saves o [...] adds 8bc87173003 doc: Update -fchar8_t documentation adds c36f3da534e Fortran: ASSOCIATE variables should not be TREE_STATIC [PR95107] adds c300e251f5b analyzer: fix -Wanalyzer-use-of-uninitialized-value false + [...] adds 7ab75a6e6df Fix 'libgomp.fortran/reverse-offload-6.f90' nvptx offloadin [...] adds 8f3b85efbf5 Daily bump. adds aa12d1b17c4 tree.def: Remove outdated comment on SAD_EXPR adds a58a4a57f9a testsuite: Fix up PR108525 test [PR108525] adds ad2bd0ad041 Revert "RA: Implement reuse of equivalent memory for caller [...] adds 740a3be7df2 vect: Check gather/scatter offset types [PR108316] adds 3d451c4228c testsuite: Import objc-dg-prune in execute.exp adds b1d26458839 aarch64: Fix return_address_sign_ab_exception.C regression adds 6ad1c102762 vect-patterns: Fix up vect_widened_op_tree [PR108692] adds 7e9f20f5517 Fortran: error handling of global entity appearing in COMMO [...] adds 2eeda82d628 arm: Optimize arm-mlib.h header inclusion [pr108505]. adds 77bb54b1b07 analyzer: fix overzealous state purging with on-stack struc [...] adds 70888d0982d testsuite: Fix asm-goto-with-outputs tests; limit to lra targets adds 1a49390f3f6 doc: Change fsf.org to www.fsf.org adds 53678f7f794 c: Update checks on constexpr pointer initializers adds f6fc79d0c90 Daily bump. adds 4b19ff1b5ef tree-optimization/26854 - slow bitmap operations adds b1ed0c9671b c++: Mangle EXCESS_PRECISION_EXPR <REAL_CST> as fold_conver [...] adds 9453e3cd0ff lto-wrapper: Pass through -funwind-tables and -fasynchronou [...] adds ae091a44f6a Fortran/OpenMP: Fix -fopenmp-simd for 'omp assume(s)' adds 1eb78a935aa OpenMP: Parse align clause in allocate directive in C/C++ adds 1189d1b38e2 docs: add caveat for __builtin_cpu_supports adds ac2949574da OpenMP/Fortran: Partially fix non-rect loop nests [PR107424] adds 44f308e59bf match.pd: When simplifying BFR of an insert, require a mode [...] adds bcca64d70ce match.pd: Simplify BFR of insert when extracting exactly al [...] adds b24e9c08309 i386: Call get_available_features for all CPUs with max_lev [...] adds a618b45ac41 Fortran: catch invalid kind in character conversion [PR6963 [...] adds 10827a92f1a RA: Implement reuse of equivalent memory for caller saves o [...] adds 125b57aa674 analyzer: fix further overzealous state purging [PR108733] adds 67b82bc1b29 c++: ICE initing lifetime-extended constexpr var [PR107079] adds e92e2c9671e Daily bump. adds c47f76c16bf testsuite: XFAIL bogus g++.dg/warn/Wstringop-overflow-4.C:1 [...] adds 41015797ad1 testsuite: XFAIL g++.dg/pr71488.C and warn/Warray-bounds-16 [...] adds b9f8935e110 c: Allow conversions of null pointer constants to nullptr_t adds 6a5cb782d14 tree-optimization: [PR108684] ICE in verify_ssa due to simp [...] adds e635681dd26 Add x86_64-gnu target to contrib/config-list.mk adds 2a37a4a3cbf Revert "docs: add caveat for __builtin_cpu_supports" adds dc87e1391c5 tree-optimization/108724 - vectorized code getting piecewis [...] adds a035d133809 RISC-V: Add binary vx C/C++ support adds 649107f6d1f RISC-V: Add vmul.vv C API tests adds 1b0bd520f5a RISC-V: Add vmul.vv C++ API tests adds e9d5e4ac357 RISC-V: Add vxor.vx C API tests adds fe9e2eccb9e RISC-V: Add vsub.vx C API tests adds d2d6b0915e0 RISC-V: Add vrsub.vx C API tests adds b65e8a19002 RISC-V: Add vremu.vx C API tests adds dc4d66d543b RISC-V: Add vrem.vx C API tests adds 76cd8e80058 RISC-V: Add vor.vx C API tests adds ac843ce70e6 RISC-V: Add vmul.vx C API tests adds f82338eca2f RISC-V: Add vminu.vx C API tests adds 5255664d4ab RISC-V: Add vmin.vx C API tests adds a524f0c44f1 RISC-V: Add vmaxu.vx C API tests adds e6a085499cb RISC-V: Add vmax.vx C API tests adds 8f1320e0976 RISC-V: Add vdivu C API tests adds 5442df6cbdf RISC-V: Add vdiv.vx C API tests adds 9f35eb5d51b RISC-V: Add vand.vx C API tests adds f7bff05f5e9 RISC-V: Add vadd.vx C API tests adds ce4b00f393b RISC-V: Add binary op vx constraint tests adds 7d8c4a59fdf RISC-V: Add vxor.vx C++ API tests adds 525274d82f3 RISC-V: Add vsub.vx C++ API tests adds f0cd94672fc RISC-V: Add vrsub.vx C++ API tests adds 1e6324f7f36 RISC-V: Add vadd.vx C++ API tests adds d862fd1832a RISC-V: Add vremu.vx C++ API tests. adds 988cc529af6 RISC-V: Add vrem.vx C++ API tests adds 6289b83ffe2 RISC-V: Add vor.vx C++ API tests adds 8c971d59a7c RISC-V: Add vmul.vx C++ API testcase adds 679ba598453 RISC-V: Add vminu.vx C++ API tests adds 0e5ae1fad00 RISC-V: Add vmin.vx C++ API tests adds 66979d72eb9 RISC-V: Add vmaxu.vx C++ API tests. adds ae3ea1340de RISC-V: Add vmax.vx C++ API tests. adds 8189380d868 RISC-V: Add vdivu.vx C++ API tests adds e0e32c3397e RISC-V: Add vdiv.vx C++ API test. adds edfc4402504 RISC-V: Add vand.vx C++ API test. adds 99f3ad2e5b1 Add function context for querying global ranges. adds 6493b7af37e Query rangers cache in readonly mode only from within adds 3c5154d0f0d RA: Use simple LRA for huge functions adds 7757567358a RA: Use caller save equivalent memory only for LRA adds 305037ee3ed Regenerate .pot files adds aa601e30758 analyzer: don't warn for deref-before-check for checks in m [...] adds d7a47ed17ad Daily bump. adds e2bb55ec3b7 libiberty: fix lrealpath on Windows NTFS symlinks adds d651736e10c libstdc++: Update link to "Worst-case efficient priority queues" adds 76ab4084d03 gcc/testsuite: fix excess warnings for mingw-w64 adds 391f29e60a9 pr65658.c: fix excess warnings on LLP64 targets adds d1bf1c9771d doc: Adjust link to WG14 N965 adds 00a49047b50 ipa-cp: Punt for too large offsets [PR108605] adds ee117887838 Daily bump. adds c129d22de6b RISC-V: Fix VSETVL PASS bug in exception handling adds d7f8c79a57e RISC-V: Add unary C/C++ API support adds 2855e295484 RISC-V: Add vnot.v C API tests adds 340a770d9dc RISC-V: Add vneg.v C/C++ API tests adds 779e441103e RISC-V: Add unary constraint tests. adds 4170a0f021f RISC-V: Add vnot.v C++ API tests adds eeb50b70354 RISC-V: Add vneg.v C++ API tests adds 7ad729a0df0 RISC-V: Add saturating Addition && Subtraction C/C++ Support adds b2691c96efd RISC-V: Add saturating Add && Sub vx constraint tests adds 098e7fc10e4 RISC-V: Add vsadd.vv C++ API tests adds 77c9ee5e22e RISC-V: Add vsaddu.vv C++ API tests. adds cc01b5c0659 RISC-V: Add vsub.vv C++ API tests adds ae9b600f2d5 RISC-V: Add vssubu.vv C++ API tests adds cd92bd48c55 RISC-V: Add vssubu.vv C API tests adds bd182ae41bc RISC-V: Add vssub.vv C API tests adds e5600572a17 RISC-V: Add vsaddu.vv C API tests adds 6a04629d5a0 RISC-V: Add vsadd.vv C API tests adds d6c18465cbb RISC-V: Add vssubu.vx C API tests adds 1b7f3e20a2f RISC-V: Add vssub.vx C API tests adds ed0c99027d4 RISC-V: Add vsaddu.vx C++ API tests adds 933dce55100 RISC-V: Add vsadd.vx C++ API tests adds e5dd529dcdb RISC-V: Add vssubu.vx C++ API tests adds 3762ff2450c RISC-V: Add vssub.vx C++ API tests adds a1ca758fd5e RISC-V: Add vsaddu.vx overloaded API tests adds 064a2d53a38 RISC-V: Add vsadd.vx C++ overloaded API tests adds 99fa5d94c41 RISC-V: Add vsext/vzext C/C++ intrinsic support adds a2da134248b RISC-V: Add vzext.vf8 C API tests adds 1d66166b0f7 RISC-V: Add vzext.vf4 C API tests adds 91d0120e389 RISC-V: Add vzext.vf2 C API tests adds decfa1d5bc5 RISC-V: Add vsext.vf8 C API tests adds 42666defc0d RISC-V: Add vsext.vf4 C API tests adds 7d2c4a6f07e RISC-V: Add vsext.vf2 C API tests adds 00c93929571 RISC-V: Add vsext constraint tests adds 221f26c9624 RISC-V: Add vzext.vf8 C++ API tests adds 522d385831b RISC-V: Add vzext.vf4 C++ API tests adds 921f11c8cc2 RISC-V: Add vzext.vf2 C++ API tests adds 74595dd5181 RISC-V: Add vsext C++ API tests adds 8340bbad6a1 RISC-V: Add vmulh C/C++ support adds 87c557e2696 RISC-V: Add vmulhu.vx C API tests adds ce756a1392b RISC-V: Add vmulhu.vv C API tests adds f95ada62f3f RISC-V: Add vmulhsu.vx C API tests adds 956c0c8c7dc RISC-V: Add vmulhsu.vv C API tests adds fa07f9da8b7 RISC-V: Add vmulh.vx C API tests adds 9ecdd261f72 RISC-V: Add vmulh.vv C API tests adds b9eabfee849 RISC-V: Add vmulhu.vx C++ tests adds 5a792199d80 RISC-V: Add vmulhsu.vx C++ API tests adds b81d711d189 RISC-V: Add vmulhsu.vv C++ API tests adds f18e96e6188 RISC-V: Add vmulh.vx C++ API tests adds d88110b07e7 RISC-V: Add vmulh.vv C++ API tests adds a1e42094e7a RISC-V: Add integer widening instructions adds 9aa6c67dea4 RISC-V: Add vwsubu.wx C API tests adds f98b4bc59b8 RISC-V: Add vwsubu.wx C API tests adds 9b180754891 RISC-V: Add vwsubu.vx C API tests adds 8aa1e133b12 RISC-V: Add vwsubu.vv C API tests adds 931b3d88313 RISC-V: Add vwsub.wx C API tests adds 14ac33c8e03 RISC-V: Add vwsub.wv C API tests adds 524e491ab53 RISC-V: Add vwsub.vx C API tests adds 2a2ab19d559 RISC-V: Add vwsub.vv C API tests adds fcbe69a096a RISC-V: Add vwmulu C API tests adds 697a877279b RISC-V: Add vwmulsu C API tests adds ee4f91db8ee RISC-V: Add vwmul C api tests adds 011ec88dd2b RISC-V: Add vwcvt C API test adds f14f44d92f6 RISC-V: Add vwaddu.w C API tests adds 2daeb10c609 RISC-V: Add vwaddu.v C API tests adds 7df7cbaaf5e RISC-V: Add vwadd.w C API tests adds c12ea7136ad RISC-V: Add vwadd.v C API tests adds 345b2aa4eb3 RISC-V: Add constraint tests adds 8532ae57f30 RISC-V: Add vwsubu.w C++ api TETS adds 0fca6d1ac50 RISC-V: Add vwsubu.v C++ API test adds b406b86cad2 RISC-V: Add vwsub.w C++ api TESTS adds c95bc128c05 RISC-V: Add vwsub.v C++ API tests adds ba839fb84bc RISC-V: Add vwmulu C++ API tests adds 307241cbaa9 RISC-V: Add vwmulsu.v C++ API tests adds 7d010731e8b RISC-V: Add vwmul.v C++ api TETS adds 98767d253c1 RISC-V: Add vwcvt C++ api test adds b840dad84da RISC-V: Add vwaddu.w c++ API TESTS adds 0006e578d0a RISC-V: Add vwaddu.v C++ API tests adds ccfaa507361 RISC-V: Add vwadd.w C++ API tests adds 316c83b158d RISC-V: Add vwadd v C++ api test adds 5e620b36cd3 RISC-V: allow vx instruction use "zero" as scalar register. adds cb44a16d212 RISC-V: Add vadc/vsbc C/C++ API support adds b5e7450a173 RISC-V: Add vadc.vvm/vadc.vxm C API tests adds c2f4dc58105 RISC-V: Add vsbc.vvm/vsbc.vxm C API tests adds 6483b831033 RISC-V: Add vsbc C++ API tests adds b7e4f61c3e7 RISC-V: Add vadc C++ API tests adds dca23bf0bbe RISC-V: Add vmadc/vmsbc C/C++ API support adds c8c7b4b32d8 RISC-V: Add vmadc C API tests adds bd5c5d2eaf1 RISC-V: Add vmsbc C API tests adds 485c710b4e6 RISC-V: Add vmadc C++ API tests adds 30eedd6a4fc RISC-V: Add vmsbc C++ API tests adds 6271a07219a RISC-V: Add vnsrl/vnsra/vncvt/vmerge/vmv C/C++ support adds 10e999a3abd RISC-V: Add vnsrl C API tests adds eeec45d2923 RISC-V: Add vnsra C API tests adds fb03f2acfb7 RISC-V: Add vncvt C API tests adds c1294253310 RISC-V: Add vmv C API tests adds 4852c719a1a RISC-V: Add vmv.v.x C API tests adds c0ea34be11c RISC-V: Add vmerge C API tests adds 0b7dd2f4799 RISC-V: Add vnsrl C++ API tests adds 484ea18ffae RISC-V: Add vnsra C++ API tests adds 9a1c81afd55 RISC-V: Add vncvt/vmv C++ API tests adds 79ef372fa41 RISC-V: Add vmerge C++ API test adds 4fd0cfd87b1 libstdc++: Change www.unix.org to unix.org adds e09418f21dd RISC-V: Add fixed-point support adds 71a1c2c67aa RISC-V: Add vssrl.vx C API tests adds 13907f4bd2e RISC-V: Add vssrl.vv C API tests adds 4e00937ec3e RISC-V: Add vssra.vx C API tests adds 5ca5ca30b6a RISC-V: Add vssra.vv C API tests adds bbb168daecf RISC-V: Add vsmul.vx C API tests adds c156e8d7bcf RISC-V: Add vsmul.vv C API tests adds 367a01e6a06 RISC-V: Add vnclip C API tests adds 1580eda6c3d RISC-V: Add vasubu.vx C API tests adds 193a125c3fe RISC-V: Add vasubu.vv C API tests adds 48e24473fe1 RISC-V: Add vasub.vx C API tests adds 4432ef4eca4 RISC-V: Add vasub.vv C API tests adds 6ad0002f1e3 RISC-V: Add vaaddu.vx C API tests adds 119e5d9aff3 RISC-V: Add vaaddu.vv C api tests adds 5898e1f333b RISC-V: Add vaadd.vx C api tests adds e85cb86e338 RISC-V: Add vaadd.vv C api tests adds b7795fb143c RISC-V: Add vssrl.vx C++ API tests adds 02b0325269b RISC-V: Add vssrl.vv C++ API tests adds 7326a694da9 RISC-V: Add vssra.vx C++ API tests adds 49e53882081 RISC-V: Add vssra.vv C++ API tests adds 73dea8e6426 RISC-V: Add vsmul.vx C++ API tests adds 7302972bcd5 RISC-V: Add vsmul.vv C++ API tests adds 0906435e2b6 RISC-V: Add vnclip C++ API tests adds 90ea2d28d47 RISC-V: Add vasubu.vx C++ API tests adds 1a8c69e7ea6 RISC-V: Add vasubu.vv C++ API tests adds 3d65ea07b47 RISC-V: Add vasub.vx C++ API tests adds ff4d996600b RISC-V: Add vasub.vv C++ api tests adds 2ec75330230 RISC-V: Add vaaddu.vx C++ Api tests adds 0b1f45786f4 RISC-V: Add vaaddu.vv C++ api tests adds e8a0c9e9d41 RISC-V: Add vaadd.vx C++ API tests adds 2cd7cbaf51f RISC-V: Add vaadd.vv C++ API tests adds 52009fa79cd RISC-V: Change the generation mode of ADJUST_SP_RTX from ge [...] adds 06ca0c9abb2 doc: Remove direct reference to configure/build docs adds 74e72964b45 libstdc++: Tweak link to N1780 (C++ standard) adds 22ba8570e63 Daily bump. adds 89367e79461 RISC-V: Handle vlenb correctly in unwinding adds 338739645b8 tree-optimization/106722 - fix CD-DCE edge marking adds 9847c7531e8 docs: document new param adds bc5581fe327 arc: Don't use millicode thunks unless asked for. adds 1e191d19b5c IBM zSystems: Fix predicate execute_operation adds 7d5a935070e ifcvt: Fix regression in aarch64/fcsel_1.c adds 6995ac6f98f builtin-declaration-mismatch-7: fix LLP64 targets adds 452db716d8d IBM zSystems: Do not propagate scheduler state across basic [...] adds 6436add49ed tree-optimization/108691 - indirect calls to setjmp adds 72ae1e56356 tree-optimization/28614 - high FRE time for gcc.c-torture/c [...] adds 086a1df4374 Fortran: Add !GCC$ attributes NOINLINE,NORETURN,WEAK adds 296cf77b78b Cleanup libgm2/libm2iso/RTco.cc adds 00b8a212ea2 i386: Relax extract location operand mode requirements [PR108516] adds 2ce7e2a83e1 Fortran: error recovery after invalid use of CLASS variable [...] adds a33e3dcbd15 RA: Clear reg equiv caller_save_p flag when clearing define [...] adds 3cac06d84f3 lra: Replace subregs in bare uses & clobbers [PR108681] adds a1292514f89 libstdc++: Adjust "The Component Object Model" reference adds daeb6c94bbd d: Update __FreeBSD_version values [PR107469] adds ae7197818d6 Daily bump. adds a8d769045b4 libstdc++: Add missing free functions for atomic_flag [PR103934] adds 56cf9372c05 libstdc++: Add missing free functions for atomic_flag [PR103934] adds 4f5a1198065 rs6000/test: Adjust some test cases on partial vector [PR96373] adds b9c78605039 vect: Make partial trapping ops use predication [PR96373] adds 8d8175869ca nvptx: Adjust 'scan-assembler' in 'gfortran.dg/weak-1.f90' adds 26f4b055d97 testsuite: adjust patterns in RISC-V tests to skip unwind t [...] adds 91b36d1c85a asan: Add --param=asan-kernel-mem-intrinsic-prefix= [PR108777] adds 994224236e0 tree-optimization/108782 - nested first order recurrence ve [...] adds a16fc9333f1 Fix musl build on Linux adds 1434eee54e5 Fix small regression in Ada adds e72c2770b6d Improve VN PHI hash table handling adds 7e300a3d04c libstdc++: Update an open-std.org link adds a42ed1d9181 Simplify "1 - bool_val" to "bool_val ^ 1" adds c348a717213 bpf: fix memory constraint of ldx/stx instructions [PR108790] adds cce62625025 c++: fix ICE in joust_maybe_elide_copy [PR106675] adds abbdb623c42 debug: Support "phrs" for dumping a HARD_REG_SET adds d68adf85375 gen_reload: Correct parameter for fatal_insn call adds 05467d08e77 Daily bump. adds ec23e9e25eb target/108738 - STV bitmap operations compile-time hog adds e1dfac7e710 target/108738 - optimize bit operations in STV adds 86bc0909613 Fix possible sanopt compile-time hog adds 1e7a87dc196 c++: Add testcases from some Issaquah DRs adds 545c9f8b78b docs: document new --param=asan-kernel-mem-intrinsic-prefix adds 3f71b82596e powerpc: Fix up expansion for WIDEN_MULT_PLUS_EXPR [PR108787] adds c7a9655be60 libgomp: Fix 'target enter data' with always pointer adds edaf1d60786 libgomp: Fix reverse-offload for GOMP_MAP_TO_PSET adds 7a8cada824c OpenMP/Fortran: Fix loop-iter var privatization with !$OMP [...] adds 8b1b1b2d691 ipa: Avoid IPA confusing scalar values and single-field agg [...] adds 142bd88c5f6 testsuite, objective-c: Fix a testcase on Windows. adds acb51b5c801 RISC-V: Add integer compare C/C++ intrinsic support adds fca68b0bbf8 RISC-V: Add vmsne.vx C api tests adds 946ed63e616 RISC-V: Add vmsne vv C api tests adds 13a256448a5 RISC-V: Add vmslt vx C api tests adds 85a8ad0a351 RISC-V: Add vmslt vv C api tests adds fec15ae4a38 RISC-V: Add vmsle vx C api tests adds f7b8022bcd4 RISC-V: Add vmsle vv C api tests adds 6dae0aa2484 RISC-V: Add vmsgt vx C api tests adds fe1a6c2c8a2 RISC-V: Add vmsgt vv C api tests adds 5893cfb26a1 RISC-V: Add vmsge vx C api tests adds 52ba1d2e235 RISC-V: Add vmsge vv C api tests adds 76db33c592d RISC-V: Add vmseq vx C api tests adds 4d06fc37909 RISC-V: Add vmseq vv C api tests adds 6ec7b7b3e46 RISC-V: Add binop constraints tests for integer compare adds ecdbebde7cb RISC-V: Add vmsne vx C++ tests adds f87fca5d7f2 RISC-V: Add vmsne vv C++ tests adds 18f4691e31e RISC-V: Add vmslt vx C++ tests adds 400f003ee55 RISC-V: Add vmslt vv C++ api tests adds 6c4262a5259 RISC-V: Add vmsle vx C++ api tests adds d6d9206d2b6 RISC-V: Add vmsle vv C++ api tests adds cfbcbe8e27b RISC-V: Add vmsgt vx C++ tests adds 0d689135ffd RISC-V: Add vmsgt vv C++ tests adds 92e575eacf0 RISC-V: Add vmsge vx C++ api tests adds 5e96553eba9 RISC-V: Add vmsge vv C++ tests adds c4e770c4521 RISC-V: Add vmseq vx C++ tests adds a75fa2518d4 RISC-V: Add vmseq vv C++ tests adds 272e119d972 RISC-V: Finish all integer C/C++ intrinsics adds a432d0d9e06 RISC-V: Add vwmacc vx C api tests adds 645bfe04ce1 RISC-V: Add vwmacc vv C api tests adds 51307617b4a RISC-V: Add vnmsub vv C api tests adds a462e612073 RISC-V: Add vnmsub vx rv64 C api tests adds 496ae797c20 RISC-V: Add vnmsub vx rv32 C api tests adds 3a70551148e RISC-V: Add vnmsac rv64 C api tests adds 1d403b1e79f RISC-V: Add vnmsac vx C api tests adds 46444e3984a RISC-V: Add vnmsac vv C api tests adds 0bca2036dc7 RISC-V: Add vmadd vx rv64 c api tests adds 0033ab7b923 RISC-V: Add vmadd vx c api tests adds abbfd706cee RISC-V: Add vmadd vv C api tests adds 987f4bb2f8d RISC-V: Add vmacc vx c api tests adds dce0e53cf62 RISC-V: Add vmacc vx rv32 c api tests adds ddd7c2e9489 RISC-V: Add vmacc vv c api tests adds 5cf9afc5965 RISC-V: Add ternary constraint tests adds c4e2a63e462 RISC-V: Add vwmacc vx C++ api tests adds a5012e90b25 RISC-V: Add vwmacc vv C++ api tests adds 326fe0f2f55 RISC-V: Add vnmsub vx rv64 c++ api tests adds 1ff4063f258 RISC-V: Add vnmsub vx rv32 c++ api tests adds 249be04bb83 RISC-V: Add vnmsub vv c++ api tests adds 7ce337324a8 RISC-V: Add vnmsac vx rv64 C++ api tests adds 0fd29de569b RISC-V: Add vnmsac vx C++ api tests adds 47919b0decb RISC-V: Add vnmsac vv c++ api tests adds 4e43f0cb269 RISC-V: Add vmadd vx C++ api test adds 5db1182b7ca RISC-V: Add vmadd vv c++ api test adds 1ec316c538a RISC-V: Add vmacc vx rv32 c++ api tests adds 4a9a9a787b9 RISC-V: Add vmacc vx rv64 c++ api tests adds 81f0945cd97 RISC-V: Add vmacc vv c++ api tests adds d482b20fd34 warn-access: wrong -Wdangling-pointer with labels [PR106080] adds 053d4dda0a2 Speedup DF dataflow solver adds 1f34cf9bcec i386: Rename extr_register_operand to int248_register_operand adds 0979973c8ea testsuite/i386: Cleanup target selectors in i386 target directory. adds b03a10b0b25 analyzer: fix uninit false +ves [PR108664,PR108666,PR108725] adds a3e499430f1 i386: Relax extract location operand mode requirements adds a4181292737 Fortran: error recovery on invalid assumed size reference [ [...] adds c75cbeba81e Fortran: error recovery on checking procedure argument inte [...] adds d6d3de71706 Fix an accidental double space adds a5dd99f7ef4 Fix PR target/90458 adds 29a3539193b Daily bump. adds 88e02a1de7b testsuite: Add CRIS to check_effective_target_lra non-LRA list adds 384dedaf65d objs-gcc.sh: Only bootstrap if source-directory contains gcc adds 441c466fd4d tree-optimization/108791 - checking ICE with sloppy ADDR_EXPR adds 55db240d28d reassoc: Fix up (ab) handling in eliminate_redundant_compar [...] adds dc79eba72b4 libstdc++: Fix uses of non-reserved names in headers adds 9d71955f383 libgomp: Fix comment typo adds 0b9bd33d69d libgomp: Fix up some typos in libgomp.texi adds cb6beb887e6 libstdc++: Fix non-reserved names in PSTL headers adds 38a8a334187 libstdc++: Add missing space after effective-target name in test adds b81b017ed30 libstdc++: Fix non-reserved names in <ext/throw_allocator.h> adds d82490d5312 doc: Suggest fix for -Woverloaded-virtual warnings adds 7478278f88b libstdc++: Make names_pstl.cc require et tbb_backend adds 866555b1700 tree-ssa-dse: Fix up handling of lhs of internal calls [PR108657] adds 916ce577ad1 libstdc++: Implement P2255R2 dangling checks for std::pair adds 4024f39941f libstdc++: Enable CTAD for std::basic_format_args (LWG 3810) adds 38f321793ae libstdc++: Fix name of <experimental/optional> in comment adds b85c77e19ad libstdc++: Implement <experimental/synchronized_value> (P0290) adds feff71e035c libstdc++: Replace non-ascii character in test adds fea34ee4911 libstdc++: Ensure __builtin_constant_p isn't lost on the way adds 53b55701aed libstdc++: Annotate most lambdas with always_inline adds b0f4b166ada libstdc++: Document timeout and timeout-factor of simd tests adds 073df3e73f3 libstdc++: Use a PCH to speed up check-simd adds 07e4648b4ab libstdc++: printf format string fix in testsuite adds 1fd3836463c libstdc++: Fix incorrect __builtin_is_constant_evaluated calls adds a5de17d9120 libstdc++: Fix incorrect function call in -ffast-math optimization adds cb3e0eac262 don't declare header-defined functions both static and inline adds bb3aee20cde MAINTAINERS: stepping down from my positions adds 46711ff8e60 c++: TYPENAME_TYPE lookup ignoring non-types [PR107773] adds 07f497c2da3 testsuite, objective-c: Cater for Windows intptr type. adds c381327dd6c doc: Reword how to get possible values of a parameter adds 4d3b7be281e analyzer: respect some conditions from bit masks [PR108806] adds 88cc4495250 Daily bump. adds 061b13ed014 Fortran Tests: Allow passing on mingw. adds b9da8f063a6 RISC-V: Replace simm32_p with immediate_operand (Pmode) adds 3b6d44f459d RISC-V: Remove "extern" for namespace [NFC] adds 5804c20b13f RISC-V: Move saturating add/subtract md pattern location [NFC] adds b2dec44ee77 RISC-V: Rearrange the organization of declarations of RVV i [...] adds 3cb0fa12126 RISC-V: Normalize SEW = 64 handling into a simplified function adds c2031252868 RISC-V: Rename tu_preds to none_tu_preds [NFC] adds 1ed93bc7ed8 RISC-V: Add RVV all mask C/C++ intrinsics support adds 6108dc91cda RISC-V: Fix vmnot asm check (Should check vmnot.m instead o [...] adds f978585c293 Fortran test: Modify test cases to pass on mingw. adds 417e95263ca Fix wrong-code issue in VN adds 4c4f0f7acd6 tree-optimization/108821 - store motion and volatiles adds ae2c1d0a9dc contrib: Fix make_sunver.pl warning adds 593c8b73fb1 fixincludes: Bypass solaris_math_12 on newer Solaris 11.4 adds 6ac3ebed5ff simplify-rtx: Fix VOIDmode operand handling in simplify_sub [...] adds 6245441e124 ii386: Generate QImode binary ops with high-part input regi [...] adds 3a0bc47cdb6 c++: make manifestly_const_eval tri-state adds 5fea1be8205 c++: speculative constexpr and is_constant_evaluated [PR108243] adds 9dcfee4ef1a doc: Fix typo in -Wall description new cf4670ff8f3 Merge commit '9dcfee4ef1a165b7fe525d71fc090a1bcae550cd' into HEAD adds 27a89f84c45 '#include "tm_p.h"' in 'gcc/rust/backend/rust-tree.cc' new 99469c4acad Merge commit '27a89f84c458ae938bc3eb92ad0d594c06fc3b42' into HEAD new 24a3d7353f4 Adjust '.github/bors_log_expected_warnings' new e23e7f14a51 Merge remote-tracking branch 'upstream/tschwinge/merge-upstream'

The 11 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.

Summary of changes: .github/bors_log_expected_warnings | 12 +- ChangeLog | 4 + MAINTAINERS | 3 +- contrib/ChangeLog | 4 + contrib/config-list.mk | 2 +- contrib/make_sunver.pl | 2 +- contrib/regression/ChangeLog | 4 + contrib/regression/objs-gcc.sh | 4 +- fixincludes/fixincl.x | 15 +- fixincludes/inclhack.def | 1 + gcc/ChangeLog | 1715 ++ gcc/DATESTAMP | 2 +- gcc/ada/ChangeLog | 10 + gcc/ada/adaint.c | 3 +- gcc/ada/gcc-interface/trans.cc | 4 +- gcc/addresses.h | 6 +- gcc/analyzer/ChangeLog | 92 + gcc/analyzer/constraint-manager.cc | 166 +- gcc/analyzer/constraint-manager.h | 7 + gcc/analyzer/diagnostic-manager.cc | 23 +- gcc/analyzer/engine.cc | 30 +- gcc/analyzer/exploded-graph.h | 1 + gcc/analyzer/feasible-graph.cc | 30 + gcc/analyzer/feasible-graph.h | 5 + gcc/analyzer/infinite-recursion.cc | 7 +- gcc/analyzer/pending-diagnostic.cc | 6 + gcc/analyzer/pending-diagnostic.h | 3 +- gcc/analyzer/region-model.cc | 74 +- gcc/analyzer/sm-fd.cc | 41 +- gcc/analyzer/sm-file.cc | 10 +- gcc/analyzer/sm-malloc.cc | 37 + gcc/analyzer/state-purge.cc | 17 +- gcc/asan.cc | 41 + gcc/asan.h | 15 +- gcc/attribs.cc | 1 + gcc/attribs.h | 16 +- gcc/basic-block.h | 54 +- gcc/bitmap.h | 20 +- gcc/builtins.cc | 21 +- gcc/builtins.def | 1 + gcc/c-family/ChangeLog | 17 + gcc/c-family/c-common.h | 5 +- gcc/c-family/c-warn.cc | 2 +- gcc/c-family/c.opt | 4 + gcc/c/ChangeLog | 48 + gcc/c/c-convert.cc | 21 +- gcc/c/c-objc-common.cc | 8 + gcc/c/c-parser.cc | 88 +- gcc/c/c-parser.h | 6 +- gcc/c/c-tree.h | 1 + gcc/c/c-typeck.cc | 151 +- gcc/calls.cc | 10 +- gcc/cfgexpand.cc | 7 + gcc/cfghooks.h | 2 +- gcc/cfgloop.h | 36 +- gcc/cgraph.cc | 10 +- gcc/cgraph.h | 6 +- gcc/cgraphunit.cc | 2 +- gcc/common/config/aarch64/aarch64-common.cc | 22 +- gcc/common/config/arc/arc-common.cc | 1 - gcc/common/config/i386/cpuinfo.h | 25 +- gcc/common/config/riscv/riscv-common.cc | 6 +- gcc/compare-elim.cc | 3 +- gcc/config.gcc | 3 +- gcc/config/aarch64/aarch64-protos.h | 2 - gcc/config/aarch64/aarch64-simd.md | 2 +- gcc/config/aarch64/aarch64.cc | 11 +- gcc/config/aarch64/aarch64.opt | 2 +- gcc/config/arm/aarch-common.cc | 1 - gcc/config/arm/arm-builtins.cc | 50 +- gcc/config/arm/arm-modes.def | 1 + gcc/config/arm/arm-protos.h | 1 - gcc/config/arm/arm-simd-builtin-types.def | 4 - gcc/config/arm/arm.cc | 54 +- gcc/config/arm/arm.h | 5 + gcc/config/arm/arm.opt | 3 + gcc/config/arm/arm_mve.h | 18 +- gcc/config/arm/arm_mve_builtins.def | 18 +- gcc/config/arm/constraints.md | 2 +- gcc/config/arm/iterators.md | 18 +- gcc/config/arm/mve.md | 66 +- gcc/config/arm/unspecs.md | 10 +- gcc/config/arm/vfp.md | 4 +- gcc/config/bpf/bpf.cc | 2 +- gcc/config/bpf/bpf.md | 10 +- gcc/config/bpf/constraints.md | 11 + gcc/config/gcn/gcn-run.cc | 62 +- gcc/config/gcn/gcn-valu.md | 23 + gcc/config/gcn/gcn.cc | 192 +- gcc/config/gcn/gcn.h | 2 +- gcc/config/gcn/gcn.opt | 2 +- gcc/config/gcn/mkoffload.cc | 18 + gcc/config/i386/i386-features.cc | 67 +- gcc/config/i386/i386.cc | 11 +- gcc/config/i386/i386.md | 260 +- gcc/config/i386/predicates.md | 15 + gcc/config/i386/x86-tune.def | 2 +- gcc/config/loongarch/loongarch.md | 60 +- gcc/config/loongarch/predicates.md | 8 - gcc/config/riscv/constraints.md | 14 +- gcc/config/riscv/iterators.md | 28 +- gcc/config/riscv/predicates.md | 66 +- gcc/config/riscv/riscv-protos.h | 42 +- gcc/config/riscv/riscv-v.cc | 147 +- gcc/config/riscv/riscv-vector-builtins-bases.cc | 876 + gcc/config/riscv/riscv-vector-builtins-bases.h | 95 + .../riscv/riscv-vector-builtins-functions.def | 247 + gcc/config/riscv/riscv-vector-builtins-shapes.cc | 206 + gcc/config/riscv/riscv-vector-builtins-shapes.h | 7 + gcc/config/riscv/riscv-vector-builtins-types.def | 166 + gcc/config/riscv/riscv-vector-builtins.cc | 1072 +- gcc/config/riscv/riscv-vector-builtins.def | 7 +- gcc/config/riscv/riscv-vector-builtins.h | 44 + gcc/config/riscv/riscv-vsetvl.cc | 56 +- gcc/config/riscv/riscv.cc | 69 +- gcc/config/riscv/riscv.h | 20 +- gcc/config/riscv/riscv.md | 10 +- gcc/config/riscv/riscv.opt | 2 + gcc/config/riscv/vector-iterators.md | 367 + gcc/config/riscv/vector.md | 3636 ++- gcc/config/rs6000/rs6000.md | 33 +- gcc/config/s390/predicates.md | 4 +- gcc/config/s390/s390.cc | 313 +- gcc/config/s390/s390.md | 5 +- gcc/config/s390/s390.opt | 4 + gcc/cp/ChangeLog | 125 + gcc/cp/call.cc | 6 +- gcc/cp/class.cc | 56 +- gcc/cp/constexpr.cc | 110 +- gcc/cp/constraint.cc | 3 +- gcc/cp/cp-gimplify.cc | 162 +- gcc/cp/cp-tree.h | 27 +- gcc/cp/decl.cc | 11 +- gcc/cp/mangle.cc | 8 + gcc/cp/parser.cc | 97 +- gcc/cp/pt.cc | 66 +- gcc/cp/search.cc | 2 +- gcc/cp/semantics.cc | 15 +- gcc/cp/tree.cc | 24 +- gcc/cselib.cc | 28 +- gcc/cselib.h | 4 +- gcc/data-streamer.h | 30 +- gcc/debug.h | 2 +- gcc/df-core.cc | 54 +- gcc/df.h | 26 +- gcc/diagnostic.h | 12 +- gcc/doc/extend.texi | 2 +- gcc/doc/gm2.texi | 30 +- gcc/doc/include/gpl_v3.texi | 2 +- gcc/doc/install.texi | 3 - gcc/doc/invoke.texi | 43 +- gcc/doc/sourcebuild.texi | 3 +- gcc/dominance.cc | 27 +- gcc/dominance.h | 2 +- gcc/dumpfile.h | 16 +- gcc/dwarf2cfi.cc | 15 +- gcc/emit-rtl.h | 14 +- gcc/except.h | 2 +- gcc/expmed.h | 102 +- gcc/expr.h | 14 +- gcc/fixed-value.h | 2 +- gcc/fortran/ChangeLog | 99 + gcc/fortran/arith.cc | 2 +- gcc/fortran/decl.cc | 3 + gcc/fortran/expr.cc | 6 +- gcc/fortran/frontend-passes.cc | 3 +- gcc/fortran/gfortran.h | 7 +- gcc/fortran/gfortran.texi | 7 + gcc/fortran/intrinsic.cc | 3 +- gcc/fortran/openmp.cc | 22 +- gcc/fortran/parse.cc | 3 + gcc/fortran/primary.cc | 2 +- gcc/fortran/resolve.cc | 29 +- gcc/fortran/trans-decl.cc | 20 +- gcc/fortran/trans-openmp.cc | 241 +- gcc/gcc.cc | 2 +- gcc/gdbinit.in | 12 + gcc/gengtype.h | 12 +- gcc/genmatch.cc | 6 +- gcc/gimple-expr.h | 18 +- gcc/gimple-fold.cc | 12 +- gcc/gimple-iterator.h | 48 +- gcc/gimple-predict.h | 10 +- gcc/gimple-range-cache.cc | 2 +- gcc/gimple-range-fold.h | 6 +- gcc/gimple-range-gori.cc | 83 +- gcc/gimple-range-infer.cc | 2 +- gcc/gimple-ssa-warn-access.cc | 19 +- gcc/gimple-ssa.h | 14 +- gcc/gimple.cc | 11 +- gcc/gimple.h | 1026 +- gcc/gimplify.cc | 2 +- gcc/graphite.h | 24 +- gcc/hard-reg-set.h | 18 +- gcc/hash-map.h | 8 +- gcc/hash-set.h | 6 +- gcc/hash-table.h | 6 +- gcc/hwint.h | 26 +- gcc/ifcvt.cc | 31 +- gcc/ifcvt.h | 8 + gcc/input.h | 12 +- gcc/insn-addr.h | 2 +- gcc/internal-fn.cc | 6 - gcc/internal-fn.def | 5 - gcc/internal-fn.h | 6 +- gcc/ipa-cp.cc | 4 +- gcc/ipa-devirt.cc | 18 +- gcc/ipa-fnsummary.h | 2 +- gcc/ipa-icf-gimple.h | 6 +- gcc/ipa-inline.h | 10 +- gcc/ipa-modref.h | 2 +- gcc/ipa-param-manipulation.cc | 4 + gcc/ipa-prop.h | 70 +- gcc/ipa-split.cc | 5 +- gcc/ipa-sra.cc | 66 +- gcc/ipa.cc | 2 +- gcc/ira-color.cc | 7 + gcc/ira-int.h | 50 +- gcc/ira.cc | 38 +- gcc/ira.h | 7 +- gcc/jit/ChangeLog | 6 + gcc/jit/jit-dejagnu.h | 16 +- gcc/jit/jit-recording.h | 2 +- gcc/lra-constraints.cc | 18 +- gcc/lra-int.h | 14 +- gcc/lra-spills.cc | 3 + gcc/lra.h | 2 +- gcc/lto-streamer.h | 54 +- gcc/lto-wrapper.cc | 4 + gcc/m2/ChangeLog | 388 + gcc/m2/Make-lang.in | 159 +- gcc/m2/Make-maintainer.in | 112 +- gcc/m2/gm2-compiler/M2ALU.mod | 4 +- gcc/m2/gm2-compiler/M2Base.mod | 11 +- gcc/m2/gm2-compiler/M2GCCDeclare.mod | 6 +- gcc/m2/gm2-compiler/M2GenGCC.mod | 8 +- gcc/m2/gm2-compiler/M2Preprocess.mod | 2 + gcc/m2/gm2-compiler/M2Quads.mod | 10 +- gcc/m2/gm2-compiler/M2Search.mod | 5 +- gcc/m2/gm2-compiler/M2System.mod | 2 + gcc/m2/gm2-gcc/m2except.cc | 6 +- gcc/m2/gm2-lang.cc | 1 - gcc/m2/gm2-libs-coroutines/Debug.def | 2 +- gcc/m2/gm2-libs-coroutines/SYSTEM.def | 2 +- gcc/m2/gm2-libs-iso/ClientSocket.mod | 9 +- gcc/m2/gm2-libs-iso/EXCEPTIONS.def | 3 +- gcc/m2/gm2-libs-iso/IOLink.def | 4 +- gcc/m2/gm2-libs-iso/M2RTS.def | 57 +- gcc/m2/gm2-libs-iso/SYSTEM.def | 2 +- gcc/m2/gm2-libs-iso/TermFile.mod | 16 +- gcc/m2/gm2-libs-min/M2RTS.def | 2 +- gcc/m2/gm2-libs/FIO.mod | 13 +- gcc/m2/gm2-libs/M2RTS.def | 50 +- gcc/m2/gm2-libs/RTExceptions.def | 2 +- gcc/m2/gm2-libs/RTExceptions.mod | 15 +- gcc/m2/gm2-libs/SYSTEM.def | 2 +- gcc/m2/gm2spec.cc | 28 - gcc/m2/m2.flex | 2 +- gcc/m2/m2pp.cc | 2 +- gcc/m2/mc-boot-ch/GBuiltins.c | 2 +- gcc/m2/mc-boot-ch/GRTco.c | 2 +- gcc/m2/mc-boot-ch/GSYSTEM.c | 2 +- gcc/m2/mc-boot-ch/GSelective.c | 2 +- gcc/m2/mc-boot-ch/GSysExceptions.c | 4 +- gcc/m2/mc-boot-ch/GUnixArgs.cc | 4 +- gcc/m2/mc-boot-ch/Gdtoa.c | 2 +- gcc/m2/mc-boot-ch/Gerrno.c | 2 +- gcc/m2/mc-boot-ch/Gldtoa.c | 2 +- gcc/m2/mc-boot-ch/Gtermios.cc | 4 +- gcc/m2/mc-boot-ch/Gwrapc.c | 4 +- gcc/m2/mc-boot/GASCII.c | 2 +- gcc/m2/mc-boot/GArgs.c | 2 +- gcc/m2/mc-boot/GAssertion.c | 2 +- gcc/m2/mc-boot/GBreak.c | 2 +- gcc/m2/mc-boot/GCmdArgs.c | 2 +- gcc/m2/mc-boot/GDebug.c | 2 +- gcc/m2/mc-boot/GDynamicStrings.c | 2 +- gcc/m2/mc-boot/GEnvironment.c | 2 +- gcc/m2/mc-boot/GFIO.c | 2 +- gcc/m2/mc-boot/GFormatStrings.c | 2 +- gcc/m2/mc-boot/GFpuIO.c | 2 +- gcc/m2/mc-boot/GIO.c | 2 +- gcc/m2/mc-boot/GIndexing.c | 2 +- gcc/m2/mc-boot/GM2Dependent.c | 2 +- gcc/m2/mc-boot/GM2EXCEPTION.c | 2 +- gcc/m2/mc-boot/GM2RTS.c | 52 +- gcc/m2/mc-boot/GM2RTS.h | 50 +- gcc/m2/mc-boot/GMemUtils.c | 2 +- gcc/m2/mc-boot/GNumberIO.c | 2 +- gcc/m2/mc-boot/GPushBackInput.c | 2 +- gcc/m2/mc-boot/GRTExceptions.c | 40 +- gcc/m2/mc-boot/GRTExceptions.h | 2 +- gcc/m2/mc-boot/GRTco.h | 1 + gcc/m2/mc-boot/{GMemUtils.h => GRTentity.h} | 33 +- gcc/m2/mc-boot/GRTint.c | 2 +- gcc/m2/mc-boot/GSArgs.c | 2 +- gcc/m2/mc-boot/GSFIO.c | 2 +- gcc/m2/mc-boot/GStdIO.c | 2 +- gcc/m2/mc-boot/GStorage.c | 2 +- gcc/m2/mc-boot/GStrCase.c | 2 +- gcc/m2/mc-boot/GStrIO.c | 2 +- gcc/m2/mc-boot/GStrLib.c | 2 +- gcc/m2/mc-boot/GStringConvert.c | 2 +- gcc/m2/mc-boot/GSysStorage.c | 2 +- gcc/m2/mc-boot/GTimeString.c | 2 +- gcc/m2/mc-boot/Galists.c | 2 +- gcc/m2/mc-boot/Gdecl.c | 56 +- gcc/m2/mc-boot/Gkeyc.c | 2 +- gcc/m2/mc-boot/Glists.c | 2 +- gcc/m2/mc-boot/GmcComment.c | 2 +- gcc/m2/mc-boot/GmcComp.c | 2 +- gcc/m2/mc-boot/GmcDebug.c | 2 +- gcc/m2/mc-boot/GmcError.c | 2 +- gcc/m2/mc-boot/GmcFileName.c | 2 +- gcc/m2/mc-boot/GmcLexBuf.c | 2 +- gcc/m2/mc-boot/GmcMetaError.c | 2 +- gcc/m2/mc-boot/GmcOptions.c | 2 +- gcc/m2/mc-boot/GmcPreprocess.c | 2 +- gcc/m2/mc-boot/GmcPretty.c | 2 +- gcc/m2/mc-boot/GmcPrintf.c | 2 +- gcc/m2/mc-boot/GmcQuiet.c | 2 +- gcc/m2/mc-boot/GmcReserved.c | 2 +- gcc/m2/mc-boot/GmcSearch.c | 2 +- gcc/m2/mc-boot/GmcStack.c | 2 +- gcc/m2/mc-boot/GmcStream.c | 2 +- gcc/m2/mc-boot/Gmcp1.c | 2 +- gcc/m2/mc-boot/Gmcp2.c | 2 +- gcc/m2/mc-boot/Gmcp3.c | 2 +- gcc/m2/mc-boot/Gmcp4.c | 2 +- gcc/m2/mc-boot/Gmcp5.c | 2 +- gcc/m2/mc-boot/GnameKey.c | 2 +- gcc/m2/mc-boot/GsymbolKey.c | 2 +- gcc/m2/mc-boot/Gtop.c | 2 +- gcc/m2/mc-boot/Gvarargs.c | 2 +- gcc/m2/mc-boot/Gwlists.c | 2 +- gcc/m2/mc/decl.mod | 4 +- gcc/m2/mc/mc.flex | 5 + gcc/m2/tools-src/mklink.c | 6 +- gcc/match.pd | 22 +- gcc/memmodel.h | 18 +- gcc/objc/ChangeLog | 8 + gcc/objc/objc-act.cc | 2 - gcc/objc/objc-act.h | 6 +- gcc/objc/objc-map.h | 12 +- gcc/omp-general.h | 2 +- gcc/optabs-query.h | 8 +- gcc/optabs.h | 14 +- gcc/params.opt | 8 + gcc/plugin.h | 2 +- gcc/po/ChangeLog | 4 + gcc/po/gcc.pot | 27954 ++++++++++--------- gcc/pretty-print.h | 10 +- gcc/range-op-float.cc | 56 + gcc/range-op.cc | 111 +- gcc/range-op.h | 6 + gcc/range.h | 6 +- gcc/read-md.h | 4 +- gcc/recog.h | 8 +- gcc/ree.cc | 6 +- gcc/reg-notes.def | 5 + gcc/regs.h | 22 +- gcc/reload1.cc | 2 +- gcc/rtl-iter.h | 2 +- gcc/rtl-ssa/accesses.cc | 14 +- gcc/rtl-ssa/insns.h | 14 +- gcc/rtl.h | 34 +- gcc/rust/ChangeLog | 1014 + gcc/rust/Make-lang.in | 2 +- gcc/rust/ast/rust-ast-full-decls.h | 1 + gcc/rust/ast/rust-ast.cc | 2 +- gcc/rust/ast/rust-ast.h | 6 +- gcc/rust/ast/rust-expr.h | 138 + gcc/rust/ast/rust-item.h | 44 +- gcc/rust/ast/rust-macro.h | 10 +- gcc/rust/backend/rust-tree.cc | 2 +- .../errors/privacy/rust-visibility-resolver.cc | 4 +- gcc/rust/expand/rust-macro-builtins.cc | 2 +- gcc/rust/expand/rust-macro-expand.cc | 4 +- .../tree/{rust-hir-full-test.cc => rust-hir.cc} | 0 gcc/rust/parse/rust-parse-impl.h | 27 +- gcc/rust/rust-diagnostics.cc | 43 +- gcc/rust/rust-diagnostics.h | 56 +- gcc/rust/rust-session-manager.cc | 6 +- gcc/sanopt.cc | 17 +- gcc/sbitmap.h | 16 +- gcc/sched-deps.cc | 9 +- gcc/sched-int.h | 8 +- gcc/sel-sched-dump.cc | 10 - gcc/sel-sched-ir.h | 48 +- gcc/sese.h | 30 +- gcc/simplify-rtx.cc | 16 + gcc/sparseset.h | 22 +- gcc/ssa-iterators.h | 86 +- gcc/system.h | 6 +- gcc/target-globals.h | 2 +- gcc/target.h | 6 +- gcc/testsuite/ChangeLog | 7557 +++++ gcc/testsuite/c-c++-common/Wdangling-pointer-10.c | 12 + gcc/testsuite/c-c++-common/Wdangling-pointer-9.c | 9 + gcc/testsuite/c-c++-common/Wsizeof-array-div1.c | 6 +- .../c-c++-common/cpp/delimited-escape-seq-8.c | 20 + gcc/testsuite/c-c++-common/gomp/allocate-5.c | 36 + gcc/testsuite/c-c++-common/pr108605.c | 24 + gcc/testsuite/g++.dg/DRs/dr2475.C | 6 + gcc/testsuite/g++.dg/DRs/dr2478.C | 74 + gcc/testsuite/g++.dg/DRs/dr2530.C | 5 + gcc/testsuite/g++.dg/DRs/dr2673.C | 24 + gcc/testsuite/g++.dg/cpp0x/constexpr-nsdmi2.C | 9 + gcc/testsuite/g++.dg/cpp0x/overload-conv-5.C | 21 + gcc/testsuite/g++.dg/cpp0x/overload5.C | 12 + gcc/testsuite/g++.dg/cpp0x/overload5a.C | 10 + gcc/testsuite/g++.dg/cpp0x/overload6.C | 16 + gcc/testsuite/g++.dg/cpp0x/pr108698.C | 16 + .../cpp0x/{variadic-alias2.C => variadic-alias8.C} | 14 +- gcc/testsuite/g++.dg/cpp0x/variadic184.C | 12 + gcc/testsuite/g++.dg/cpp1y/constexpr-108158.C | 32 + gcc/testsuite/g++.dg/cpp1z/aggr-base13.C | 19 + gcc/testsuite/g++.dg/cpp23/static-operator-call5.C | 5 - gcc/testsuite/g++.dg/cpp23/static-operator-call6.C | 5 + gcc/testsuite/g++.dg/cpp2a/concepts-dtor1.C | 18 + gcc/testsuite/g++.dg/cpp2a/concepts-pr108579.C | 14 + gcc/testsuite/g++.dg/ext/builtin-object-size1.C | 260 +- gcc/testsuite/g++.dg/ext/builtin-object-size2.C | 260 +- gcc/testsuite/g++.dg/gomp/attrs-10.C | 6 +- gcc/testsuite/g++.dg/gomp/declare-simd-8.C | 1 + gcc/testsuite/g++.dg/gomp/pr108607.C | 47 + gcc/testsuite/g++.dg/ipa/pr108509.C | 22 + gcc/testsuite/g++.dg/opt/is_constant_evaluated1.C | 20 + gcc/testsuite/g++.dg/opt/is_constant_evaluated2.C | 32 + gcc/testsuite/g++.dg/pr108520.C | 17 + gcc/testsuite/g++.dg/pr71488.C | 1 + gcc/testsuite/g++.dg/template/call9.C | 26 + gcc/testsuite/g++.dg/template/typename24.C | 18 + gcc/testsuite/g++.dg/template/typename25.C | 33 + gcc/testsuite/g++.dg/template/typename25a.C | 37 + gcc/testsuite/g++.dg/template/typename26.C | 19 + gcc/testsuite/g++.dg/torture/pr108647.C | 25 + gcc/testsuite/g++.dg/tree-ssa/pr107876.C | 2 +- gcc/testsuite/g++.dg/warn/Warray-bounds-16.C | 1 + gcc/testsuite/g++.dg/warn/Wduplicated-cond3.C | 38 + gcc/testsuite/g++.dg/warn/Wduplicated-cond4.C | 17 + gcc/testsuite/g++.dg/warn/Wduplicated-cond5.C | 16 + gcc/testsuite/g++.dg/warn/Wlogical-op-4.C | 23 + .../g++.dg/warn/Wstrict-aliasing-bogus-union-2.C | 2 +- gcc/testsuite/g++.dg/warn/Wstringop-overflow-4.C | 2 +- gcc/testsuite/g++.dg/warn/changes-meaning2.C | 16 + gcc/testsuite/g++.dg/warn/changes-meaning3.C | 13 + gcc/testsuite/g++.target/i386/empty-class2.C | 1 - gcc/testsuite/g++.target/i386/pr108711.C | 20 + gcc/testsuite/g++.target/loongarch/bytepick.C | 32 + .../g++.target/riscv/rvv/base/exception-1.C | 27 + .../g++.target/riscv/rvv/base/vaadd_vv-1.C | 314 + .../g++.target/riscv/rvv/base/vaadd_vv-2.C | 314 + .../g++.target/riscv/rvv/base/vaadd_vv-3.C | 314 + .../g++.target/riscv/rvv/base/vaadd_vv_mu-1.C | 160 + .../g++.target/riscv/rvv/base/vaadd_vv_mu-2.C | 160 + .../g++.target/riscv/rvv/base/vaadd_vv_mu-3.C | 160 + .../g++.target/riscv/rvv/base/vaadd_vv_tu-1.C | 160 + .../g++.target/riscv/rvv/base/vaadd_vv_tu-2.C | 160 + .../g++.target/riscv/rvv/base/vaadd_vv_tu-3.C | 160 + .../g++.target/riscv/rvv/base/vaadd_vv_tum-1.C | 160 + .../g++.target/riscv/rvv/base/vaadd_vv_tum-2.C | 160 + .../g++.target/riscv/rvv/base/vaadd_vv_tum-3.C | 160 + .../g++.target/riscv/rvv/base/vaadd_vv_tumu-1.C | 160 + .../g++.target/riscv/rvv/base/vaadd_vv_tumu-2.C | 160 + .../g++.target/riscv/rvv/base/vaadd_vv_tumu-3.C | 160 + .../g++.target/riscv/rvv/base/vaadd_vx_mu_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vaadd_vx_mu_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vaadd_vx_mu_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vaadd_vx_mu_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vaadd_vx_mu_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vaadd_vx_mu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vaadd_vx_rv32-1.C | 308 + .../g++.target/riscv/rvv/base/vaadd_vx_rv32-2.C | 308 + .../g++.target/riscv/rvv/base/vaadd_vx_rv32-3.C | 308 + .../g++.target/riscv/rvv/base/vaadd_vx_rv64-1.C | 314 + .../g++.target/riscv/rvv/base/vaadd_vx_rv64-2.C | 314 + .../g++.target/riscv/rvv/base/vaadd_vx_rv64-3.C | 314 + .../g++.target/riscv/rvv/base/vaadd_vx_tu_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vaadd_vx_tu_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vaadd_vx_tu_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vaadd_vx_tu_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vaadd_vx_tu_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vaadd_vx_tu_rv64-3.C | 160 + .../riscv/rvv/base/vaadd_vx_tum_rv32-1.C | 157 + .../riscv/rvv/base/vaadd_vx_tum_rv32-2.C | 157 + .../riscv/rvv/base/vaadd_vx_tum_rv32-3.C | 157 + .../riscv/rvv/base/vaadd_vx_tum_rv64-1.C | 160 + .../riscv/rvv/base/vaadd_vx_tum_rv64-2.C | 160 + .../riscv/rvv/base/vaadd_vx_tum_rv64-3.C | 160 + .../riscv/rvv/base/vaadd_vx_tumu_rv32-1.C | 157 + .../riscv/rvv/base/vaadd_vx_tumu_rv32-2.C | 157 + .../riscv/rvv/base/vaadd_vx_tumu_rv32-3.C | 157 + .../riscv/rvv/base/vaadd_vx_tumu_rv64-1.C | 160 + .../riscv/rvv/base/vaadd_vx_tumu_rv64-2.C | 160 + .../riscv/rvv/base/vaadd_vx_tumu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vaaddu_vv-1.C | 314 + .../g++.target/riscv/rvv/base/vaaddu_vv-2.C | 314 + .../g++.target/riscv/rvv/base/vaaddu_vv-3.C | 314 + .../g++.target/riscv/rvv/base/vaaddu_vv_mu-1.C | 160 + .../g++.target/riscv/rvv/base/vaaddu_vv_mu-2.C | 160 + .../g++.target/riscv/rvv/base/vaaddu_vv_mu-3.C | 160 + .../g++.target/riscv/rvv/base/vaaddu_vv_tu-1.C | 160 + .../g++.target/riscv/rvv/base/vaaddu_vv_tu-2.C | 160 + .../g++.target/riscv/rvv/base/vaaddu_vv_tu-3.C | 160 + .../g++.target/riscv/rvv/base/vaaddu_vv_tum-1.C | 160 + .../g++.target/riscv/rvv/base/vaaddu_vv_tum-2.C | 160 + .../g++.target/riscv/rvv/base/vaaddu_vv_tum-3.C | 160 + .../g++.target/riscv/rvv/base/vaaddu_vv_tumu-1.C | 160 + .../g++.target/riscv/rvv/base/vaaddu_vv_tumu-2.C | 160 + .../g++.target/riscv/rvv/base/vaaddu_vv_tumu-3.C | 160 + .../riscv/rvv/base/vaaddu_vx_mu_rv32-1.C | 157 + .../riscv/rvv/base/vaaddu_vx_mu_rv32-2.C | 157 + .../riscv/rvv/base/vaaddu_vx_mu_rv32-3.C | 157 + .../riscv/rvv/base/vaaddu_vx_mu_rv64-1.C | 160 + .../riscv/rvv/base/vaaddu_vx_mu_rv64-2.C | 160 + .../riscv/rvv/base/vaaddu_vx_mu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vaaddu_vx_rv32-1.C | 308 + .../g++.target/riscv/rvv/base/vaaddu_vx_rv32-2.C | 308 + .../g++.target/riscv/rvv/base/vaaddu_vx_rv32-3.C | 308 + .../g++.target/riscv/rvv/base/vaaddu_vx_rv64-1.C | 314 + .../g++.target/riscv/rvv/base/vaaddu_vx_rv64-2.C | 314 + .../g++.target/riscv/rvv/base/vaaddu_vx_rv64-3.C | 314 + .../riscv/rvv/base/vaaddu_vx_tu_rv32-1.C | 157 + .../riscv/rvv/base/vaaddu_vx_tu_rv32-2.C | 157 + .../riscv/rvv/base/vaaddu_vx_tu_rv32-3.C | 157 + .../riscv/rvv/base/vaaddu_vx_tu_rv64-1.C | 160 + .../riscv/rvv/base/vaaddu_vx_tu_rv64-2.C | 160 + .../riscv/rvv/base/vaaddu_vx_tu_rv64-3.C | 160 + .../riscv/rvv/base/vaaddu_vx_tum_rv32-1.C | 157 + .../riscv/rvv/base/vaaddu_vx_tum_rv32-2.C | 157 + .../riscv/rvv/base/vaaddu_vx_tum_rv32-3.C | 157 + .../riscv/rvv/base/vaaddu_vx_tum_rv64-1.C | 160 + .../riscv/rvv/base/vaaddu_vx_tum_rv64-2.C | 160 + .../riscv/rvv/base/vaaddu_vx_tum_rv64-3.C | 160 + .../riscv/rvv/base/vaaddu_vx_tumu_rv32-1.C | 157 + .../riscv/rvv/base/vaaddu_vx_tumu_rv32-2.C | 157 + .../riscv/rvv/base/vaaddu_vx_tumu_rv32-3.C | 157 + .../riscv/rvv/base/vaaddu_vx_tumu_rv64-1.C | 160 + .../riscv/rvv/base/vaaddu_vx_tumu_rv64-2.C | 160 + .../riscv/rvv/base/vaaddu_vx_tumu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vadc_vvm-1.C | 292 + .../g++.target/riscv/rvv/base/vadc_vvm-2.C | 292 + .../g++.target/riscv/rvv/base/vadc_vvm-3.C | 292 + .../g++.target/riscv/rvv/base/vadc_vvm_tu-1.C | 292 + .../g++.target/riscv/rvv/base/vadc_vvm_tu-2.C | 292 + .../g++.target/riscv/rvv/base/vadc_vvm_tu-3.C | 292 + .../g++.target/riscv/rvv/base/vadc_vxm_rv32-1.C | 289 + .../g++.target/riscv/rvv/base/vadc_vxm_rv32-2.C | 289 + .../g++.target/riscv/rvv/base/vadc_vxm_rv32-3.C | 289 + .../g++.target/riscv/rvv/base/vadc_vxm_rv64-1.C | 292 + .../g++.target/riscv/rvv/base/vadc_vxm_rv64-2.C | 292 + .../g++.target/riscv/rvv/base/vadc_vxm_rv64-3.C | 292 + .../g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-1.C | 289 + .../g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-2.C | 289 + .../g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-3.C | 289 + .../g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-1.C | 292 + .../g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-2.C | 292 + .../g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-3.C | 292 + .../g++.target/riscv/rvv/base/vadd_vv-1.C | 578 + .../g++.target/riscv/rvv/base/vadd_vv-2.C | 578 + .../g++.target/riscv/rvv/base/vadd_vv-3.C | 578 + .../g++.target/riscv/rvv/base/vadd_vv_mu-1.C | 292 + .../g++.target/riscv/rvv/base/vadd_vv_mu-2.C | 292 + .../g++.target/riscv/rvv/base/vadd_vv_mu-3.C | 292 + .../g++.target/riscv/rvv/base/vadd_vv_tu-1.C | 292 + .../g++.target/riscv/rvv/base/vadd_vv_tu-2.C | 292 + .../g++.target/riscv/rvv/base/vadd_vv_tu-3.C | 292 + .../g++.target/riscv/rvv/base/vadd_vv_tum-1.C | 292 + .../g++.target/riscv/rvv/base/vadd_vv_tum-2.C | 292 + .../g++.target/riscv/rvv/base/vadd_vv_tum-3.C | 292 + .../g++.target/riscv/rvv/base/vadd_vv_tumu-1.C | 292 + .../g++.target/riscv/rvv/base/vadd_vv_tumu-2.C | 292 + .../g++.target/riscv/rvv/base/vadd_vv_tumu-3.C | 292 + .../g++.target/riscv/rvv/base/vadd_vx_mu_rv32-1.C | 289 + .../g++.target/riscv/rvv/base/vadd_vx_mu_rv32-2.C | 289 + .../g++.target/riscv/rvv/base/vadd_vx_mu_rv32-3.C | 289 + .../g++.target/riscv/rvv/base/vadd_vx_mu_rv64-1.C | 292 + .../g++.target/riscv/rvv/base/vadd_vx_mu_rv64-2.C | 292 + .../g++.target/riscv/rvv/base/vadd_vx_mu_rv64-3.C | 292 + .../g++.target/riscv/rvv/base/vadd_vx_rv32-1.C | 572 + .../g++.target/riscv/rvv/base/vadd_vx_rv32-2.C | 572 + .../g++.target/riscv/rvv/base/vadd_vx_rv32-3.C | 572 + .../g++.target/riscv/rvv/base/vadd_vx_rv64-1.C | 578 + .../g++.target/riscv/rvv/base/vadd_vx_rv64-2.C | 578 + .../g++.target/riscv/rvv/base/vadd_vx_rv64-3.C | 578 + .../g++.target/riscv/rvv/base/vadd_vx_tu_rv32-1.C | 289 + .../g++.target/riscv/rvv/base/vadd_vx_tu_rv32-2.C | 289 + .../g++.target/riscv/rvv/base/vadd_vx_tu_rv32-3.C | 289 + .../g++.target/riscv/rvv/base/vadd_vx_tu_rv64-1.C | 292 + .../g++.target/riscv/rvv/base/vadd_vx_tu_rv64-2.C | 292 + .../g++.target/riscv/rvv/base/vadd_vx_tu_rv64-3.C | 292 + .../g++.target/riscv/rvv/base/vadd_vx_tum_rv32-1.C | 289 + .../g++.target/riscv/rvv/base/vadd_vx_tum_rv32-2.C | 289 + .../g++.target/riscv/rvv/base/vadd_vx_tum_rv32-3.C | 289 + .../g++.target/riscv/rvv/base/vadd_vx_tum_rv64-1.C | 292 + .../g++.target/riscv/rvv/base/vadd_vx_tum_rv64-2.C | 292 + .../g++.target/riscv/rvv/base/vadd_vx_tum_rv64-3.C | 292 + .../riscv/rvv/base/vadd_vx_tumu_rv32-1.C | 289 + .../riscv/rvv/base/vadd_vx_tumu_rv32-2.C | 289 + .../riscv/rvv/base/vadd_vx_tumu_rv32-3.C | 289 + .../riscv/rvv/base/vadd_vx_tumu_rv64-1.C | 292 + .../riscv/rvv/base/vadd_vx_tumu_rv64-2.C | 292 + .../riscv/rvv/base/vadd_vx_tumu_rv64-3.C | 292 + .../g++.target/riscv/rvv/base/vand_vv-1.C | 578 + .../g++.target/riscv/rvv/base/vand_vv-2.C | 578 + .../g++.target/riscv/rvv/base/vand_vv-3.C | 578 + .../g++.target/riscv/rvv/base/vand_vv_mu-1.C | 292 + .../g++.target/riscv/rvv/base/vand_vv_mu-2.C | 292 + .../g++.target/riscv/rvv/base/vand_vv_mu-3.C | 292 + .../g++.target/riscv/rvv/base/vand_vv_tu-1.C | 292 + .../g++.target/riscv/rvv/base/vand_vv_tu-2.C | 292 + .../g++.target/riscv/rvv/base/vand_vv_tu-3.C | 292 + .../g++.target/riscv/rvv/base/vand_vv_tum-1.C | 292 + .../g++.target/riscv/rvv/base/vand_vv_tum-2.C | 292 + .../g++.target/riscv/rvv/base/vand_vv_tum-3.C | 292 + .../g++.target/riscv/rvv/base/vand_vv_tumu-1.C | 292 + .../g++.target/riscv/rvv/base/vand_vv_tumu-2.C | 292 + .../g++.target/riscv/rvv/base/vand_vv_tumu-3.C | 292 + .../g++.target/riscv/rvv/base/vand_vx_mu_rv32-1.C | 289 + .../g++.target/riscv/rvv/base/vand_vx_mu_rv32-2.C | 289 + .../g++.target/riscv/rvv/base/vand_vx_mu_rv32-3.C | 289 + .../g++.target/riscv/rvv/base/vand_vx_mu_rv64-1.C | 292 + .../g++.target/riscv/rvv/base/vand_vx_mu_rv64-2.C | 292 + .../g++.target/riscv/rvv/base/vand_vx_mu_rv64-3.C | 292 + .../g++.target/riscv/rvv/base/vand_vx_rv32-1.C | 572 + .../g++.target/riscv/rvv/base/vand_vx_rv32-2.C | 572 + .../g++.target/riscv/rvv/base/vand_vx_rv32-3.C | 572 + .../g++.target/riscv/rvv/base/vand_vx_rv64-1.C | 578 + .../g++.target/riscv/rvv/base/vand_vx_rv64-2.C | 578 + .../g++.target/riscv/rvv/base/vand_vx_rv64-3.C | 578 + .../g++.target/riscv/rvv/base/vand_vx_tu_rv32-1.C | 289 + .../g++.target/riscv/rvv/base/vand_vx_tu_rv32-2.C | 289 + .../g++.target/riscv/rvv/base/vand_vx_tu_rv32-3.C | 289 + .../g++.target/riscv/rvv/base/vand_vx_tu_rv64-1.C | 292 + .../g++.target/riscv/rvv/base/vand_vx_tu_rv64-2.C | 292 + .../g++.target/riscv/rvv/base/vand_vx_tu_rv64-3.C | 292 + .../g++.target/riscv/rvv/base/vand_vx_tum_rv32-1.C | 289 + .../g++.target/riscv/rvv/base/vand_vx_tum_rv32-2.C | 289 + .../g++.target/riscv/rvv/base/vand_vx_tum_rv32-3.C | 289 + .../g++.target/riscv/rvv/base/vand_vx_tum_rv64-1.C | 292 + .../g++.target/riscv/rvv/base/vand_vx_tum_rv64-2.C | 292 + .../g++.target/riscv/rvv/base/vand_vx_tum_rv64-3.C | 292 + .../riscv/rvv/base/vand_vx_tumu_rv32-1.C | 289 + .../riscv/rvv/base/vand_vx_tumu_rv32-2.C | 289 + .../riscv/rvv/base/vand_vx_tumu_rv32-3.C | 289 + .../riscv/rvv/base/vand_vx_tumu_rv64-1.C | 292 + .../riscv/rvv/base/vand_vx_tumu_rv64-2.C | 292 + .../riscv/rvv/base/vand_vx_tumu_rv64-3.C | 292 + .../g++.target/riscv/rvv/base/vasub_vv-1.C | 314 + .../g++.target/riscv/rvv/base/vasub_vv-2.C | 314 + .../g++.target/riscv/rvv/base/vasub_vv-3.C | 314 + .../g++.target/riscv/rvv/base/vasub_vv_mu-1.C | 160 + .../g++.target/riscv/rvv/base/vasub_vv_mu-2.C | 160 + .../g++.target/riscv/rvv/base/vasub_vv_mu-3.C | 160 + .../g++.target/riscv/rvv/base/vasub_vv_tu-1.C | 160 + .../g++.target/riscv/rvv/base/vasub_vv_tu-2.C | 160 + .../g++.target/riscv/rvv/base/vasub_vv_tu-3.C | 160 + .../g++.target/riscv/rvv/base/vasub_vv_tum-1.C | 160 + .../g++.target/riscv/rvv/base/vasub_vv_tum-2.C | 160 + .../g++.target/riscv/rvv/base/vasub_vv_tum-3.C | 160 + .../g++.target/riscv/rvv/base/vasub_vv_tumu-1.C | 160 + .../g++.target/riscv/rvv/base/vasub_vv_tumu-2.C | 160 + .../g++.target/riscv/rvv/base/vasub_vv_tumu-3.C | 160 + .../g++.target/riscv/rvv/base/vasub_vx_mu_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vasub_vx_mu_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vasub_vx_mu_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vasub_vx_mu_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vasub_vx_mu_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vasub_vx_mu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vasub_vx_rv32-1.C | 308 + .../g++.target/riscv/rvv/base/vasub_vx_rv32-2.C | 308 + .../g++.target/riscv/rvv/base/vasub_vx_rv32-3.C | 308 + .../g++.target/riscv/rvv/base/vasub_vx_rv64-1.C | 314 + .../g++.target/riscv/rvv/base/vasub_vx_rv64-2.C | 314 + .../g++.target/riscv/rvv/base/vasub_vx_rv64-3.C | 314 + .../g++.target/riscv/rvv/base/vasub_vx_tu_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vasub_vx_tu_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vasub_vx_tu_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vasub_vx_tu_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vasub_vx_tu_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vasub_vx_tu_rv64-3.C | 160 + .../riscv/rvv/base/vasub_vx_tum_rv32-1.C | 157 + .../riscv/rvv/base/vasub_vx_tum_rv32-2.C | 157 + .../riscv/rvv/base/vasub_vx_tum_rv32-3.C | 157 + .../riscv/rvv/base/vasub_vx_tum_rv64-1.C | 160 + .../riscv/rvv/base/vasub_vx_tum_rv64-2.C | 160 + .../riscv/rvv/base/vasub_vx_tum_rv64-3.C | 160 + .../riscv/rvv/base/vasub_vx_tumu_rv32-1.C | 157 + .../riscv/rvv/base/vasub_vx_tumu_rv32-2.C | 157 + .../riscv/rvv/base/vasub_vx_tumu_rv32-3.C | 157 + .../riscv/rvv/base/vasub_vx_tumu_rv64-1.C | 160 + .../riscv/rvv/base/vasub_vx_tumu_rv64-2.C | 160 + .../riscv/rvv/base/vasub_vx_tumu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vasubu_vv-1.C | 314 + .../g++.target/riscv/rvv/base/vasubu_vv-2.C | 314 + .../g++.target/riscv/rvv/base/vasubu_vv-3.C | 314 + .../g++.target/riscv/rvv/base/vasubu_vv_mu-1.C | 160 + .../g++.target/riscv/rvv/base/vasubu_vv_mu-2.C | 160 + .../g++.target/riscv/rvv/base/vasubu_vv_mu-3.C | 160 + .../g++.target/riscv/rvv/base/vasubu_vv_tu-1.C | 160 + .../g++.target/riscv/rvv/base/vasubu_vv_tu-2.C | 160 + .../g++.target/riscv/rvv/base/vasubu_vv_tu-3.C | 160 + .../g++.target/riscv/rvv/base/vasubu_vv_tum-1.C | 160 + .../g++.target/riscv/rvv/base/vasubu_vv_tum-2.C | 160 + .../g++.target/riscv/rvv/base/vasubu_vv_tum-3.C | 160 + .../g++.target/riscv/rvv/base/vasubu_vv_tumu-1.C | 160 + .../g++.target/riscv/rvv/base/vasubu_vv_tumu-2.C | 160 + .../g++.target/riscv/rvv/base/vasubu_vv_tumu-3.C | 160 + .../riscv/rvv/base/vasubu_vx_mu_rv32-1.C | 157 + .../riscv/rvv/base/vasubu_vx_mu_rv32-2.C | 157 + .../riscv/rvv/base/vasubu_vx_mu_rv32-3.C | 157 + .../riscv/rvv/base/vasubu_vx_mu_rv64-1.C | 160 + .../riscv/rvv/base/vasubu_vx_mu_rv64-2.C | 160 + .../riscv/rvv/base/vasubu_vx_mu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vasubu_vx_rv32-1.C | 308 + .../g++.target/riscv/rvv/base/vasubu_vx_rv32-2.C | 308 + .../g++.target/riscv/rvv/base/vasubu_vx_rv32-3.C | 308 + .../g++.target/riscv/rvv/base/vasubu_vx_rv64-1.C | 314 + .../g++.target/riscv/rvv/base/vasubu_vx_rv64-2.C | 314 + .../g++.target/riscv/rvv/base/vasubu_vx_rv64-3.C | 314 + .../riscv/rvv/base/vasubu_vx_tu_rv32-1.C | 157 + .../riscv/rvv/base/vasubu_vx_tu_rv32-2.C | 157 + .../riscv/rvv/base/vasubu_vx_tu_rv32-3.C | 157 + .../riscv/rvv/base/vasubu_vx_tu_rv64-1.C | 160 + .../riscv/rvv/base/vasubu_vx_tu_rv64-2.C | 160 + .../riscv/rvv/base/vasubu_vx_tu_rv64-3.C | 160 + .../riscv/rvv/base/vasubu_vx_tum_rv32-1.C | 157 + .../riscv/rvv/base/vasubu_vx_tum_rv32-2.C | 157 + .../riscv/rvv/base/vasubu_vx_tum_rv32-3.C | 157 + .../riscv/rvv/base/vasubu_vx_tum_rv64-1.C | 160 + .../riscv/rvv/base/vasubu_vx_tum_rv64-2.C | 160 + .../riscv/rvv/base/vasubu_vx_tum_rv64-3.C | 160 + .../riscv/rvv/base/vasubu_vx_tumu_rv32-1.C | 157 + .../riscv/rvv/base/vasubu_vx_tumu_rv32-2.C | 157 + .../riscv/rvv/base/vasubu_vx_tumu_rv32-3.C | 157 + .../riscv/rvv/base/vasubu_vx_tumu_rv64-1.C | 160 + .../riscv/rvv/base/vasubu_vx_tumu_rv64-2.C | 160 + .../riscv/rvv/base/vasubu_vx_tumu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vdiv_vv-1.C | 314 + .../g++.target/riscv/rvv/base/vdiv_vv-2.C | 314 + .../g++.target/riscv/rvv/base/vdiv_vv-3.C | 314 + .../g++.target/riscv/rvv/base/vdiv_vv_mu-1.C | 160 + .../g++.target/riscv/rvv/base/vdiv_vv_mu-2.C | 160 + .../g++.target/riscv/rvv/base/vdiv_vv_mu-3.C | 160 + .../g++.target/riscv/rvv/base/vdiv_vv_tu-1.C | 160 + .../g++.target/riscv/rvv/base/vdiv_vv_tu-2.C | 160 + .../g++.target/riscv/rvv/base/vdiv_vv_tu-3.C | 160 + .../g++.target/riscv/rvv/base/vdiv_vv_tum-1.C | 160 + .../g++.target/riscv/rvv/base/vdiv_vv_tum-2.C | 160 + .../g++.target/riscv/rvv/base/vdiv_vv_tum-3.C | 160 + .../g++.target/riscv/rvv/base/vdiv_vv_tumu-1.C | 160 + .../g++.target/riscv/rvv/base/vdiv_vv_tumu-2.C | 160 + .../g++.target/riscv/rvv/base/vdiv_vv_tumu-3.C | 160 + .../g++.target/riscv/rvv/base/vdiv_vx_mu_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vdiv_vx_mu_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vdiv_vx_mu_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vdiv_vx_mu_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vdiv_vx_mu_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vdiv_vx_mu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vdiv_vx_rv32-1.C | 308 + .../g++.target/riscv/rvv/base/vdiv_vx_rv32-2.C | 308 + .../g++.target/riscv/rvv/base/vdiv_vx_rv32-3.C | 308 + .../g++.target/riscv/rvv/base/vdiv_vx_rv64-1.C | 314 + .../g++.target/riscv/rvv/base/vdiv_vx_rv64-2.C | 314 + .../g++.target/riscv/rvv/base/vdiv_vx_rv64-3.C | 314 + .../g++.target/riscv/rvv/base/vdiv_vx_tu_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vdiv_vx_tu_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vdiv_vx_tu_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vdiv_vx_tu_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vdiv_vx_tu_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vdiv_vx_tu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vdiv_vx_tum_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vdiv_vx_tum_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vdiv_vx_tum_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vdiv_vx_tum_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vdiv_vx_tum_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vdiv_vx_tum_rv64-3.C | 160 + .../riscv/rvv/base/vdiv_vx_tumu_rv32-1.C | 157 + .../riscv/rvv/base/vdiv_vx_tumu_rv32-2.C | 157 + .../riscv/rvv/base/vdiv_vx_tumu_rv32-3.C | 157 + .../riscv/rvv/base/vdiv_vx_tumu_rv64-1.C | 160 + .../riscv/rvv/base/vdiv_vx_tumu_rv64-2.C | 160 + .../riscv/rvv/base/vdiv_vx_tumu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vdivu_vv-1.C | 314 + .../g++.target/riscv/rvv/base/vdivu_vv-2.C | 314 + .../g++.target/riscv/rvv/base/vdivu_vv-3.C | 314 + .../g++.target/riscv/rvv/base/vdivu_vv_mu-1.C | 160 + .../g++.target/riscv/rvv/base/vdivu_vv_mu-2.C | 160 + .../g++.target/riscv/rvv/base/vdivu_vv_mu-3.C | 160 + .../g++.target/riscv/rvv/base/vdivu_vv_tu-1.C | 160 + .../g++.target/riscv/rvv/base/vdivu_vv_tu-2.C | 160 + .../g++.target/riscv/rvv/base/vdivu_vv_tu-3.C | 160 + .../g++.target/riscv/rvv/base/vdivu_vv_tum-1.C | 160 + .../g++.target/riscv/rvv/base/vdivu_vv_tum-2.C | 160 + .../g++.target/riscv/rvv/base/vdivu_vv_tum-3.C | 160 + .../g++.target/riscv/rvv/base/vdivu_vv_tumu-1.C | 160 + .../g++.target/riscv/rvv/base/vdivu_vv_tumu-2.C | 160 + .../g++.target/riscv/rvv/base/vdivu_vv_tumu-3.C | 160 + .../g++.target/riscv/rvv/base/vdivu_vx_mu_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vdivu_vx_mu_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vdivu_vx_mu_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vdivu_vx_mu_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vdivu_vx_mu_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vdivu_vx_mu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vdivu_vx_rv32-1.C | 308 + .../g++.target/riscv/rvv/base/vdivu_vx_rv32-2.C | 308 + .../g++.target/riscv/rvv/base/vdivu_vx_rv32-3.C | 308 + .../g++.target/riscv/rvv/base/vdivu_vx_rv64-1.C | 314 + .../g++.target/riscv/rvv/base/vdivu_vx_rv64-2.C | 314 + .../g++.target/riscv/rvv/base/vdivu_vx_rv64-3.C | 314 + .../g++.target/riscv/rvv/base/vdivu_vx_tu_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vdivu_vx_tu_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vdivu_vx_tu_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vdivu_vx_tu_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vdivu_vx_tu_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vdivu_vx_tu_rv64-3.C | 160 + .../riscv/rvv/base/vdivu_vx_tum_rv32-1.C | 157 + .../riscv/rvv/base/vdivu_vx_tum_rv32-2.C | 157 + .../riscv/rvv/base/vdivu_vx_tum_rv32-3.C | 157 + .../riscv/rvv/base/vdivu_vx_tum_rv64-1.C | 160 + .../riscv/rvv/base/vdivu_vx_tum_rv64-2.C | 160 + .../riscv/rvv/base/vdivu_vx_tum_rv64-3.C | 160 + .../riscv/rvv/base/vdivu_vx_tumu_rv32-1.C | 157 + .../riscv/rvv/base/vdivu_vx_tumu_rv32-2.C | 157 + .../riscv/rvv/base/vdivu_vx_tumu_rv32-3.C | 157 + .../riscv/rvv/base/vdivu_vx_tumu_rv64-1.C | 160 + .../riscv/rvv/base/vdivu_vx_tumu_rv64-2.C | 160 + .../riscv/rvv/base/vdivu_vx_tumu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vmacc_vv-1.C | 578 + .../g++.target/riscv/rvv/base/vmacc_vv-2.C | 578 + .../g++.target/riscv/rvv/base/vmacc_vv-3.C | 578 + .../g++.target/riscv/rvv/base/vmacc_vv_mu-1.C | 292 + .../g++.target/riscv/rvv/base/vmacc_vv_mu-2.C | 292 + .../g++.target/riscv/rvv/base/vmacc_vv_mu-3.C | 292 + .../g++.target/riscv/rvv/base/vmacc_vv_tu-1.C | 292 + .../g++.target/riscv/rvv/base/vmacc_vv_tu-2.C | 292 + .../g++.target/riscv/rvv/base/vmacc_vv_tu-3.C | 292 + .../g++.target/riscv/rvv/base/vmacc_vv_tum-1.C | 292 + .../g++.target/riscv/rvv/base/vmacc_vv_tum-2.C | 292 + .../g++.target/riscv/rvv/base/vmacc_vv_tum-3.C | 292 + .../g++.target/riscv/rvv/base/vmacc_vv_tumu-1.C | 292 + .../g++.target/riscv/rvv/base/vmacc_vv_tumu-2.C | 292 + .../g++.target/riscv/rvv/base/vmacc_vv_tumu-3.C | 292 + .../g++.target/riscv/rvv/base/vmacc_vx_mu_rv32-1.C | 289 + .../g++.target/riscv/rvv/base/vmacc_vx_mu_rv32-2.C | 289 + .../g++.target/riscv/rvv/base/vmacc_vx_mu_rv32-3.C | 289 + .../g++.target/riscv/rvv/base/vmacc_vx_mu_rv64-1.C | 292 + .../g++.target/riscv/rvv/base/vmacc_vx_mu_rv64-2.C | 292 + .../g++.target/riscv/rvv/base/vmacc_vx_mu_rv64-3.C | 292 + .../g++.target/riscv/rvv/base/vmacc_vx_rv32-1.C | 572 + .../g++.target/riscv/rvv/base/vmacc_vx_rv32-2.C | 572 + .../g++.target/riscv/rvv/base/vmacc_vx_rv32-3.C | 572 + .../g++.target/riscv/rvv/base/vmacc_vx_rv64-1.C | 578 + .../g++.target/riscv/rvv/base/vmacc_vx_rv64-2.C | 578 + .../g++.target/riscv/rvv/base/vmacc_vx_rv64-3.C | 578 + .../g++.target/riscv/rvv/base/vmacc_vx_tu_rv32-1.C | 289 + .../g++.target/riscv/rvv/base/vmacc_vx_tu_rv32-2.C | 289 + .../g++.target/riscv/rvv/base/vmacc_vx_tu_rv32-3.C | 289 + .../g++.target/riscv/rvv/base/vmacc_vx_tu_rv64-1.C | 292 + .../g++.target/riscv/rvv/base/vmacc_vx_tu_rv64-2.C | 292 + .../g++.target/riscv/rvv/base/vmacc_vx_tu_rv64-3.C | 292 + .../riscv/rvv/base/vmacc_vx_tum_rv32-1.C | 289 + .../riscv/rvv/base/vmacc_vx_tum_rv32-2.C | 289 + .../riscv/rvv/base/vmacc_vx_tum_rv32-3.C | 289 + .../riscv/rvv/base/vmacc_vx_tum_rv64-1.C | 292 + .../riscv/rvv/base/vmacc_vx_tum_rv64-2.C | 292 + .../riscv/rvv/base/vmacc_vx_tum_rv64-3.C | 292 + .../riscv/rvv/base/vmacc_vx_tumu_rv32-1.C | 289 + .../riscv/rvv/base/vmacc_vx_tumu_rv32-2.C | 289 + .../riscv/rvv/base/vmacc_vx_tumu_rv32-3.C | 289 + .../riscv/rvv/base/vmacc_vx_tumu_rv64-1.C | 292 + .../riscv/rvv/base/vmacc_vx_tumu_rv64-2.C | 292 + .../riscv/rvv/base/vmacc_vx_tumu_rv64-3.C | 292 + .../g++.target/riscv/rvv/base/vmadc_vv-1.C | 292 + .../g++.target/riscv/rvv/base/vmadc_vv-2.C | 292 + .../g++.target/riscv/rvv/base/vmadc_vv-3.C | 292 + .../g++.target/riscv/rvv/base/vmadc_vvm-1.C | 292 + .../g++.target/riscv/rvv/base/vmadc_vvm-2.C | 292 + .../g++.target/riscv/rvv/base/vmadc_vvm-3.C | 292 + .../g++.target/riscv/rvv/base/vmadc_vx_rv32-1.C | 289 + .../g++.target/riscv/rvv/base/vmadc_vx_rv32-2.C | 289 + .../g++.target/riscv/rvv/base/vmadc_vx_rv32-3.C | 289 + .../g++.target/riscv/rvv/base/vmadc_vx_rv64-1.C | 292 + .../g++.target/riscv/rvv/base/vmadc_vx_rv64-2.C | 292 + .../g++.target/riscv/rvv/base/vmadc_vx_rv64-3.C | 292 + .../g++.target/riscv/rvv/base/vmadc_vxm_rv32-1.C | 289 + .../g++.target/riscv/rvv/base/vmadc_vxm_rv32-2.C | 289 + .../g++.target/riscv/rvv/base/vmadc_vxm_rv32-3.C | 289 + .../g++.target/riscv/rvv/base/vmadc_vxm_rv64-1.C | 292 + .../g++.target/riscv/rvv/base/vmadc_vxm_rv64-2.C | 292 + .../g++.target/riscv/rvv/base/vmadc_vxm_rv64-3.C | 292 + .../g++.target/riscv/rvv/base/vmadd_vv-1.C | 578 + .../g++.target/riscv/rvv/base/vmadd_vv-2.C | 578 + .../g++.target/riscv/rvv/base/vmadd_vv-3.C | 578 + .../g++.target/riscv/rvv/base/vmadd_vv_mu-1.C | 292 + .../g++.target/riscv/rvv/base/vmadd_vv_mu-2.C | 292 + .../g++.target/riscv/rvv/base/vmadd_vv_mu-3.C | 292 + .../g++.target/riscv/rvv/base/vmadd_vv_tu-1.C | 292 + .../g++.target/riscv/rvv/base/vmadd_vv_tu-2.C | 292 + .../g++.target/riscv/rvv/base/vmadd_vv_tu-3.C | 292 + .../g++.target/riscv/rvv/base/vmadd_vv_tum-1.C | 292 + .../g++.target/riscv/rvv/base/vmadd_vv_tum-2.C | 292 + .../g++.target/riscv/rvv/base/vmadd_vv_tum-3.C | 292 + .../g++.target/riscv/rvv/base/vmadd_vv_tumu-1.C | 292 + .../g++.target/riscv/rvv/base/vmadd_vv_tumu-2.C | 292 + .../g++.target/riscv/rvv/base/vmadd_vv_tumu-3.C | 292 + .../g++.target/riscv/rvv/base/vmadd_vx_mu_rv64-1.C | 292 + .../g++.target/riscv/rvv/base/vmadd_vx_mu_rv64-2.C | 292 + .../g++.target/riscv/rvv/base/vmadd_vx_mu_rv64-3.C | 292 + .../g++.target/riscv/rvv/base/vmadd_vx_rv64-1.C | 578 + .../g++.target/riscv/rvv/base/vmadd_vx_rv64-2.C | 578 + .../g++.target/riscv/rvv/base/vmadd_vx_rv64-3.C | 578 + .../g++.target/riscv/rvv/base/vmadd_vx_tu_rv64-1.C | 292 + .../g++.target/riscv/rvv/base/vmadd_vx_tu_rv64-2.C | 292 + .../g++.target/riscv/rvv/base/vmadd_vx_tu_rv64-3.C | 292 + .../riscv/rvv/base/vmadd_vx_tum_rv64-1.C | 292 + .../riscv/rvv/base/vmadd_vx_tum_rv64-2.C | 292 + .../riscv/rvv/base/vmadd_vx_tum_rv64-3.C | 292 + .../riscv/rvv/base/vmadd_vx_tumu_rv64-1.C | 292 + .../riscv/rvv/base/vmadd_vx_tumu_rv64-2.C | 292 + .../riscv/rvv/base/vmadd_vx_tumu_rv64-3.C | 292 + .../g++.target/riscv/rvv/base/vmax_vv-1.C | 314 + .../g++.target/riscv/rvv/base/vmax_vv-2.C | 314 + .../g++.target/riscv/rvv/base/vmax_vv-3.C | 314 + .../g++.target/riscv/rvv/base/vmax_vv_mu-1.C | 160 + .../g++.target/riscv/rvv/base/vmax_vv_mu-2.C | 160 + .../g++.target/riscv/rvv/base/vmax_vv_mu-3.C | 160 + .../g++.target/riscv/rvv/base/vmax_vv_tu-1.C | 160 + .../g++.target/riscv/rvv/base/vmax_vv_tu-2.C | 160 + .../g++.target/riscv/rvv/base/vmax_vv_tu-3.C | 160 + .../g++.target/riscv/rvv/base/vmax_vv_tum-1.C | 160 + .../g++.target/riscv/rvv/base/vmax_vv_tum-2.C | 160 + .../g++.target/riscv/rvv/base/vmax_vv_tum-3.C | 160 + .../g++.target/riscv/rvv/base/vmax_vv_tumu-1.C | 160 + .../g++.target/riscv/rvv/base/vmax_vv_tumu-2.C | 160 + .../g++.target/riscv/rvv/base/vmax_vv_tumu-3.C | 160 + .../g++.target/riscv/rvv/base/vmax_vx_mu_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vmax_vx_mu_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vmax_vx_mu_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vmax_vx_mu_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vmax_vx_mu_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vmax_vx_mu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vmax_vx_rv32-1.C | 308 + .../g++.target/riscv/rvv/base/vmax_vx_rv32-2.C | 308 + .../g++.target/riscv/rvv/base/vmax_vx_rv32-3.C | 308 + .../g++.target/riscv/rvv/base/vmax_vx_rv64-1.C | 314 + .../g++.target/riscv/rvv/base/vmax_vx_rv64-2.C | 314 + .../g++.target/riscv/rvv/base/vmax_vx_rv64-3.C | 314 + .../g++.target/riscv/rvv/base/vmax_vx_tu_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vmax_vx_tu_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vmax_vx_tu_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vmax_vx_tu_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vmax_vx_tu_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vmax_vx_tu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vmax_vx_tum_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vmax_vx_tum_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vmax_vx_tum_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vmax_vx_tum_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vmax_vx_tum_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vmax_vx_tum_rv64-3.C | 160 + .../riscv/rvv/base/vmax_vx_tumu_rv32-1.C | 157 + .../riscv/rvv/base/vmax_vx_tumu_rv32-2.C | 157 + .../riscv/rvv/base/vmax_vx_tumu_rv32-3.C | 157 + .../riscv/rvv/base/vmax_vx_tumu_rv64-1.C | 160 + .../riscv/rvv/base/vmax_vx_tumu_rv64-2.C | 160 + .../riscv/rvv/base/vmax_vx_tumu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vmaxu_vv-1.C | 314 + .../g++.target/riscv/rvv/base/vmaxu_vv-2.C | 314 + .../g++.target/riscv/rvv/base/vmaxu_vv-3.C | 314 + .../g++.target/riscv/rvv/base/vmaxu_vv_mu-1.C | 160 + .../g++.target/riscv/rvv/base/vmaxu_vv_mu-2.C | 160 + .../g++.target/riscv/rvv/base/vmaxu_vv_mu-3.C | 160 + .../g++.target/riscv/rvv/base/vmaxu_vv_tu-1.C | 160 + .../g++.target/riscv/rvv/base/vmaxu_vv_tu-2.C | 160 + .../g++.target/riscv/rvv/base/vmaxu_vv_tu-3.C | 160 + .../g++.target/riscv/rvv/base/vmaxu_vv_tum-1.C | 160 + .../g++.target/riscv/rvv/base/vmaxu_vv_tum-2.C | 160 + .../g++.target/riscv/rvv/base/vmaxu_vv_tum-3.C | 160 + .../g++.target/riscv/rvv/base/vmaxu_vv_tumu-1.C | 160 + .../g++.target/riscv/rvv/base/vmaxu_vv_tumu-2.C | 160 + .../g++.target/riscv/rvv/base/vmaxu_vv_tumu-3.C | 160 + .../g++.target/riscv/rvv/base/vmaxu_vx_mu_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vmaxu_vx_mu_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vmaxu_vx_mu_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vmaxu_vx_mu_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vmaxu_vx_mu_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vmaxu_vx_mu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vmaxu_vx_rv32-1.C | 308 + .../g++.target/riscv/rvv/base/vmaxu_vx_rv32-2.C | 308 + .../g++.target/riscv/rvv/base/vmaxu_vx_rv32-3.C | 308 + .../g++.target/riscv/rvv/base/vmaxu_vx_rv64-1.C | 314 + .../g++.target/riscv/rvv/base/vmaxu_vx_rv64-2.C | 314 + .../g++.target/riscv/rvv/base/vmaxu_vx_rv64-3.C | 314 + .../g++.target/riscv/rvv/base/vmaxu_vx_tu_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vmaxu_vx_tu_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vmaxu_vx_tu_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vmaxu_vx_tu_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vmaxu_vx_tu_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vmaxu_vx_tu_rv64-3.C | 160 + .../riscv/rvv/base/vmaxu_vx_tum_rv32-1.C | 157 + .../riscv/rvv/base/vmaxu_vx_tum_rv32-2.C | 157 + .../riscv/rvv/base/vmaxu_vx_tum_rv32-3.C | 157 + .../riscv/rvv/base/vmaxu_vx_tum_rv64-1.C | 160 + .../riscv/rvv/base/vmaxu_vx_tum_rv64-2.C | 160 + .../riscv/rvv/base/vmaxu_vx_tum_rv64-3.C | 160 + .../riscv/rvv/base/vmaxu_vx_tumu_rv32-1.C | 157 + .../riscv/rvv/base/vmaxu_vx_tumu_rv32-2.C | 157 + .../riscv/rvv/base/vmaxu_vx_tumu_rv32-3.C | 157 + .../riscv/rvv/base/vmaxu_vx_tumu_rv64-1.C | 160 + .../riscv/rvv/base/vmaxu_vx_tumu_rv64-2.C | 160 + .../riscv/rvv/base/vmaxu_vx_tumu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vmerge_vvm-1.C | 292 + .../g++.target/riscv/rvv/base/vmerge_vvm-2.C | 292 + .../g++.target/riscv/rvv/base/vmerge_vvm-3.C | 292 + .../g++.target/riscv/rvv/base/vmerge_vvm-4.C | 292 + .../g++.target/riscv/rvv/base/vmerge_vvm-5.C | 292 + .../g++.target/riscv/rvv/base/vmerge_vvm-6.C | 292 + .../g++.target/riscv/rvv/base/vmerge_vvm_tu-1.C | 292 + .../g++.target/riscv/rvv/base/vmerge_vvm_tu-2.C | 292 + .../g++.target/riscv/rvv/base/vmerge_vvm_tu-3.C | 292 + .../g++.target/riscv/rvv/base/vmerge_vvm_tu-4.C | 292 + .../g++.target/riscv/rvv/base/vmerge_vvm_tu-5.C | 292 + .../g++.target/riscv/rvv/base/vmerge_vvm_tu-6.C | 292 + .../g++.target/riscv/rvv/base/vmerge_vxm_rv32-1.C | 289 + .../g++.target/riscv/rvv/base/vmerge_vxm_rv32-2.C | 289 + .../g++.target/riscv/rvv/base/vmerge_vxm_rv32-3.C | 289 + .../g++.target/riscv/rvv/base/vmerge_vxm_rv64-1.C | 292 + .../g++.target/riscv/rvv/base/vmerge_vxm_rv64-2.C | 292 + .../g++.target/riscv/rvv/base/vmerge_vxm_rv64-3.C | 292 + .../riscv/rvv/base/vmerge_vxm_tu_rv32-1.C | 289 + .../riscv/rvv/base/vmerge_vxm_tu_rv32-2.C | 289 + .../riscv/rvv/base/vmerge_vxm_tu_rv32-3.C | 289 + .../riscv/rvv/base/vmerge_vxm_tu_rv64-1.C | 292 + .../riscv/rvv/base/vmerge_vxm_tu_rv64-2.C | 292 + .../riscv/rvv/base/vmerge_vxm_tu_rv64-3.C | 292 + .../g++.target/riscv/rvv/base/vmin_vv-1.C | 314 + .../g++.target/riscv/rvv/base/vmin_vv-2.C | 314 + .../g++.target/riscv/rvv/base/vmin_vv-3.C | 314 + .../g++.target/riscv/rvv/base/vmin_vv_mu-1.C | 160 + .../g++.target/riscv/rvv/base/vmin_vv_mu-2.C | 160 + .../g++.target/riscv/rvv/base/vmin_vv_mu-3.C | 160 + .../g++.target/riscv/rvv/base/vmin_vv_tu-1.C | 160 + .../g++.target/riscv/rvv/base/vmin_vv_tu-2.C | 160 + .../g++.target/riscv/rvv/base/vmin_vv_tu-3.C | 160 + .../g++.target/riscv/rvv/base/vmin_vv_tum-1.C | 160 + .../g++.target/riscv/rvv/base/vmin_vv_tum-2.C | 160 + .../g++.target/riscv/rvv/base/vmin_vv_tum-3.C | 160 + .../g++.target/riscv/rvv/base/vmin_vv_tumu-1.C | 160 + .../g++.target/riscv/rvv/base/vmin_vv_tumu-2.C | 160 + .../g++.target/riscv/rvv/base/vmin_vv_tumu-3.C | 160 + .../g++.target/riscv/rvv/base/vmin_vx_mu_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vmin_vx_mu_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vmin_vx_mu_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vmin_vx_mu_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vmin_vx_mu_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vmin_vx_mu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vmin_vx_rv32-1.C | 308 + .../g++.target/riscv/rvv/base/vmin_vx_rv32-2.C | 308 + .../g++.target/riscv/rvv/base/vmin_vx_rv32-3.C | 308 + .../g++.target/riscv/rvv/base/vmin_vx_rv64-1.C | 314 + .../g++.target/riscv/rvv/base/vmin_vx_rv64-2.C | 314 + .../g++.target/riscv/rvv/base/vmin_vx_rv64-3.C | 314 + .../g++.target/riscv/rvv/base/vmin_vx_tu_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vmin_vx_tu_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vmin_vx_tu_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vmin_vx_tu_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vmin_vx_tu_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vmin_vx_tu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vmin_vx_tum_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vmin_vx_tum_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vmin_vx_tum_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vmin_vx_tum_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vmin_vx_tum_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vmin_vx_tum_rv64-3.C | 160 + .../riscv/rvv/base/vmin_vx_tumu_rv32-1.C | 157 + .../riscv/rvv/base/vmin_vx_tumu_rv32-2.C | 157 + .../riscv/rvv/base/vmin_vx_tumu_rv32-3.C | 157 + .../riscv/rvv/base/vmin_vx_tumu_rv64-1.C | 160 + .../riscv/rvv/base/vmin_vx_tumu_rv64-2.C | 160 + .../riscv/rvv/base/vmin_vx_tumu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vminu_vv-1.C | 314 + .../g++.target/riscv/rvv/base/vminu_vv-2.C | 314 + .../g++.target/riscv/rvv/base/vminu_vv-3.C | 314 + .../g++.target/riscv/rvv/base/vminu_vv_mu-1.C | 160 + .../g++.target/riscv/rvv/base/vminu_vv_mu-2.C | 160 + .../g++.target/riscv/rvv/base/vminu_vv_mu-3.C | 160 + .../g++.target/riscv/rvv/base/vminu_vv_tu-1.C | 160 + .../g++.target/riscv/rvv/base/vminu_vv_tu-2.C | 160 + .../g++.target/riscv/rvv/base/vminu_vv_tu-3.C | 160 + .../g++.target/riscv/rvv/base/vminu_vv_tum-1.C | 160 + .../g++.target/riscv/rvv/base/vminu_vv_tum-2.C | 160 + .../g++.target/riscv/rvv/base/vminu_vv_tum-3.C | 160 + .../g++.target/riscv/rvv/base/vminu_vv_tumu-1.C | 160 + .../g++.target/riscv/rvv/base/vminu_vv_tumu-2.C | 160 + .../g++.target/riscv/rvv/base/vminu_vv_tumu-3.C | 160 + .../g++.target/riscv/rvv/base/vminu_vx_mu_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vminu_vx_mu_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vminu_vx_mu_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vminu_vx_mu_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vminu_vx_mu_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vminu_vx_mu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vminu_vx_rv32-1.C | 308 + .../g++.target/riscv/rvv/base/vminu_vx_rv32-2.C | 308 + .../g++.target/riscv/rvv/base/vminu_vx_rv32-3.C | 308 + .../g++.target/riscv/rvv/base/vminu_vx_rv64-1.C | 314 + .../g++.target/riscv/rvv/base/vminu_vx_rv64-2.C | 314 + .../g++.target/riscv/rvv/base/vminu_vx_rv64-3.C | 314 + .../g++.target/riscv/rvv/base/vminu_vx_tu_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vminu_vx_tu_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vminu_vx_tu_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vminu_vx_tu_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vminu_vx_tu_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vminu_vx_tu_rv64-3.C | 160 + .../riscv/rvv/base/vminu_vx_tum_rv32-1.C | 157 + .../riscv/rvv/base/vminu_vx_tum_rv32-2.C | 157 + .../riscv/rvv/base/vminu_vx_tum_rv32-3.C | 157 + .../riscv/rvv/base/vminu_vx_tum_rv64-1.C | 160 + .../riscv/rvv/base/vminu_vx_tum_rv64-2.C | 160 + .../riscv/rvv/base/vminu_vx_tum_rv64-3.C | 160 + .../riscv/rvv/base/vminu_vx_tumu_rv32-1.C | 157 + .../riscv/rvv/base/vminu_vx_tumu_rv32-2.C | 157 + .../riscv/rvv/base/vminu_vx_tumu_rv32-3.C | 157 + .../riscv/rvv/base/vminu_vx_tumu_rv64-1.C | 160 + .../riscv/rvv/base/vminu_vx_tumu_rv64-2.C | 160 + .../riscv/rvv/base/vminu_vx_tumu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vmsbc_vv-1.C | 292 + .../g++.target/riscv/rvv/base/vmsbc_vv-2.C | 292 + .../g++.target/riscv/rvv/base/vmsbc_vv-3.C | 292 + .../g++.target/riscv/rvv/base/vmsbc_vvm-1.C | 292 + .../g++.target/riscv/rvv/base/vmsbc_vvm-2.C | 292 + .../g++.target/riscv/rvv/base/vmsbc_vvm-3.C | 292 + .../g++.target/riscv/rvv/base/vmsbc_vx_rv32-1.C | 289 + .../g++.target/riscv/rvv/base/vmsbc_vx_rv32-2.C | 289 + .../g++.target/riscv/rvv/base/vmsbc_vx_rv32-3.C | 289 + .../g++.target/riscv/rvv/base/vmsbc_vx_rv64-1.C | 292 + .../g++.target/riscv/rvv/base/vmsbc_vx_rv64-2.C | 292 + .../g++.target/riscv/rvv/base/vmsbc_vx_rv64-3.C | 292 + .../g++.target/riscv/rvv/base/vmsbc_vxm_rv32-1.C | 289 + .../g++.target/riscv/rvv/base/vmsbc_vxm_rv32-2.C | 289 + .../g++.target/riscv/rvv/base/vmsbc_vxm_rv32-3.C | 289 + .../g++.target/riscv/rvv/base/vmsbc_vxm_rv64-1.C | 292 + .../g++.target/riscv/rvv/base/vmsbc_vxm_rv64-2.C | 292 + .../g++.target/riscv/rvv/base/vmsbc_vxm_rv64-3.C | 292 + .../g++.target/riscv/rvv/base/vmseq_vv-1.C | 292 + .../g++.target/riscv/rvv/base/vmseq_vv-2.C | 292 + .../g++.target/riscv/rvv/base/vmseq_vv-3.C | 292 + .../g++.target/riscv/rvv/base/vmseq_vv_m-1.C | 292 + .../g++.target/riscv/rvv/base/vmseq_vv_m-2.C | 292 + .../g++.target/riscv/rvv/base/vmseq_vv_m-3.C | 292 + .../g++.target/riscv/rvv/base/vmseq_vv_mu-1.C | 292 + .../g++.target/riscv/rvv/base/vmseq_vv_mu-2.C | 292 + .../g++.target/riscv/rvv/base/vmseq_vv_mu-3.C | 292 + .../g++.target/riscv/rvv/base/vmseq_vx_m_rv32-1.C | 289 + .../g++.target/riscv/rvv/base/vmseq_vx_m_rv32-2.C | 289 + .../g++.target/riscv/rvv/base/vmseq_vx_m_rv32-3.C | 289 + .../g++.target/riscv/rvv/base/vmseq_vx_m_rv64-1.C | 292 + .../g++.target/riscv/rvv/base/vmseq_vx_m_rv64-2.C | 292 + .../g++.target/riscv/rvv/base/vmseq_vx_m_rv64-3.C | 292 + .../g++.target/riscv/rvv/base/vmseq_vx_mu_rv32-1.C | 289 + .../g++.target/riscv/rvv/base/vmseq_vx_mu_rv32-2.C | 289 + .../g++.target/riscv/rvv/base/vmseq_vx_mu_rv32-3.C | 289 + .../g++.target/riscv/rvv/base/vmseq_vx_mu_rv64-1.C | 292 + .../g++.target/riscv/rvv/base/vmseq_vx_mu_rv64-2.C | 292 + .../g++.target/riscv/rvv/base/vmseq_vx_mu_rv64-3.C | 292 + .../g++.target/riscv/rvv/base/vmseq_vx_rv32-1.C | 289 + .../g++.target/riscv/rvv/base/vmseq_vx_rv32-2.C | 289 + .../g++.target/riscv/rvv/base/vmseq_vx_rv32-3.C | 289 + .../g++.target/riscv/rvv/base/vmseq_vx_rv64-1.C | 292 + .../g++.target/riscv/rvv/base/vmseq_vx_rv64-2.C | 292 + .../g++.target/riscv/rvv/base/vmseq_vx_rv64-3.C | 292 + .../g++.target/riscv/rvv/base/vmsge_vv-1.C | 160 + .../g++.target/riscv/rvv/base/vmsge_vv-2.C | 160 + .../g++.target/riscv/rvv/base/vmsge_vv-3.C | 160 + .../g++.target/riscv/rvv/base/vmsge_vv_m-1.C | 160 + .../g++.target/riscv/rvv/base/vmsge_vv_m-2.C | 160 + .../g++.target/riscv/rvv/base/vmsge_vv_m-3.C | 160 + .../g++.target/riscv/rvv/base/vmsge_vv_mu-1.C | 160 + .../g++.target/riscv/rvv/base/vmsge_vv_mu-2.C | 160 + .../g++.target/riscv/rvv/base/vmsge_vv_mu-3.C | 160 + .../g++.target/riscv/rvv/base/vmsge_vx_m_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vmsge_vx_m_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vmsge_vx_m_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vmsge_vx_m_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vmsge_vx_m_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vmsge_vx_m_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vmsge_vx_mu_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vmsge_vx_mu_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vmsge_vx_mu_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vmsge_vx_mu_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vmsge_vx_mu_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vmsge_vx_mu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vmsge_vx_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vmsge_vx_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vmsge_vx_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vmsge_vx_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vmsge_vx_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vmsge_vx_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vmsgeu_vv-1.C | 160 + .../g++.target/riscv/rvv/base/vmsgeu_vv-2.C | 160 + .../g++.target/riscv/rvv/base/vmsgeu_vv-3.C | 160 + .../g++.target/riscv/rvv/base/vmsgeu_vv_m-1.C | 160 + .../g++.target/riscv/rvv/base/vmsgeu_vv_m-2.C | 160 + .../g++.target/riscv/rvv/base/vmsgeu_vv_m-3.C | 160 + .../g++.target/riscv/rvv/base/vmsgeu_vv_mu-1.C | 160 + .../g++.target/riscv/rvv/base/vmsgeu_vv_mu-2.C | 160 + .../g++.target/riscv/rvv/base/vmsgeu_vv_mu-3.C | 160 + .../g++.target/riscv/rvv/base/vmsgeu_vx_m_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vmsgeu_vx_m_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vmsgeu_vx_m_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vmsgeu_vx_m_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vmsgeu_vx_m_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vmsgeu_vx_m_rv64-3.C | 160 + .../riscv/rvv/base/vmsgeu_vx_mu_rv32-1.C | 157 + .../riscv/rvv/base/vmsgeu_vx_mu_rv32-2.C | 157 + .../riscv/rvv/base/vmsgeu_vx_mu_rv32-3.C | 157 + .../riscv/rvv/base/vmsgeu_vx_mu_rv64-1.C | 160 + .../riscv/rvv/base/vmsgeu_vx_mu_rv64-2.C | 160 + .../riscv/rvv/base/vmsgeu_vx_mu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vmsgeu_vx_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vmsgeu_vx_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vmsgeu_vx_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vmsgeu_vx_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vmsgeu_vx_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vmsgeu_vx_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vmsgt_vv-1.C | 160 + .../g++.target/riscv/rvv/base/vmsgt_vv-2.C | 160 + .../g++.target/riscv/rvv/base/vmsgt_vv-3.C | 160 + .../g++.target/riscv/rvv/base/vmsgt_vv_m-1.C | 160 + .../g++.target/riscv/rvv/base/vmsgt_vv_m-2.C | 160 + .../g++.target/riscv/rvv/base/vmsgt_vv_m-3.C | 160 + .../g++.target/riscv/rvv/base/vmsgt_vv_mu-1.C | 160 + .../g++.target/riscv/rvv/base/vmsgt_vv_mu-2.C | 160 + .../g++.target/riscv/rvv/base/vmsgt_vv_mu-3.C | 160 + .../g++.target/riscv/rvv/base/vmsgt_vx_m_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vmsgt_vx_m_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vmsgt_vx_m_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vmsgt_vx_m_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vmsgt_vx_m_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vmsgt_vx_m_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vmsgt_vx_mu_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vmsgt_vx_mu_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vmsgt_vx_mu_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vmsgt_vx_mu_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vmsgt_vx_mu_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vmsgt_vx_mu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vmsgt_vx_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vmsgt_vx_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vmsgt_vx_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vmsgt_vx_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vmsgt_vx_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vmsgt_vx_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vmsgtu_vv-1.C | 160 + .../g++.target/riscv/rvv/base/vmsgtu_vv-2.C | 160 + .../g++.target/riscv/rvv/base/vmsgtu_vv-3.C | 160 + .../g++.target/riscv/rvv/base/vmsgtu_vv_m-1.C | 160 + .../g++.target/riscv/rvv/base/vmsgtu_vv_m-2.C | 160 + .../g++.target/riscv/rvv/base/vmsgtu_vv_m-3.C | 160 + .../g++.target/riscv/rvv/base/vmsgtu_vv_mu-1.C | 160 + .../g++.target/riscv/rvv/base/vmsgtu_vv_mu-2.C | 160 + .../g++.target/riscv/rvv/base/vmsgtu_vv_mu-3.C | 160 + .../g++.target/riscv/rvv/base/vmsgtu_vx_m_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vmsgtu_vx_m_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vmsgtu_vx_m_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vmsgtu_vx_m_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vmsgtu_vx_m_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vmsgtu_vx_m_rv64-3.C | 160 + .../riscv/rvv/base/vmsgtu_vx_mu_rv32-1.C | 157 + .../riscv/rvv/base/vmsgtu_vx_mu_rv32-2.C | 157 + .../riscv/rvv/base/vmsgtu_vx_mu_rv32-3.C | 157 + .../riscv/rvv/base/vmsgtu_vx_mu_rv64-1.C | 160 + .../riscv/rvv/base/vmsgtu_vx_mu_rv64-2.C | 160 + .../riscv/rvv/base/vmsgtu_vx_mu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vmsgtu_vx_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vmsgtu_vx_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vmsgtu_vx_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vmsgtu_vx_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vmsgtu_vx_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vmsgtu_vx_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vmsle_vv-1.C | 160 + .../g++.target/riscv/rvv/base/vmsle_vv-2.C | 160 + .../g++.target/riscv/rvv/base/vmsle_vv-3.C | 160 + .../g++.target/riscv/rvv/base/vmsle_vv_m-1.C | 160 + .../g++.target/riscv/rvv/base/vmsle_vv_m-2.C | 160 + .../g++.target/riscv/rvv/base/vmsle_vv_m-3.C | 160 + .../g++.target/riscv/rvv/base/vmsle_vv_mu-1.C | 160 + .../g++.target/riscv/rvv/base/vmsle_vv_mu-2.C | 160 + .../g++.target/riscv/rvv/base/vmsle_vv_mu-3.C | 160 + .../g++.target/riscv/rvv/base/vmsle_vx_m_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vmsle_vx_m_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vmsle_vx_m_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vmsle_vx_m_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vmsle_vx_m_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vmsle_vx_m_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vmsle_vx_mu_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vmsle_vx_mu_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vmsle_vx_mu_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vmsle_vx_mu_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vmsle_vx_mu_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vmsle_vx_mu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vmsle_vx_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vmsle_vx_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vmsle_vx_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vmsle_vx_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vmsle_vx_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vmsle_vx_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vmsleu_vv-1.C | 160 + .../g++.target/riscv/rvv/base/vmsleu_vv-2.C | 160 + .../g++.target/riscv/rvv/base/vmsleu_vv-3.C | 160 + .../g++.target/riscv/rvv/base/vmsleu_vv_m-1.C | 160 + .../g++.target/riscv/rvv/base/vmsleu_vv_m-2.C | 160 + .../g++.target/riscv/rvv/base/vmsleu_vv_m-3.C | 160 + .../g++.target/riscv/rvv/base/vmsleu_vv_mu-1.C | 160 + .../g++.target/riscv/rvv/base/vmsleu_vv_mu-2.C | 160 + .../g++.target/riscv/rvv/base/vmsleu_vv_mu-3.C | 160 + .../g++.target/riscv/rvv/base/vmsleu_vx_m_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vmsleu_vx_m_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vmsleu_vx_m_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vmsleu_vx_m_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vmsleu_vx_m_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vmsleu_vx_m_rv64-3.C | 160 + .../riscv/rvv/base/vmsleu_vx_mu_rv32-1.C | 157 + .../riscv/rvv/base/vmsleu_vx_mu_rv32-2.C | 157 + .../riscv/rvv/base/vmsleu_vx_mu_rv32-3.C | 157 + .../riscv/rvv/base/vmsleu_vx_mu_rv64-1.C | 160 + .../riscv/rvv/base/vmsleu_vx_mu_rv64-2.C | 160 + .../riscv/rvv/base/vmsleu_vx_mu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vmsleu_vx_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vmsleu_vx_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vmsleu_vx_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vmsleu_vx_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vmsleu_vx_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vmsleu_vx_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vmslt_vv-1.C | 160 + .../g++.target/riscv/rvv/base/vmslt_vv-2.C | 160 + .../g++.target/riscv/rvv/base/vmslt_vv-3.C | 160 + .../g++.target/riscv/rvv/base/vmslt_vv_m-1.C | 160 + .../g++.target/riscv/rvv/base/vmslt_vv_m-2.C | 160 + .../g++.target/riscv/rvv/base/vmslt_vv_m-3.C | 160 + .../g++.target/riscv/rvv/base/vmslt_vv_mu-1.C | 160 + .../g++.target/riscv/rvv/base/vmslt_vv_mu-2.C | 160 + .../g++.target/riscv/rvv/base/vmslt_vv_mu-3.C | 160 + .../g++.target/riscv/rvv/base/vmslt_vx_m_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vmslt_vx_m_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vmslt_vx_m_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vmslt_vx_m_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vmslt_vx_m_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vmslt_vx_m_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vmslt_vx_mu_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vmslt_vx_mu_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vmslt_vx_mu_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vmslt_vx_mu_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vmslt_vx_mu_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vmslt_vx_mu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vmslt_vx_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vmslt_vx_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vmslt_vx_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vmslt_vx_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vmslt_vx_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vmslt_vx_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vmsltu_vv-1.C | 160 + .../g++.target/riscv/rvv/base/vmsltu_vv-2.C | 160 + .../g++.target/riscv/rvv/base/vmsltu_vv-3.C | 160 + .../g++.target/riscv/rvv/base/vmsltu_vv_m-1.C | 160 + .../g++.target/riscv/rvv/base/vmsltu_vv_m-2.C | 160 + .../g++.target/riscv/rvv/base/vmsltu_vv_m-3.C | 160 + .../g++.target/riscv/rvv/base/vmsltu_vv_mu-1.C | 160 + .../g++.target/riscv/rvv/base/vmsltu_vv_mu-2.C | 160 + .../g++.target/riscv/rvv/base/vmsltu_vv_mu-3.C | 160 + .../g++.target/riscv/rvv/base/vmsltu_vx_m_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vmsltu_vx_m_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vmsltu_vx_m_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vmsltu_vx_m_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vmsltu_vx_m_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vmsltu_vx_m_rv64-3.C | 160 + .../riscv/rvv/base/vmsltu_vx_mu_rv32-1.C | 157 + .../riscv/rvv/base/vmsltu_vx_mu_rv32-2.C | 157 + .../riscv/rvv/base/vmsltu_vx_mu_rv32-3.C | 157 + .../riscv/rvv/base/vmsltu_vx_mu_rv64-1.C | 160 + .../riscv/rvv/base/vmsltu_vx_mu_rv64-2.C | 160 + .../riscv/rvv/base/vmsltu_vx_mu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vmsltu_vx_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vmsltu_vx_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vmsltu_vx_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vmsltu_vx_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vmsltu_vx_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vmsltu_vx_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vmsne_vv-1.C | 292 + .../g++.target/riscv/rvv/base/vmsne_vv-2.C | 292 + .../g++.target/riscv/rvv/base/vmsne_vv-3.C | 292 + .../g++.target/riscv/rvv/base/vmsne_vv_m-1.C | 292 + .../g++.target/riscv/rvv/base/vmsne_vv_m-2.C | 292 + .../g++.target/riscv/rvv/base/vmsne_vv_m-3.C | 292 + .../g++.target/riscv/rvv/base/vmsne_vv_mu-1.C | 292 + .../g++.target/riscv/rvv/base/vmsne_vv_mu-2.C | 292 + .../g++.target/riscv/rvv/base/vmsne_vv_mu-3.C | 292 + .../g++.target/riscv/rvv/base/vmsne_vx_m_rv32-1.C | 289 + .../g++.target/riscv/rvv/base/vmsne_vx_m_rv32-2.C | 289 + .../g++.target/riscv/rvv/base/vmsne_vx_m_rv32-3.C | 289 + .../g++.target/riscv/rvv/base/vmsne_vx_m_rv64-1.C | 292 + .../g++.target/riscv/rvv/base/vmsne_vx_m_rv64-2.C | 292 + .../g++.target/riscv/rvv/base/vmsne_vx_m_rv64-3.C | 292 + .../g++.target/riscv/rvv/base/vmsne_vx_mu_rv32-1.C | 289 + .../g++.target/riscv/rvv/base/vmsne_vx_mu_rv32-2.C | 289 + .../g++.target/riscv/rvv/base/vmsne_vx_mu_rv32-3.C | 289 + .../g++.target/riscv/rvv/base/vmsne_vx_mu_rv64-1.C | 292 + .../g++.target/riscv/rvv/base/vmsne_vx_mu_rv64-2.C | 292 + .../g++.target/riscv/rvv/base/vmsne_vx_mu_rv64-3.C | 292 + .../g++.target/riscv/rvv/base/vmsne_vx_rv32-1.C | 289 + .../g++.target/riscv/rvv/base/vmsne_vx_rv32-2.C | 289 + .../g++.target/riscv/rvv/base/vmsne_vx_rv32-3.C | 289 + .../g++.target/riscv/rvv/base/vmsne_vx_rv64-1.C | 292 + .../g++.target/riscv/rvv/base/vmsne_vx_rv64-2.C | 292 + .../g++.target/riscv/rvv/base/vmsne_vx_rv64-3.C | 292 + .../g++.target/riscv/rvv/base/vmul_vv-1.C | 578 + .../g++.target/riscv/rvv/base/vmul_vv-2.C | 578 + .../g++.target/riscv/rvv/base/vmul_vv-3.C | 578 + .../g++.target/riscv/rvv/base/vmul_vv_mu-1.C | 292 + .../g++.target/riscv/rvv/base/vmul_vv_mu-2.C | 292 + .../g++.target/riscv/rvv/base/vmul_vv_mu-3.C | 292 + .../g++.target/riscv/rvv/base/vmul_vv_tu-1.C | 292 + .../g++.target/riscv/rvv/base/vmul_vv_tu-2.C | 292 + .../g++.target/riscv/rvv/base/vmul_vv_tu-3.C | 292 + .../g++.target/riscv/rvv/base/vmul_vv_tum-1.C | 292 + .../g++.target/riscv/rvv/base/vmul_vv_tum-2.C | 292 + .../g++.target/riscv/rvv/base/vmul_vv_tum-3.C | 292 + .../g++.target/riscv/rvv/base/vmul_vv_tumu-1.C | 292 + .../g++.target/riscv/rvv/base/vmul_vv_tumu-2.C | 292 + .../g++.target/riscv/rvv/base/vmul_vv_tumu-3.C | 292 + .../g++.target/riscv/rvv/base/vmul_vx_mu_rv32-1.C | 289 + .../g++.target/riscv/rvv/base/vmul_vx_mu_rv32-2.C | 289 + .../g++.target/riscv/rvv/base/vmul_vx_mu_rv32-3.C | 289 + .../g++.target/riscv/rvv/base/vmul_vx_mu_rv64-1.C | 292 + .../g++.target/riscv/rvv/base/vmul_vx_mu_rv64-2.C | 292 + .../g++.target/riscv/rvv/base/vmul_vx_mu_rv64-3.C | 292 + .../g++.target/riscv/rvv/base/vmul_vx_rv32-1.C | 572 + .../g++.target/riscv/rvv/base/vmul_vx_rv32-2.C | 572 + .../g++.target/riscv/rvv/base/vmul_vx_rv32-3.C | 572 + .../g++.target/riscv/rvv/base/vmul_vx_rv64-1.C | 578 + .../g++.target/riscv/rvv/base/vmul_vx_rv64-2.C | 578 + .../g++.target/riscv/rvv/base/vmul_vx_rv64-3.C | 578 + .../g++.target/riscv/rvv/base/vmul_vx_tu_rv32-1.C | 289 + .../g++.target/riscv/rvv/base/vmul_vx_tu_rv32-2.C | 289 + .../g++.target/riscv/rvv/base/vmul_vx_tu_rv32-3.C | 289 + .../g++.target/riscv/rvv/base/vmul_vx_tu_rv64-1.C | 292 + .../g++.target/riscv/rvv/base/vmul_vx_tu_rv64-2.C | 292 + .../g++.target/riscv/rvv/base/vmul_vx_tu_rv64-3.C | 292 + .../g++.target/riscv/rvv/base/vmul_vx_tum_rv32-1.C | 289 + .../g++.target/riscv/rvv/base/vmul_vx_tum_rv32-2.C | 289 + .../g++.target/riscv/rvv/base/vmul_vx_tum_rv32-3.C | 289 + .../g++.target/riscv/rvv/base/vmul_vx_tum_rv64-1.C | 292 + .../g++.target/riscv/rvv/base/vmul_vx_tum_rv64-2.C | 292 + .../g++.target/riscv/rvv/base/vmul_vx_tum_rv64-3.C | 292 + .../riscv/rvv/base/vmul_vx_tumu_rv32-1.C | 289 + .../riscv/rvv/base/vmul_vx_tumu_rv32-2.C | 289 + .../riscv/rvv/base/vmul_vx_tumu_rv32-3.C | 289 + .../riscv/rvv/base/vmul_vx_tumu_rv64-1.C | 292 + .../riscv/rvv/base/vmul_vx_tumu_rv64-2.C | 292 + .../riscv/rvv/base/vmul_vx_tumu_rv64-3.C | 292 + .../g++.target/riscv/rvv/base/vmulh_vv-1.C | 314 + .../g++.target/riscv/rvv/base/vmulh_vv-2.C | 314 + .../g++.target/riscv/rvv/base/vmulh_vv-3.C | 314 + .../g++.target/riscv/rvv/base/vmulh_vv_mu-1.C | 160 + .../g++.target/riscv/rvv/base/vmulh_vv_mu-2.C | 160 + .../g++.target/riscv/rvv/base/vmulh_vv_mu-3.C | 160 + .../g++.target/riscv/rvv/base/vmulh_vv_tu-1.C | 160 + .../g++.target/riscv/rvv/base/vmulh_vv_tu-2.C | 160 + .../g++.target/riscv/rvv/base/vmulh_vv_tu-3.C | 160 + .../g++.target/riscv/rvv/base/vmulh_vv_tum-1.C | 160 + .../g++.target/riscv/rvv/base/vmulh_vv_tum-2.C | 160 + .../g++.target/riscv/rvv/base/vmulh_vv_tum-3.C | 160 + .../g++.target/riscv/rvv/base/vmulh_vv_tumu-1.C | 160 + .../g++.target/riscv/rvv/base/vmulh_vv_tumu-2.C | 160 + .../g++.target/riscv/rvv/base/vmulh_vv_tumu-3.C | 160 + .../g++.target/riscv/rvv/base/vmulh_vx_mu_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vmulh_vx_mu_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vmulh_vx_mu_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vmulh_vx_mu_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vmulh_vx_mu_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vmulh_vx_mu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vmulh_vx_rv32-1.C | 308 + .../g++.target/riscv/rvv/base/vmulh_vx_rv32-2.C | 308 + .../g++.target/riscv/rvv/base/vmulh_vx_rv32-3.C | 308 + .../g++.target/riscv/rvv/base/vmulh_vx_rv64-1.C | 314 + .../g++.target/riscv/rvv/base/vmulh_vx_rv64-2.C | 314 + .../g++.target/riscv/rvv/base/vmulh_vx_rv64-3.C | 314 + .../g++.target/riscv/rvv/base/vmulh_vx_tu_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vmulh_vx_tu_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vmulh_vx_tu_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vmulh_vx_tu_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vmulh_vx_tu_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vmulh_vx_tu_rv64-3.C | 160 + .../riscv/rvv/base/vmulh_vx_tum_rv32-1.C | 157 + .../riscv/rvv/base/vmulh_vx_tum_rv32-2.C | 157 + .../riscv/rvv/base/vmulh_vx_tum_rv32-3.C | 157 + .../riscv/rvv/base/vmulh_vx_tum_rv64-1.C | 160 + .../riscv/rvv/base/vmulh_vx_tum_rv64-2.C | 160 + .../riscv/rvv/base/vmulh_vx_tum_rv64-3.C | 160 + .../riscv/rvv/base/vmulh_vx_tumu_rv32-1.C | 157 + .../riscv/rvv/base/vmulh_vx_tumu_rv32-2.C | 157 + .../riscv/rvv/base/vmulh_vx_tumu_rv32-3.C | 157 + .../riscv/rvv/base/vmulh_vx_tumu_rv64-1.C | 160 + .../riscv/rvv/base/vmulh_vx_tumu_rv64-2.C | 160 + .../riscv/rvv/base/vmulh_vx_tumu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vmulhsu_vv-1.C | 314 + .../g++.target/riscv/rvv/base/vmulhsu_vv-2.C | 314 + .../g++.target/riscv/rvv/base/vmulhsu_vv-3.C | 314 + .../g++.target/riscv/rvv/base/vmulhsu_vv_mu-1.C | 160 + .../g++.target/riscv/rvv/base/vmulhsu_vv_mu-2.C | 160 + .../g++.target/riscv/rvv/base/vmulhsu_vv_mu-3.C | 160 + .../g++.target/riscv/rvv/base/vmulhsu_vv_tu-1.C | 160 + .../g++.target/riscv/rvv/base/vmulhsu_vv_tu-2.C | 160 + .../g++.target/riscv/rvv/base/vmulhsu_vv_tu-3.C | 160 + .../g++.target/riscv/rvv/base/vmulhsu_vv_tum-1.C | 160 + .../g++.target/riscv/rvv/base/vmulhsu_vv_tum-2.C | 160 + .../g++.target/riscv/rvv/base/vmulhsu_vv_tum-3.C | 160 + .../g++.target/riscv/rvv/base/vmulhsu_vv_tumu-1.C | 160 + .../g++.target/riscv/rvv/base/vmulhsu_vv_tumu-2.C | 160 + .../g++.target/riscv/rvv/base/vmulhsu_vv_tumu-3.C | 160 + .../riscv/rvv/base/vmulhsu_vx_mu_rv32-1.C | 157 + .../riscv/rvv/base/vmulhsu_vx_mu_rv32-2.C | 157 + .../riscv/rvv/base/vmulhsu_vx_mu_rv32-3.C | 157 + .../riscv/rvv/base/vmulhsu_vx_mu_rv64-1.C | 160 + .../riscv/rvv/base/vmulhsu_vx_mu_rv64-2.C | 160 + .../riscv/rvv/base/vmulhsu_vx_mu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vmulhsu_vx_rv32-1.C | 308 + .../g++.target/riscv/rvv/base/vmulhsu_vx_rv32-2.C | 308 + .../g++.target/riscv/rvv/base/vmulhsu_vx_rv32-3.C | 308 + .../g++.target/riscv/rvv/base/vmulhsu_vx_rv64-1.C | 314 + .../g++.target/riscv/rvv/base/vmulhsu_vx_rv64-2.C | 314 + .../g++.target/riscv/rvv/base/vmulhsu_vx_rv64-3.C | 314 + .../riscv/rvv/base/vmulhsu_vx_tu_rv32-1.C | 157 + .../riscv/rvv/base/vmulhsu_vx_tu_rv32-2.C | 157 + .../riscv/rvv/base/vmulhsu_vx_tu_rv32-3.C | 157 + .../riscv/rvv/base/vmulhsu_vx_tu_rv64-1.C | 160 + .../riscv/rvv/base/vmulhsu_vx_tu_rv64-2.C | 160 + .../riscv/rvv/base/vmulhsu_vx_tu_rv64-3.C | 160 + .../riscv/rvv/base/vmulhsu_vx_tum_rv32-1.C | 157 + .../riscv/rvv/base/vmulhsu_vx_tum_rv32-2.C | 157 + .../riscv/rvv/base/vmulhsu_vx_tum_rv32-3.C | 157 + .../riscv/rvv/base/vmulhsu_vx_tum_rv64-1.C | 160 + .../riscv/rvv/base/vmulhsu_vx_tum_rv64-2.C | 160 + .../riscv/rvv/base/vmulhsu_vx_tum_rv64-3.C | 160 + .../riscv/rvv/base/vmulhsu_vx_tumu_rv32-1.C | 157 + .../riscv/rvv/base/vmulhsu_vx_tumu_rv32-2.C | 157 + .../riscv/rvv/base/vmulhsu_vx_tumu_rv32-3.C | 157 + .../riscv/rvv/base/vmulhsu_vx_tumu_rv64-1.C | 160 + .../riscv/rvv/base/vmulhsu_vx_tumu_rv64-2.C | 160 + .../riscv/rvv/base/vmulhsu_vx_tumu_rv64-3.C | 160 + .../riscv/rvv/base/vmulhu_vx_mu_rv32-1.C | 157 + .../riscv/rvv/base/vmulhu_vx_mu_rv32-2.C | 157 + .../riscv/rvv/base/vmulhu_vx_mu_rv32-3.C | 157 + .../riscv/rvv/base/vmulhu_vx_mu_rv64-1.C | 160 + .../riscv/rvv/base/vmulhu_vx_mu_rv64-2.C | 160 + .../riscv/rvv/base/vmulhu_vx_mu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vmulhu_vx_rv32-1.C | 308 + .../g++.target/riscv/rvv/base/vmulhu_vx_rv32-2.C | 308 + .../g++.target/riscv/rvv/base/vmulhu_vx_rv32-3.C | 308 + .../g++.target/riscv/rvv/base/vmulhu_vx_rv64-1.C | 314 + .../g++.target/riscv/rvv/base/vmulhu_vx_rv64-2.C | 314 + .../g++.target/riscv/rvv/base/vmulhu_vx_rv64-3.C | 314 + .../riscv/rvv/base/vmulhu_vx_tu_rv32-1.C | 157 + .../riscv/rvv/base/vmulhu_vx_tu_rv32-2.C | 157 + .../riscv/rvv/base/vmulhu_vx_tu_rv32-3.C | 157 + .../riscv/rvv/base/vmulhu_vx_tu_rv64-1.C | 160 + .../riscv/rvv/base/vmulhu_vx_tu_rv64-2.C | 160 + .../riscv/rvv/base/vmulhu_vx_tu_rv64-3.C | 160 + .../riscv/rvv/base/vmulhu_vx_tum_rv32-1.C | 157 + .../riscv/rvv/base/vmulhu_vx_tum_rv32-2.C | 157 + .../riscv/rvv/base/vmulhu_vx_tum_rv32-3.C | 157 + .../riscv/rvv/base/vmulhu_vx_tum_rv64-1.C | 160 + .../riscv/rvv/base/vmulhu_vx_tum_rv64-2.C | 160 + .../riscv/rvv/base/vmulhu_vx_tum_rv64-3.C | 160 + .../riscv/rvv/base/vmulhu_vx_tumu_rv32-1.C | 157 + .../riscv/rvv/base/vmulhu_vx_tumu_rv32-2.C | 157 + .../riscv/rvv/base/vmulhu_vx_tumu_rv32-3.C | 157 + .../riscv/rvv/base/vmulhu_vx_tumu_rv64-1.C | 160 + .../riscv/rvv/base/vmulhu_vx_tumu_rv64-2.C | 160 + .../riscv/rvv/base/vmulhu_vx_tumu_rv64-3.C | 160 + gcc/testsuite/g++.target/riscv/rvv/base/vmv_v-1.C | 392 + .../g++.target/riscv/rvv/base/vmv_v_tu-1.C | 392 + .../g++.target/riscv/rvv/base/vmv_v_x_rv32-1.C | 289 + .../g++.target/riscv/rvv/base/vmv_v_x_rv32-2.C | 289 + .../g++.target/riscv/rvv/base/vmv_v_x_rv32-3.C | 289 + .../g++.target/riscv/rvv/base/vmv_v_x_rv64-1.C | 292 + .../g++.target/riscv/rvv/base/vmv_v_x_rv64-2.C | 292 + .../g++.target/riscv/rvv/base/vmv_v_x_rv64-3.C | 292 + .../g++.target/riscv/rvv/base/vnclip_vv-1.C | 216 + .../g++.target/riscv/rvv/base/vnclip_vv-2.C | 216 + .../g++.target/riscv/rvv/base/vnclip_vv-3.C | 216 + .../g++.target/riscv/rvv/base/vnclip_vv_mu-1.C | 111 + .../g++.target/riscv/rvv/base/vnclip_vv_mu-2.C | 111 + .../g++.target/riscv/rvv/base/vnclip_vv_mu-3.C | 111 + .../g++.target/riscv/rvv/base/vnclip_vv_tu-1.C | 111 + .../g++.target/riscv/rvv/base/vnclip_vv_tu-2.C | 111 + .../g++.target/riscv/rvv/base/vnclip_vv_tu-3.C | 111 + .../g++.target/riscv/rvv/base/vnclip_vv_tum-1.C | 111 + .../g++.target/riscv/rvv/base/vnclip_vv_tum-2.C | 111 + .../g++.target/riscv/rvv/base/vnclip_vv_tum-3.C | 111 + .../g++.target/riscv/rvv/base/vnclip_vv_tumu-1.C | 111 + .../g++.target/riscv/rvv/base/vnclip_vv_tumu-2.C | 111 + .../g++.target/riscv/rvv/base/vnclip_vv_tumu-3.C | 111 + .../g++.target/riscv/rvv/base/vnclip_vx-1.C | 216 + .../g++.target/riscv/rvv/base/vnclip_vx-2.C | 216 + .../g++.target/riscv/rvv/base/vnclip_vx-3.C | 216 + .../g++.target/riscv/rvv/base/vnclip_vx_mu-1.C | 111 + .../g++.target/riscv/rvv/base/vnclip_vx_mu-2.C | 111 + .../g++.target/riscv/rvv/base/vnclip_vx_mu-3.C | 111 + .../g++.target/riscv/rvv/base/vnclip_vx_tu-1.C | 111 + .../g++.target/riscv/rvv/base/vnclip_vx_tu-2.C | 111 + .../g++.target/riscv/rvv/base/vnclip_vx_tu-3.C | 111 + .../g++.target/riscv/rvv/base/vnclip_vx_tum-1.C | 111 + .../g++.target/riscv/rvv/base/vnclip_vx_tum-2.C | 111 + .../g++.target/riscv/rvv/base/vnclip_vx_tum-3.C | 111 + .../g++.target/riscv/rvv/base/vnclip_vx_tumu-1.C | 111 + .../g++.target/riscv/rvv/base/vnclip_vx_tumu-2.C | 111 + .../g++.target/riscv/rvv/base/vnclip_vx_tumu-3.C | 111 + .../g++.target/riscv/rvv/base/vnclipu_vv-1.C | 216 + .../g++.target/riscv/rvv/base/vnclipu_vv-2.C | 216 + .../g++.target/riscv/rvv/base/vnclipu_vv-3.C | 216 + .../g++.target/riscv/rvv/base/vnclipu_vv_mu-1.C | 111 + .../g++.target/riscv/rvv/base/vnclipu_vv_mu-2.C | 111 + .../g++.target/riscv/rvv/base/vnclipu_vv_mu-3.C | 111 + .../g++.target/riscv/rvv/base/vnclipu_vv_tu-1.C | 111 + .../g++.target/riscv/rvv/base/vnclipu_vv_tu-2.C | 111 + .../g++.target/riscv/rvv/base/vnclipu_vv_tu-3.C | 111 + .../g++.target/riscv/rvv/base/vnclipu_vv_tum-1.C | 111 + .../g++.target/riscv/rvv/base/vnclipu_vv_tum-2.C | 111 + .../g++.target/riscv/rvv/base/vnclipu_vv_tum-3.C | 111 + .../g++.target/riscv/rvv/base/vnclipu_vv_tumu-1.C | 111 + .../g++.target/riscv/rvv/base/vnclipu_vv_tumu-2.C | 111 + .../g++.target/riscv/rvv/base/vnclipu_vv_tumu-3.C | 111 + .../g++.target/riscv/rvv/base/vnclipu_vx-1.C | 216 + .../g++.target/riscv/rvv/base/vnclipu_vx-2.C | 216 + .../g++.target/riscv/rvv/base/vnclipu_vx-3.C | 216 + .../g++.target/riscv/rvv/base/vnclipu_vx_mu-1.C | 111 + .../g++.target/riscv/rvv/base/vnclipu_vx_mu-2.C | 111 + .../g++.target/riscv/rvv/base/vnclipu_vx_mu-3.C | 111 + .../g++.target/riscv/rvv/base/vnclipu_vx_tu-1.C | 111 + .../g++.target/riscv/rvv/base/vnclipu_vx_tu-2.C | 111 + .../g++.target/riscv/rvv/base/vnclipu_vx_tu-3.C | 111 + .../g++.target/riscv/rvv/base/vnclipu_vx_tum-1.C | 111 + .../g++.target/riscv/rvv/base/vnclipu_vx_tum-2.C | 111 + .../g++.target/riscv/rvv/base/vnclipu_vx_tum-3.C | 111 + .../g++.target/riscv/rvv/base/vnclipu_vx_tumu-1.C | 111 + .../g++.target/riscv/rvv/base/vnclipu_vx_tumu-2.C | 111 + .../g++.target/riscv/rvv/base/vnclipu_vx_tumu-3.C | 111 + .../g++.target/riscv/rvv/base/vncvt_x-1.C | 396 + .../g++.target/riscv/rvv/base/vncvt_x-2.C | 396 + .../g++.target/riscv/rvv/base/vncvt_x-3.C | 396 + .../g++.target/riscv/rvv/base/vncvt_x_mu-1.C | 201 + .../g++.target/riscv/rvv/base/vncvt_x_mu-2.C | 201 + .../g++.target/riscv/rvv/base/vncvt_x_mu-3.C | 201 + .../g++.target/riscv/rvv/base/vncvt_x_tu-1.C | 201 + .../g++.target/riscv/rvv/base/vncvt_x_tu-2.C | 201 + .../g++.target/riscv/rvv/base/vncvt_x_tu-3.C | 201 + .../g++.target/riscv/rvv/base/vncvt_x_tum-1.C | 201 + .../g++.target/riscv/rvv/base/vncvt_x_tum-2.C | 201 + .../g++.target/riscv/rvv/base/vncvt_x_tum-3.C | 201 + .../g++.target/riscv/rvv/base/vncvt_x_tumu-1.C | 201 + .../g++.target/riscv/rvv/base/vncvt_x_tumu-2.C | 201 + .../g++.target/riscv/rvv/base/vncvt_x_tumu-3.C | 201 + gcc/testsuite/g++.target/riscv/rvv/base/vneg_v-1.C | 314 + gcc/testsuite/g++.target/riscv/rvv/base/vneg_v-2.C | 314 + gcc/testsuite/g++.target/riscv/rvv/base/vneg_v-3.C | 314 + .../g++.target/riscv/rvv/base/vneg_v_mu-1.C | 160 + .../g++.target/riscv/rvv/base/vneg_v_mu-2.C | 160 + .../g++.target/riscv/rvv/base/vneg_v_mu-3.C | 160 + .../g++.target/riscv/rvv/base/vneg_v_tu-1.C | 160 + .../g++.target/riscv/rvv/base/vneg_v_tu-2.C | 160 + .../g++.target/riscv/rvv/base/vneg_v_tu-3.C | 160 + .../g++.target/riscv/rvv/base/vneg_v_tum-1.C | 160 + .../g++.target/riscv/rvv/base/vneg_v_tum-2.C | 160 + .../g++.target/riscv/rvv/base/vneg_v_tum-3.C | 160 + .../g++.target/riscv/rvv/base/vneg_v_tumu-1.C | 160 + .../g++.target/riscv/rvv/base/vneg_v_tumu-2.C | 160 + .../g++.target/riscv/rvv/base/vneg_v_tumu-3.C | 160 + .../g++.target/riscv/rvv/base/vnmsac_vv-1.C | 578 + .../g++.target/riscv/rvv/base/vnmsac_vv-2.C | 578 + .../g++.target/riscv/rvv/base/vnmsac_vv-3.C | 578 + .../g++.target/riscv/rvv/base/vnmsac_vv_mu-1.C | 292 + .../g++.target/riscv/rvv/base/vnmsac_vv_mu-2.C | 292 + .../g++.target/riscv/rvv/base/vnmsac_vv_mu-3.C | 292 + .../g++.target/riscv/rvv/base/vnmsac_vv_tu-1.C | 292 + .../g++.target/riscv/rvv/base/vnmsac_vv_tu-2.C | 292 + .../g++.target/riscv/rvv/base/vnmsac_vv_tu-3.C | 292 + .../g++.target/riscv/rvv/base/vnmsac_vv_tum-1.C | 292 + .../g++.target/riscv/rvv/base/vnmsac_vv_tum-2.C | 292 + .../g++.target/riscv/rvv/base/vnmsac_vv_tum-3.C | 292 + .../g++.target/riscv/rvv/base/vnmsac_vv_tumu-1.C | 292 + .../g++.target/riscv/rvv/base/vnmsac_vv_tumu-2.C | 292 + .../g++.target/riscv/rvv/base/vnmsac_vv_tumu-3.C | 292 + .../riscv/rvv/base/vnmsac_vx_mu_rv32-1.C | 289 + .../riscv/rvv/base/vnmsac_vx_mu_rv32-2.C | 289 + .../riscv/rvv/base/vnmsac_vx_mu_rv32-3.C | 289 + .../riscv/rvv/base/vnmsac_vx_mu_rv64-1.C | 292 + .../riscv/rvv/base/vnmsac_vx_mu_rv64-2.C | 292 + .../riscv/rvv/base/vnmsac_vx_mu_rv64-3.C | 292 + .../g++.target/riscv/rvv/base/vnmsac_vx_rv32-1.C | 572 + .../g++.target/riscv/rvv/base/vnmsac_vx_rv32-2.C | 572 + .../g++.target/riscv/rvv/base/vnmsac_vx_rv32-3.C | 572 + .../g++.target/riscv/rvv/base/vnmsac_vx_rv64-1.C | 578 + .../g++.target/riscv/rvv/base/vnmsac_vx_rv64-2.C | 578 + .../g++.target/riscv/rvv/base/vnmsac_vx_rv64-3.C | 578 + .../riscv/rvv/base/vnmsac_vx_tu_rv32-1.C | 289 + .../riscv/rvv/base/vnmsac_vx_tu_rv32-2.C | 289 + .../riscv/rvv/base/vnmsac_vx_tu_rv32-3.C | 289 + .../riscv/rvv/base/vnmsac_vx_tu_rv64-1.C | 292 + .../riscv/rvv/base/vnmsac_vx_tu_rv64-2.C | 292 + .../riscv/rvv/base/vnmsac_vx_tu_rv64-3.C | 292 + .../riscv/rvv/base/vnmsac_vx_tum_rv32-1.C | 289 + .../riscv/rvv/base/vnmsac_vx_tum_rv32-2.C | 289 + .../riscv/rvv/base/vnmsac_vx_tum_rv32-3.C | 289 + .../riscv/rvv/base/vnmsac_vx_tum_rv64-1.C | 292 + .../riscv/rvv/base/vnmsac_vx_tum_rv64-2.C | 292 + .../riscv/rvv/base/vnmsac_vx_tum_rv64-3.C | 292 + .../riscv/rvv/base/vnmsac_vx_tumu_rv32-1.C | 289 + .../riscv/rvv/base/vnmsac_vx_tumu_rv32-2.C | 289 + .../riscv/rvv/base/vnmsac_vx_tumu_rv32-3.C | 289 + .../riscv/rvv/base/vnmsac_vx_tumu_rv64-1.C | 292 + .../riscv/rvv/base/vnmsac_vx_tumu_rv64-2.C | 292 + .../riscv/rvv/base/vnmsac_vx_tumu_rv64-3.C | 292 + .../g++.target/riscv/rvv/base/vnmsub_vv-1.C | 578 + .../g++.target/riscv/rvv/base/vnmsub_vv-2.C | 578 + .../g++.target/riscv/rvv/base/vnmsub_vv-3.C | 578 + .../g++.target/riscv/rvv/base/vnmsub_vv_mu-1.C | 292 + .../g++.target/riscv/rvv/base/vnmsub_vv_mu-2.C | 292 + .../g++.target/riscv/rvv/base/vnmsub_vv_mu-3.C | 292 + .../g++.target/riscv/rvv/base/vnmsub_vv_tu-1.C | 292 + .../g++.target/riscv/rvv/base/vnmsub_vv_tu-2.C | 292 + .../g++.target/riscv/rvv/base/vnmsub_vv_tu-3.C | 292 + .../g++.target/riscv/rvv/base/vnmsub_vv_tum-1.C | 292 + .../g++.target/riscv/rvv/base/vnmsub_vv_tum-2.C | 292 + .../g++.target/riscv/rvv/base/vnmsub_vv_tum-3.C | 292 + .../g++.target/riscv/rvv/base/vnmsub_vv_tumu-1.C | 292 + .../g++.target/riscv/rvv/base/vnmsub_vv_tumu-2.C | 292 + .../g++.target/riscv/rvv/base/vnmsub_vv_tumu-3.C | 292 + .../riscv/rvv/base/vnmsub_vx_mu_rv32-1.C | 289 + .../riscv/rvv/base/vnmsub_vx_mu_rv32-2.C | 289 + .../riscv/rvv/base/vnmsub_vx_mu_rv32-3.C | 289 + .../riscv/rvv/base/vnmsub_vx_mu_rv64-1.C | 292 + .../riscv/rvv/base/vnmsub_vx_mu_rv64-2.C | 292 + .../riscv/rvv/base/vnmsub_vx_mu_rv64-3.C | 292 + .../g++.target/riscv/rvv/base/vnmsub_vx_rv32-1.C | 572 + .../g++.target/riscv/rvv/base/vnmsub_vx_rv32-2.C | 572 + .../g++.target/riscv/rvv/base/vnmsub_vx_rv32-3.C | 572 + .../g++.target/riscv/rvv/base/vnmsub_vx_rv64-1.C | 578 + .../g++.target/riscv/rvv/base/vnmsub_vx_rv64-2.C | 578 + .../g++.target/riscv/rvv/base/vnmsub_vx_rv64-3.C | 578 + .../riscv/rvv/base/vnmsub_vx_tu_rv32-1.C | 289 + .../riscv/rvv/base/vnmsub_vx_tu_rv32-2.C | 289 + .../riscv/rvv/base/vnmsub_vx_tu_rv32-3.C | 289 + .../riscv/rvv/base/vnmsub_vx_tu_rv64-1.C | 292 + .../riscv/rvv/base/vnmsub_vx_tu_rv64-2.C | 292 + .../riscv/rvv/base/vnmsub_vx_tu_rv64-3.C | 292 + .../riscv/rvv/base/vnmsub_vx_tum_rv32-1.C | 289 + .../riscv/rvv/base/vnmsub_vx_tum_rv32-2.C | 289 + .../riscv/rvv/base/vnmsub_vx_tum_rv32-3.C | 289 + .../riscv/rvv/base/vnmsub_vx_tum_rv64-1.C | 292 + .../riscv/rvv/base/vnmsub_vx_tum_rv64-2.C | 292 + .../riscv/rvv/base/vnmsub_vx_tum_rv64-3.C | 292 + .../riscv/rvv/base/vnmsub_vx_tumu_rv32-1.C | 289 + .../riscv/rvv/base/vnmsub_vx_tumu_rv32-2.C | 289 + .../riscv/rvv/base/vnmsub_vx_tumu_rv32-3.C | 289 + .../riscv/rvv/base/vnmsub_vx_tumu_rv64-1.C | 292 + .../riscv/rvv/base/vnmsub_vx_tumu_rv64-2.C | 292 + .../riscv/rvv/base/vnmsub_vx_tumu_rv64-3.C | 292 + gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-1.C | 314 + gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-2.C | 314 + gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-3.C | 314 + .../g++.target/riscv/rvv/base/vnot_v_mu-1.C | 160 + .../g++.target/riscv/rvv/base/vnot_v_mu-2.C | 160 + .../g++.target/riscv/rvv/base/vnot_v_mu-3.C | 160 + .../g++.target/riscv/rvv/base/vnot_v_tu-1.C | 160 + .../g++.target/riscv/rvv/base/vnot_v_tu-2.C | 160 + .../g++.target/riscv/rvv/base/vnot_v_tu-3.C | 160 + .../g++.target/riscv/rvv/base/vnot_v_tum-1.C | 160 + .../g++.target/riscv/rvv/base/vnot_v_tum-2.C | 160 + .../g++.target/riscv/rvv/base/vnot_v_tum-3.C | 160 + .../g++.target/riscv/rvv/base/vnot_v_tumu-1.C | 160 + .../g++.target/riscv/rvv/base/vnot_v_tumu-2.C | 160 + .../g++.target/riscv/rvv/base/vnot_v_tumu-3.C | 160 + .../g++.target/riscv/rvv/base/vnsra_vv-1.C | 216 + .../g++.target/riscv/rvv/base/vnsra_vv-2.C | 216 + .../g++.target/riscv/rvv/base/vnsra_vv-3.C | 216 + .../g++.target/riscv/rvv/base/vnsra_vv_mu-1.C | 111 + .../g++.target/riscv/rvv/base/vnsra_vv_mu-2.C | 111 + .../g++.target/riscv/rvv/base/vnsra_vv_mu-3.C | 111 + .../g++.target/riscv/rvv/base/vnsra_vv_tu-1.C | 111 + .../g++.target/riscv/rvv/base/vnsra_vv_tu-2.C | 111 + .../g++.target/riscv/rvv/base/vnsra_vv_tu-3.C | 111 + .../g++.target/riscv/rvv/base/vnsra_vv_tum-1.C | 111 + .../g++.target/riscv/rvv/base/vnsra_vv_tum-2.C | 111 + .../g++.target/riscv/rvv/base/vnsra_vv_tum-3.C | 111 + .../g++.target/riscv/rvv/base/vnsra_vv_tumu-1.C | 111 + .../g++.target/riscv/rvv/base/vnsra_vv_tumu-2.C | 111 + .../g++.target/riscv/rvv/base/vnsra_vv_tumu-3.C | 111 + .../g++.target/riscv/rvv/base/vnsra_vx-1.C | 216 + .../g++.target/riscv/rvv/base/vnsra_vx-2.C | 216 + .../g++.target/riscv/rvv/base/vnsra_vx-3.C | 216 + .../g++.target/riscv/rvv/base/vnsra_vx_mu-1.C | 111 + .../g++.target/riscv/rvv/base/vnsra_vx_mu-2.C | 111 + .../g++.target/riscv/rvv/base/vnsra_vx_mu-3.C | 111 + .../g++.target/riscv/rvv/base/vnsra_vx_tu-1.C | 111 + .../g++.target/riscv/rvv/base/vnsra_vx_tu-2.C | 111 + .../g++.target/riscv/rvv/base/vnsra_vx_tu-3.C | 111 + .../g++.target/riscv/rvv/base/vnsra_vx_tum-1.C | 111 + .../g++.target/riscv/rvv/base/vnsra_vx_tum-2.C | 111 + .../g++.target/riscv/rvv/base/vnsra_vx_tum-3.C | 111 + .../g++.target/riscv/rvv/base/vnsra_vx_tumu-1.C | 111 + .../g++.target/riscv/rvv/base/vnsra_vx_tumu-2.C | 111 + .../g++.target/riscv/rvv/base/vnsra_vx_tumu-3.C | 111 + .../g++.target/riscv/rvv/base/vnsrl_vv-1.C | 216 + .../g++.target/riscv/rvv/base/vnsrl_vv-2.C | 216 + .../g++.target/riscv/rvv/base/vnsrl_vv-3.C | 216 + .../g++.target/riscv/rvv/base/vnsrl_vv_mu-1.C | 111 + .../g++.target/riscv/rvv/base/vnsrl_vv_mu-2.C | 111 + .../g++.target/riscv/rvv/base/vnsrl_vv_mu-3.C | 111 + .../g++.target/riscv/rvv/base/vnsrl_vv_tu-1.C | 111 + .../g++.target/riscv/rvv/base/vnsrl_vv_tu-2.C | 111 + .../g++.target/riscv/rvv/base/vnsrl_vv_tu-3.C | 111 + .../g++.target/riscv/rvv/base/vnsrl_vv_tum-1.C | 111 + .../g++.target/riscv/rvv/base/vnsrl_vv_tum-2.C | 111 + .../g++.target/riscv/rvv/base/vnsrl_vv_tum-3.C | 111 + .../g++.target/riscv/rvv/base/vnsrl_vv_tumu-1.C | 111 + .../g++.target/riscv/rvv/base/vnsrl_vv_tumu-2.C | 111 + .../g++.target/riscv/rvv/base/vnsrl_vv_tumu-3.C | 111 + .../g++.target/riscv/rvv/base/vnsrl_vx-1.C | 216 + .../g++.target/riscv/rvv/base/vnsrl_vx-2.C | 216 + .../g++.target/riscv/rvv/base/vnsrl_vx-3.C | 216 + .../g++.target/riscv/rvv/base/vnsrl_vx_mu-1.C | 111 + .../g++.target/riscv/rvv/base/vnsrl_vx_mu-2.C | 111 + .../g++.target/riscv/rvv/base/vnsrl_vx_mu-3.C | 111 + .../g++.target/riscv/rvv/base/vnsrl_vx_tu-1.C | 111 + .../g++.target/riscv/rvv/base/vnsrl_vx_tu-2.C | 111 + .../g++.target/riscv/rvv/base/vnsrl_vx_tu-3.C | 111 + .../g++.target/riscv/rvv/base/vnsrl_vx_tum-1.C | 111 + .../g++.target/riscv/rvv/base/vnsrl_vx_tum-2.C | 111 + .../g++.target/riscv/rvv/base/vnsrl_vx_tum-3.C | 111 + .../g++.target/riscv/rvv/base/vnsrl_vx_tumu-1.C | 111 + .../g++.target/riscv/rvv/base/vnsrl_vx_tumu-2.C | 111 + .../g++.target/riscv/rvv/base/vnsrl_vx_tumu-3.C | 111 + gcc/testsuite/g++.target/riscv/rvv/base/vor_vv-1.C | 578 + gcc/testsuite/g++.target/riscv/rvv/base/vor_vv-2.C | 578 + gcc/testsuite/g++.target/riscv/rvv/base/vor_vv-3.C | 578 + .../g++.target/riscv/rvv/base/vor_vv_mu-1.C | 292 + .../g++.target/riscv/rvv/base/vor_vv_mu-2.C | 292 + .../g++.target/riscv/rvv/base/vor_vv_mu-3.C | 292 + .../g++.target/riscv/rvv/base/vor_vv_tu-1.C | 292 + .../g++.target/riscv/rvv/base/vor_vv_tu-2.C | 292 + .../g++.target/riscv/rvv/base/vor_vv_tu-3.C | 292 + .../g++.target/riscv/rvv/base/vor_vv_tum-1.C | 292 + .../g++.target/riscv/rvv/base/vor_vv_tum-2.C | 292 + .../g++.target/riscv/rvv/base/vor_vv_tum-3.C | 292 + .../g++.target/riscv/rvv/base/vor_vv_tumu-1.C | 292 + .../g++.target/riscv/rvv/base/vor_vv_tumu-2.C | 292 + .../g++.target/riscv/rvv/base/vor_vv_tumu-3.C | 292 + .../g++.target/riscv/rvv/base/vor_vx_mu_rv32-1.C | 289 + .../g++.target/riscv/rvv/base/vor_vx_mu_rv32-2.C | 289 + .../g++.target/riscv/rvv/base/vor_vx_mu_rv32-3.C | 289 + .../g++.target/riscv/rvv/base/vor_vx_mu_rv64-1.C | 292 + .../g++.target/riscv/rvv/base/vor_vx_mu_rv64-2.C | 292 + .../g++.target/riscv/rvv/base/vor_vx_mu_rv64-3.C | 292 + .../g++.target/riscv/rvv/base/vor_vx_rv32-1.C | 572 + .../g++.target/riscv/rvv/base/vor_vx_rv32-2.C | 572 + .../g++.target/riscv/rvv/base/vor_vx_rv32-3.C | 572 + .../g++.target/riscv/rvv/base/vor_vx_rv64-1.C | 578 + .../g++.target/riscv/rvv/base/vor_vx_rv64-2.C | 578 + .../g++.target/riscv/rvv/base/vor_vx_rv64-3.C | 578 + .../g++.target/riscv/rvv/base/vor_vx_tu_rv32-1.C | 289 + .../g++.target/riscv/rvv/base/vor_vx_tu_rv32-2.C | 289 + .../g++.target/riscv/rvv/base/vor_vx_tu_rv32-3.C | 289 + .../g++.target/riscv/rvv/base/vor_vx_tu_rv64-1.C | 292 + .../g++.target/riscv/rvv/base/vor_vx_tu_rv64-2.C | 292 + .../g++.target/riscv/rvv/base/vor_vx_tu_rv64-3.C | 292 + .../g++.target/riscv/rvv/base/vor_vx_tum_rv32-1.C | 289 + .../g++.target/riscv/rvv/base/vor_vx_tum_rv32-2.C | 289 + .../g++.target/riscv/rvv/base/vor_vx_tum_rv32-3.C | 289 + .../g++.target/riscv/rvv/base/vor_vx_tum_rv64-1.C | 292 + .../g++.target/riscv/rvv/base/vor_vx_tum_rv64-2.C | 292 + .../g++.target/riscv/rvv/base/vor_vx_tum_rv64-3.C | 292 + .../g++.target/riscv/rvv/base/vor_vx_tumu_rv32-1.C | 289 + .../g++.target/riscv/rvv/base/vor_vx_tumu_rv32-2.C | 289 + .../g++.target/riscv/rvv/base/vor_vx_tumu_rv32-3.C | 289 + .../g++.target/riscv/rvv/base/vor_vx_tumu_rv64-1.C | 292 + .../g++.target/riscv/rvv/base/vor_vx_tumu_rv64-2.C | 292 + .../g++.target/riscv/rvv/base/vor_vx_tumu_rv64-3.C | 292 + .../g++.target/riscv/rvv/base/vrem_vv-1.C | 314 + .../g++.target/riscv/rvv/base/vrem_vv-2.C | 314 + .../g++.target/riscv/rvv/base/vrem_vv-3.C | 314 + .../g++.target/riscv/rvv/base/vrem_vv_mu-1.C | 160 + .../g++.target/riscv/rvv/base/vrem_vv_mu-2.C | 160 + .../g++.target/riscv/rvv/base/vrem_vv_mu-3.C | 160 + .../g++.target/riscv/rvv/base/vrem_vv_tu-1.C | 160 + .../g++.target/riscv/rvv/base/vrem_vv_tu-2.C | 160 + .../g++.target/riscv/rvv/base/vrem_vv_tu-3.C | 160 + .../g++.target/riscv/rvv/base/vrem_vv_tum-1.C | 160 + .../g++.target/riscv/rvv/base/vrem_vv_tum-2.C | 160 + .../g++.target/riscv/rvv/base/vrem_vv_tum-3.C | 160 + .../g++.target/riscv/rvv/base/vrem_vv_tumu-1.C | 160 + .../g++.target/riscv/rvv/base/vrem_vv_tumu-2.C | 160 + .../g++.target/riscv/rvv/base/vrem_vv_tumu-3.C | 160 + .../g++.target/riscv/rvv/base/vrem_vx_mu_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vrem_vx_mu_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vrem_vx_mu_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vrem_vx_mu_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vrem_vx_mu_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vrem_vx_mu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vrem_vx_rv32-1.C | 308 + .../g++.target/riscv/rvv/base/vrem_vx_rv32-2.C | 308 + .../g++.target/riscv/rvv/base/vrem_vx_rv32-3.C | 308 + .../g++.target/riscv/rvv/base/vrem_vx_rv64-1.C | 314 + .../g++.target/riscv/rvv/base/vrem_vx_rv64-2.C | 314 + .../g++.target/riscv/rvv/base/vrem_vx_rv64-3.C | 314 + .../g++.target/riscv/rvv/base/vrem_vx_tu_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vrem_vx_tu_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vrem_vx_tu_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vrem_vx_tu_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vrem_vx_tu_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vrem_vx_tu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vrem_vx_tum_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vrem_vx_tum_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vrem_vx_tum_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vrem_vx_tum_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vrem_vx_tum_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vrem_vx_tum_rv64-3.C | 160 + .../riscv/rvv/base/vrem_vx_tumu_rv32-1.C | 157 + .../riscv/rvv/base/vrem_vx_tumu_rv32-2.C | 157 + .../riscv/rvv/base/vrem_vx_tumu_rv32-3.C | 157 + .../riscv/rvv/base/vrem_vx_tumu_rv64-1.C | 160 + .../riscv/rvv/base/vrem_vx_tumu_rv64-2.C | 160 + .../riscv/rvv/base/vrem_vx_tumu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vremu_vv-1.C | 314 + .../g++.target/riscv/rvv/base/vremu_vv-2.C | 314 + .../g++.target/riscv/rvv/base/vremu_vv-3.C | 314 + .../g++.target/riscv/rvv/base/vremu_vv_mu-1.C | 160 + .../g++.target/riscv/rvv/base/vremu_vv_mu-2.C | 160 + .../g++.target/riscv/rvv/base/vremu_vv_mu-3.C | 160 + .../g++.target/riscv/rvv/base/vremu_vv_tu-1.C | 160 + .../g++.target/riscv/rvv/base/vremu_vv_tu-2.C | 160 + .../g++.target/riscv/rvv/base/vremu_vv_tu-3.C | 160 + .../g++.target/riscv/rvv/base/vremu_vv_tum-1.C | 160 + .../g++.target/riscv/rvv/base/vremu_vv_tum-2.C | 160 + .../g++.target/riscv/rvv/base/vremu_vv_tum-3.C | 160 + .../g++.target/riscv/rvv/base/vremu_vv_tumu-1.C | 160 + .../g++.target/riscv/rvv/base/vremu_vv_tumu-2.C | 160 + .../g++.target/riscv/rvv/base/vremu_vv_tumu-3.C | 160 + .../g++.target/riscv/rvv/base/vremu_vx_mu_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vremu_vx_mu_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vremu_vx_mu_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vremu_vx_mu_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vremu_vx_mu_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vremu_vx_mu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vremu_vx_rv32-1.C | 308 + .../g++.target/riscv/rvv/base/vremu_vx_rv32-2.C | 308 + .../g++.target/riscv/rvv/base/vremu_vx_rv32-3.C | 308 + .../g++.target/riscv/rvv/base/vremu_vx_rv64-1.C | 314 + .../g++.target/riscv/rvv/base/vremu_vx_rv64-2.C | 314 + .../g++.target/riscv/rvv/base/vremu_vx_rv64-3.C | 314 + .../g++.target/riscv/rvv/base/vremu_vx_tu_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vremu_vx_tu_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vremu_vx_tu_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vremu_vx_tu_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vremu_vx_tu_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vremu_vx_tu_rv64-3.C | 160 + .../riscv/rvv/base/vremu_vx_tum_rv32-1.C | 157 + .../riscv/rvv/base/vremu_vx_tum_rv32-2.C | 157 + .../riscv/rvv/base/vremu_vx_tum_rv32-3.C | 157 + .../riscv/rvv/base/vremu_vx_tum_rv64-1.C | 160 + .../riscv/rvv/base/vremu_vx_tum_rv64-2.C | 160 + .../riscv/rvv/base/vremu_vx_tum_rv64-3.C | 160 + .../riscv/rvv/base/vremu_vx_tumu_rv32-1.C | 157 + .../riscv/rvv/base/vremu_vx_tumu_rv32-2.C | 157 + .../riscv/rvv/base/vremu_vx_tumu_rv32-3.C | 157 + .../riscv/rvv/base/vremu_vx_tumu_rv64-1.C | 160 + .../riscv/rvv/base/vremu_vx_tumu_rv64-2.C | 160 + .../riscv/rvv/base/vremu_vx_tumu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vrsub_vx_mu_rv32-1.C | 289 + .../g++.target/riscv/rvv/base/vrsub_vx_mu_rv32-2.C | 289 + .../g++.target/riscv/rvv/base/vrsub_vx_mu_rv32-3.C | 289 + .../g++.target/riscv/rvv/base/vrsub_vx_mu_rv64-1.C | 292 + .../g++.target/riscv/rvv/base/vrsub_vx_mu_rv64-2.C | 292 + .../g++.target/riscv/rvv/base/vrsub_vx_mu_rv64-3.C | 292 + .../g++.target/riscv/rvv/base/vrsub_vx_rv32-1.C | 572 + .../g++.target/riscv/rvv/base/vrsub_vx_rv32-2.C | 572 + .../g++.target/riscv/rvv/base/vrsub_vx_rv32-3.C | 572 + .../g++.target/riscv/rvv/base/vrsub_vx_rv64-1.C | 578 + .../g++.target/riscv/rvv/base/vrsub_vx_rv64-2.C | 578 + .../g++.target/riscv/rvv/base/vrsub_vx_rv64-3.C | 578 + .../g++.target/riscv/rvv/base/vrsub_vx_tu_rv32-1.C | 289 + .../g++.target/riscv/rvv/base/vrsub_vx_tu_rv32-2.C | 289 + .../g++.target/riscv/rvv/base/vrsub_vx_tu_rv32-3.C | 289 + .../g++.target/riscv/rvv/base/vrsub_vx_tu_rv64-1.C | 292 + .../g++.target/riscv/rvv/base/vrsub_vx_tu_rv64-2.C | 292 + .../g++.target/riscv/rvv/base/vrsub_vx_tu_rv64-3.C | 292 + .../riscv/rvv/base/vrsub_vx_tum_rv32-1.C | 289 + .../riscv/rvv/base/vrsub_vx_tum_rv32-2.C | 289 + .../riscv/rvv/base/vrsub_vx_tum_rv32-3.C | 289 + .../riscv/rvv/base/vrsub_vx_tum_rv64-1.C | 292 + .../riscv/rvv/base/vrsub_vx_tum_rv64-2.C | 292 + .../riscv/rvv/base/vrsub_vx_tum_rv64-3.C | 292 + .../riscv/rvv/base/vrsub_vx_tumu_rv32-1.C | 289 + .../riscv/rvv/base/vrsub_vx_tumu_rv32-2.C | 289 + .../riscv/rvv/base/vrsub_vx_tumu_rv32-3.C | 289 + .../riscv/rvv/base/vrsub_vx_tumu_rv64-1.C | 292 + .../riscv/rvv/base/vrsub_vx_tumu_rv64-2.C | 292 + .../riscv/rvv/base/vrsub_vx_tumu_rv64-3.C | 292 + .../g++.target/riscv/rvv/base/vsadd_vv-1.C | 314 + .../g++.target/riscv/rvv/base/vsadd_vv-2.C | 314 + .../g++.target/riscv/rvv/base/vsadd_vv-3.C | 314 + .../g++.target/riscv/rvv/base/vsadd_vv_mu-1.C | 160 + .../g++.target/riscv/rvv/base/vsadd_vv_mu-2.C | 160 + .../g++.target/riscv/rvv/base/vsadd_vv_mu-3.C | 160 + .../g++.target/riscv/rvv/base/vsadd_vv_tu-1.C | 160 + .../g++.target/riscv/rvv/base/vsadd_vv_tu-2.C | 160 + .../g++.target/riscv/rvv/base/vsadd_vv_tu-3.C | 160 + .../g++.target/riscv/rvv/base/vsadd_vv_tum-1.C | 160 + .../g++.target/riscv/rvv/base/vsadd_vv_tum-2.C | 160 + .../g++.target/riscv/rvv/base/vsadd_vv_tum-3.C | 160 + .../g++.target/riscv/rvv/base/vsadd_vv_tumu-1.C | 160 + .../g++.target/riscv/rvv/base/vsadd_vv_tumu-2.C | 160 + .../g++.target/riscv/rvv/base/vsadd_vv_tumu-3.C | 160 + .../g++.target/riscv/rvv/base/vsadd_vx_mu_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vsadd_vx_mu_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vsadd_vx_mu_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vsadd_vx_mu_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vsadd_vx_mu_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vsadd_vx_mu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vsadd_vx_rv32-1.C | 308 + .../g++.target/riscv/rvv/base/vsadd_vx_rv32-2.C | 308 + .../g++.target/riscv/rvv/base/vsadd_vx_rv32-3.C | 308 + .../g++.target/riscv/rvv/base/vsadd_vx_rv64-1.C | 314 + .../g++.target/riscv/rvv/base/vsadd_vx_rv64-2.C | 314 + .../g++.target/riscv/rvv/base/vsadd_vx_rv64-3.C | 314 + .../g++.target/riscv/rvv/base/vsadd_vx_tu_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vsadd_vx_tu_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vsadd_vx_tu_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vsadd_vx_tu_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vsadd_vx_tu_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vsadd_vx_tu_rv64-3.C | 160 + .../riscv/rvv/base/vsadd_vx_tum_rv32-1.C | 157 + .../riscv/rvv/base/vsadd_vx_tum_rv32-2.C | 157 + .../riscv/rvv/base/vsadd_vx_tum_rv32-3.C | 157 + .../riscv/rvv/base/vsadd_vx_tum_rv64-1.C | 160 + .../riscv/rvv/base/vsadd_vx_tum_rv64-2.C | 160 + .../riscv/rvv/base/vsadd_vx_tum_rv64-3.C | 160 + .../riscv/rvv/base/vsadd_vx_tumu_rv32-1.C | 157 + .../riscv/rvv/base/vsadd_vx_tumu_rv32-2.C | 157 + .../riscv/rvv/base/vsadd_vx_tumu_rv32-3.C | 157 + .../riscv/rvv/base/vsadd_vx_tumu_rv64-1.C | 160 + .../riscv/rvv/base/vsadd_vx_tumu_rv64-2.C | 160 + .../riscv/rvv/base/vsadd_vx_tumu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vsaddu_vv-1.C | 314 + .../g++.target/riscv/rvv/base/vsaddu_vv-2.C | 314 + .../g++.target/riscv/rvv/base/vsaddu_vv-3.C | 314 + .../g++.target/riscv/rvv/base/vsaddu_vv_mu-1.C | 160 + .../g++.target/riscv/rvv/base/vsaddu_vv_mu-2.C | 160 + .../g++.target/riscv/rvv/base/vsaddu_vv_mu-3.C | 160 + .../g++.target/riscv/rvv/base/vsaddu_vv_tu-1.C | 160 + .../g++.target/riscv/rvv/base/vsaddu_vv_tu-2.C | 160 + .../g++.target/riscv/rvv/base/vsaddu_vv_tu-3.C | 160 + .../g++.target/riscv/rvv/base/vsaddu_vv_tum-1.C | 160 + .../g++.target/riscv/rvv/base/vsaddu_vv_tum-2.C | 160 + .../g++.target/riscv/rvv/base/vsaddu_vv_tum-3.C | 160 + .../g++.target/riscv/rvv/base/vsaddu_vv_tumu-1.C | 160 + .../g++.target/riscv/rvv/base/vsaddu_vv_tumu-2.C | 160 + .../g++.target/riscv/rvv/base/vsaddu_vv_tumu-3.C | 160 + .../riscv/rvv/base/vsaddu_vx_mu_rv32-1.C | 157 + .../riscv/rvv/base/vsaddu_vx_mu_rv32-2.C | 157 + .../riscv/rvv/base/vsaddu_vx_mu_rv32-3.C | 157 + .../riscv/rvv/base/vsaddu_vx_mu_rv64-1.C | 160 + .../riscv/rvv/base/vsaddu_vx_mu_rv64-2.C | 160 + .../riscv/rvv/base/vsaddu_vx_mu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vsaddu_vx_rv32-1.C | 308 + .../g++.target/riscv/rvv/base/vsaddu_vx_rv32-2.C | 308 + .../g++.target/riscv/rvv/base/vsaddu_vx_rv32-3.C | 308 + .../g++.target/riscv/rvv/base/vsaddu_vx_rv64-1.C | 314 + .../g++.target/riscv/rvv/base/vsaddu_vx_rv64-2.C | 314 + .../g++.target/riscv/rvv/base/vsaddu_vx_rv64-3.C | 314 + .../riscv/rvv/base/vsaddu_vx_tu_rv32-1.C | 157 + .../riscv/rvv/base/vsaddu_vx_tu_rv32-2.C | 157 + .../riscv/rvv/base/vsaddu_vx_tu_rv32-3.C | 157 + .../riscv/rvv/base/vsaddu_vx_tu_rv64-1.C | 160 + .../riscv/rvv/base/vsaddu_vx_tu_rv64-2.C | 160 + .../riscv/rvv/base/vsaddu_vx_tu_rv64-3.C | 160 + .../riscv/rvv/base/vsaddu_vx_tum_rv32-1.C | 157 + .../riscv/rvv/base/vsaddu_vx_tum_rv32-2.C | 157 + .../riscv/rvv/base/vsaddu_vx_tum_rv32-3.C | 157 + .../riscv/rvv/base/vsaddu_vx_tum_rv64-1.C | 160 + .../riscv/rvv/base/vsaddu_vx_tum_rv64-2.C | 160 + .../riscv/rvv/base/vsaddu_vx_tum_rv64-3.C | 160 + .../riscv/rvv/base/vsaddu_vx_tumu_rv32-1.C | 157 + .../riscv/rvv/base/vsaddu_vx_tumu_rv32-2.C | 157 + .../riscv/rvv/base/vsaddu_vx_tumu_rv32-3.C | 157 + .../riscv/rvv/base/vsaddu_vx_tumu_rv64-1.C | 160 + .../riscv/rvv/base/vsaddu_vx_tumu_rv64-2.C | 160 + .../riscv/rvv/base/vsaddu_vx_tumu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vsbc_vvm-1.C | 292 + .../g++.target/riscv/rvv/base/vsbc_vvm-2.C | 292 + .../g++.target/riscv/rvv/base/vsbc_vvm-3.C | 292 + .../g++.target/riscv/rvv/base/vsbc_vvm_tu-1.C | 292 + .../g++.target/riscv/rvv/base/vsbc_vvm_tu-2.C | 292 + .../g++.target/riscv/rvv/base/vsbc_vvm_tu-3.C | 292 + .../g++.target/riscv/rvv/base/vsbc_vxm_rv32-1.C | 289 + .../g++.target/riscv/rvv/base/vsbc_vxm_rv32-2.C | 289 + .../g++.target/riscv/rvv/base/vsbc_vxm_rv32-3.C | 289 + .../g++.target/riscv/rvv/base/vsbc_vxm_rv64-1.C | 292 + .../g++.target/riscv/rvv/base/vsbc_vxm_rv64-2.C | 292 + .../g++.target/riscv/rvv/base/vsbc_vxm_rv64-3.C | 292 + .../g++.target/riscv/rvv/base/vsbc_vxm_tu_rv32-1.C | 289 + .../g++.target/riscv/rvv/base/vsbc_vxm_tu_rv32-2.C | 289 + .../g++.target/riscv/rvv/base/vsbc_vxm_tu_rv32-3.C | 289 + .../g++.target/riscv/rvv/base/vsbc_vxm_tu_rv64-1.C | 292 + .../g++.target/riscv/rvv/base/vsbc_vxm_tu_rv64-2.C | 292 + .../g++.target/riscv/rvv/base/vsbc_vxm_tu_rv64-3.C | 292 + .../g++.target/riscv/rvv/base/vsext_vf2-1.C | 216 + .../g++.target/riscv/rvv/base/vsext_vf2-2.C | 216 + .../g++.target/riscv/rvv/base/vsext_vf2-3.C | 216 + .../g++.target/riscv/rvv/base/vsext_vf2_mu-1.C | 111 + .../g++.target/riscv/rvv/base/vsext_vf2_mu-2.C | 111 + .../g++.target/riscv/rvv/base/vsext_vf2_mu-3.C | 111 + .../g++.target/riscv/rvv/base/vsext_vf2_tu-1.C | 111 + .../g++.target/riscv/rvv/base/vsext_vf2_tu-2.C | 111 + .../g++.target/riscv/rvv/base/vsext_vf2_tu-3.C | 111 + .../g++.target/riscv/rvv/base/vsext_vf2_tum-1.C | 111 + .../g++.target/riscv/rvv/base/vsext_vf2_tum-2.C | 111 + .../g++.target/riscv/rvv/base/vsext_vf2_tum-3.C | 111 + .../g++.target/riscv/rvv/base/vsext_vf2_tumu-1.C | 111 + .../g++.target/riscv/rvv/base/vsext_vf2_tumu-2.C | 111 + .../g++.target/riscv/rvv/base/vsext_vf2_tumu-3.C | 111 + .../g++.target/riscv/rvv/base/vsext_vf4-1.C | 132 + .../g++.target/riscv/rvv/base/vsext_vf4-2.C | 132 + .../g++.target/riscv/rvv/base/vsext_vf4-3.C | 132 + .../g++.target/riscv/rvv/base/vsext_vf4_mu-1.C | 69 + .../g++.target/riscv/rvv/base/vsext_vf4_mu-2.C | 69 + .../g++.target/riscv/rvv/base/vsext_vf4_mu-3.C | 69 + .../g++.target/riscv/rvv/base/vsext_vf4_tu-1.C | 69 + .../g++.target/riscv/rvv/base/vsext_vf4_tu-2.C | 69 + .../g++.target/riscv/rvv/base/vsext_vf4_tu-3.C | 69 + .../g++.target/riscv/rvv/base/vsext_vf4_tum-1.C | 69 + .../g++.target/riscv/rvv/base/vsext_vf4_tum-2.C | 69 + .../g++.target/riscv/rvv/base/vsext_vf4_tum-3.C | 69 + .../g++.target/riscv/rvv/base/vsext_vf4_tumu-1.C | 69 + .../g++.target/riscv/rvv/base/vsext_vf4_tumu-2.C | 69 + .../g++.target/riscv/rvv/base/vsext_vf4_tumu-3.C | 69 + .../g++.target/riscv/rvv/base/vsext_vf8-1.C | 62 + .../g++.target/riscv/rvv/base/vsext_vf8-2.C | 62 + .../g++.target/riscv/rvv/base/vsext_vf8-3.C | 62 + .../g++.target/riscv/rvv/base/vsext_vf8_mu-1.C | 34 + .../g++.target/riscv/rvv/base/vsext_vf8_mu-2.C | 34 + .../g++.target/riscv/rvv/base/vsext_vf8_mu-3.C | 34 + .../g++.target/riscv/rvv/base/vsext_vf8_tu-1.C | 34 + .../g++.target/riscv/rvv/base/vsext_vf8_tu-2.C | 34 + .../g++.target/riscv/rvv/base/vsext_vf8_tu-3.C | 34 + .../g++.target/riscv/rvv/base/vsext_vf8_tum-1.C | 34 + .../g++.target/riscv/rvv/base/vsext_vf8_tum-2.C | 34 + .../g++.target/riscv/rvv/base/vsext_vf8_tum-3.C | 34 + .../g++.target/riscv/rvv/base/vsext_vf8_tumu-1.C | 34 + .../g++.target/riscv/rvv/base/vsext_vf8_tumu-2.C | 34 + .../g++.target/riscv/rvv/base/vsext_vf8_tumu-3.C | 34 + .../g++.target/riscv/rvv/base/vsll_vv-1.C | 578 + .../g++.target/riscv/rvv/base/vsll_vv-2.C | 578 + .../g++.target/riscv/rvv/base/vsll_vv-3.C | 578 + .../g++.target/riscv/rvv/base/vsll_vv_mu-1.C | 292 + .../g++.target/riscv/rvv/base/vsll_vv_mu-2.C | 292 + .../g++.target/riscv/rvv/base/vsll_vv_mu-3.C | 292 + .../g++.target/riscv/rvv/base/vsll_vv_tu-1.C | 292 + .../g++.target/riscv/rvv/base/vsll_vv_tu-2.C | 292 + .../g++.target/riscv/rvv/base/vsll_vv_tu-3.C | 292 + .../g++.target/riscv/rvv/base/vsll_vv_tum-1.C | 292 + .../g++.target/riscv/rvv/base/vsll_vv_tum-2.C | 292 + .../g++.target/riscv/rvv/base/vsll_vv_tum-3.C | 292 + .../g++.target/riscv/rvv/base/vsll_vv_tumu-1.C | 292 + .../g++.target/riscv/rvv/base/vsll_vv_tumu-2.C | 292 + .../g++.target/riscv/rvv/base/vsll_vv_tumu-3.C | 292 + .../g++.target/riscv/rvv/base/vsll_vx-1.C | 578 + .../g++.target/riscv/rvv/base/vsll_vx-2.C | 578 + .../g++.target/riscv/rvv/base/vsll_vx-3.C | 578 + .../g++.target/riscv/rvv/base/vsll_vx_mu-1.C | 292 + .../g++.target/riscv/rvv/base/vsll_vx_mu-2.C | 292 + .../g++.target/riscv/rvv/base/vsll_vx_mu-3.C | 292 + .../g++.target/riscv/rvv/base/vsll_vx_tu-1.C | 292 + .../g++.target/riscv/rvv/base/vsll_vx_tu-2.C | 292 + .../g++.target/riscv/rvv/base/vsll_vx_tu-3.C | 292 + .../g++.target/riscv/rvv/base/vsll_vx_tum-1.C | 292 + .../g++.target/riscv/rvv/base/vsll_vx_tum-2.C | 292 + .../g++.target/riscv/rvv/base/vsll_vx_tum-3.C | 292 + .../g++.target/riscv/rvv/base/vsll_vx_tumu-1.C | 292 + .../g++.target/riscv/rvv/base/vsll_vx_tumu-2.C | 292 + .../g++.target/riscv/rvv/base/vsll_vx_tumu-3.C | 292 + .../g++.target/riscv/rvv/base/vsmul_vv-1.C | 314 + .../g++.target/riscv/rvv/base/vsmul_vv-2.C | 314 + .../g++.target/riscv/rvv/base/vsmul_vv-3.C | 314 + .../g++.target/riscv/rvv/base/vsmul_vv_mu-1.C | 160 + .../g++.target/riscv/rvv/base/vsmul_vv_mu-2.C | 160 + .../g++.target/riscv/rvv/base/vsmul_vv_mu-3.C | 160 + .../g++.target/riscv/rvv/base/vsmul_vv_tu-1.C | 160 + .../g++.target/riscv/rvv/base/vsmul_vv_tu-2.C | 160 + .../g++.target/riscv/rvv/base/vsmul_vv_tu-3.C | 160 + .../g++.target/riscv/rvv/base/vsmul_vv_tum-1.C | 160 + .../g++.target/riscv/rvv/base/vsmul_vv_tum-2.C | 160 + .../g++.target/riscv/rvv/base/vsmul_vv_tum-3.C | 160 + .../g++.target/riscv/rvv/base/vsmul_vv_tumu-1.C | 160 + .../g++.target/riscv/rvv/base/vsmul_vv_tumu-2.C | 160 + .../g++.target/riscv/rvv/base/vsmul_vv_tumu-3.C | 160 + .../g++.target/riscv/rvv/base/vsmul_vx_mu_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vsmul_vx_mu_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vsmul_vx_mu_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vsmul_vx_mu_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vsmul_vx_mu_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vsmul_vx_mu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vsmul_vx_rv32-1.C | 308 + .../g++.target/riscv/rvv/base/vsmul_vx_rv32-2.C | 308 + .../g++.target/riscv/rvv/base/vsmul_vx_rv32-3.C | 308 + .../g++.target/riscv/rvv/base/vsmul_vx_rv64-1.C | 314 + .../g++.target/riscv/rvv/base/vsmul_vx_rv64-2.C | 314 + .../g++.target/riscv/rvv/base/vsmul_vx_rv64-3.C | 314 + .../g++.target/riscv/rvv/base/vsmul_vx_tu_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vsmul_vx_tu_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vsmul_vx_tu_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vsmul_vx_tu_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vsmul_vx_tu_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vsmul_vx_tu_rv64-3.C | 160 + .../riscv/rvv/base/vsmul_vx_tum_rv32-1.C | 157 + .../riscv/rvv/base/vsmul_vx_tum_rv32-2.C | 157 + .../riscv/rvv/base/vsmul_vx_tum_rv32-3.C | 157 + .../riscv/rvv/base/vsmul_vx_tum_rv64-1.C | 160 + .../riscv/rvv/base/vsmul_vx_tum_rv64-2.C | 160 + .../riscv/rvv/base/vsmul_vx_tum_rv64-3.C | 160 + .../riscv/rvv/base/vsmul_vx_tumu_rv32-1.C | 157 + .../riscv/rvv/base/vsmul_vx_tumu_rv32-2.C | 157 + .../riscv/rvv/base/vsmul_vx_tumu_rv32-3.C | 157 + .../riscv/rvv/base/vsmul_vx_tumu_rv64-1.C | 160 + .../riscv/rvv/base/vsmul_vx_tumu_rv64-2.C | 160 + .../riscv/rvv/base/vsmul_vx_tumu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vsra_vv-1.C | 314 + .../g++.target/riscv/rvv/base/vsra_vv-2.C | 314 + .../g++.target/riscv/rvv/base/vsra_vv-3.C | 314 + .../g++.target/riscv/rvv/base/vsra_vv_mu-1.C | 160 + .../g++.target/riscv/rvv/base/vsra_vv_mu-2.C | 160 + .../g++.target/riscv/rvv/base/vsra_vv_mu-3.C | 160 + .../g++.target/riscv/rvv/base/vsra_vv_tu-1.C | 160 + .../g++.target/riscv/rvv/base/vsra_vv_tu-2.C | 160 + .../g++.target/riscv/rvv/base/vsra_vv_tu-3.C | 160 + .../g++.target/riscv/rvv/base/vsra_vv_tum-1.C | 160 + .../g++.target/riscv/rvv/base/vsra_vv_tum-2.C | 160 + .../g++.target/riscv/rvv/base/vsra_vv_tum-3.C | 160 + .../g++.target/riscv/rvv/base/vsra_vv_tumu-1.C | 160 + .../g++.target/riscv/rvv/base/vsra_vv_tumu-2.C | 160 + .../g++.target/riscv/rvv/base/vsra_vv_tumu-3.C | 160 + .../g++.target/riscv/rvv/base/vsra_vx-1.C | 314 + .../g++.target/riscv/rvv/base/vsra_vx-2.C | 314 + .../g++.target/riscv/rvv/base/vsra_vx-3.C | 314 + .../g++.target/riscv/rvv/base/vsra_vx_mu-1.C | 160 + .../g++.target/riscv/rvv/base/vsra_vx_mu-2.C | 160 + .../g++.target/riscv/rvv/base/vsra_vx_mu-3.C | 160 + .../g++.target/riscv/rvv/base/vsra_vx_tu-1.C | 160 + .../g++.target/riscv/rvv/base/vsra_vx_tu-2.C | 160 + .../g++.target/riscv/rvv/base/vsra_vx_tu-3.C | 160 + .../g++.target/riscv/rvv/base/vsra_vx_tum-1.C | 160 + .../g++.target/riscv/rvv/base/vsra_vx_tum-2.C | 160 + .../g++.target/riscv/rvv/base/vsra_vx_tum-3.C | 160 + .../g++.target/riscv/rvv/base/vsra_vx_tumu-1.C | 160 + .../g++.target/riscv/rvv/base/vsra_vx_tumu-2.C | 160 + .../g++.target/riscv/rvv/base/vsra_vx_tumu-3.C | 160 + .../g++.target/riscv/rvv/base/vsrl_vv-1.C | 314 + .../g++.target/riscv/rvv/base/vsrl_vv-2.C | 314 + .../g++.target/riscv/rvv/base/vsrl_vv-3.C | 314 + .../g++.target/riscv/rvv/base/vsrl_vv_mu-1.C | 160 + .../g++.target/riscv/rvv/base/vsrl_vv_mu-2.C | 160 + .../g++.target/riscv/rvv/base/vsrl_vv_mu-3.C | 160 + .../g++.target/riscv/rvv/base/vsrl_vv_tu-1.C | 160 + .../g++.target/riscv/rvv/base/vsrl_vv_tu-2.C | 160 + .../g++.target/riscv/rvv/base/vsrl_vv_tu-3.C | 160 + .../g++.target/riscv/rvv/base/vsrl_vv_tum-1.C | 160 + .../g++.target/riscv/rvv/base/vsrl_vv_tum-2.C | 160 + .../g++.target/riscv/rvv/base/vsrl_vv_tum-3.C | 160 + .../g++.target/riscv/rvv/base/vsrl_vv_tumu-1.C | 160 + .../g++.target/riscv/rvv/base/vsrl_vv_tumu-2.C | 160 + .../g++.target/riscv/rvv/base/vsrl_vv_tumu-3.C | 160 + .../g++.target/riscv/rvv/base/vsrl_vx-1.C | 314 + .../g++.target/riscv/rvv/base/vsrl_vx-2.C | 314 + .../g++.target/riscv/rvv/base/vsrl_vx-3.C | 314 + .../g++.target/riscv/rvv/base/vsrl_vx_mu-1.C | 160 + .../g++.target/riscv/rvv/base/vsrl_vx_mu-2.C | 160 + .../g++.target/riscv/rvv/base/vsrl_vx_mu-3.C | 160 + .../g++.target/riscv/rvv/base/vsrl_vx_tu-1.C | 160 + .../g++.target/riscv/rvv/base/vsrl_vx_tu-2.C | 160 + .../g++.target/riscv/rvv/base/vsrl_vx_tu-3.C | 160 + .../g++.target/riscv/rvv/base/vsrl_vx_tum-1.C | 160 + .../g++.target/riscv/rvv/base/vsrl_vx_tum-2.C | 160 + .../g++.target/riscv/rvv/base/vsrl_vx_tum-3.C | 160 + .../g++.target/riscv/rvv/base/vsrl_vx_tumu-1.C | 160 + .../g++.target/riscv/rvv/base/vsrl_vx_tumu-2.C | 160 + .../g++.target/riscv/rvv/base/vsrl_vx_tumu-3.C | 160 + .../g++.target/riscv/rvv/base/vssra_vv-1.C | 314 + .../g++.target/riscv/rvv/base/vssra_vv-2.C | 314 + .../g++.target/riscv/rvv/base/vssra_vv-3.C | 314 + .../g++.target/riscv/rvv/base/vssra_vv_mu-1.C | 160 + .../g++.target/riscv/rvv/base/vssra_vv_mu-2.C | 160 + .../g++.target/riscv/rvv/base/vssra_vv_mu-3.C | 160 + .../g++.target/riscv/rvv/base/vssra_vv_tu-1.C | 160 + .../g++.target/riscv/rvv/base/vssra_vv_tu-2.C | 160 + .../g++.target/riscv/rvv/base/vssra_vv_tu-3.C | 160 + .../g++.target/riscv/rvv/base/vssra_vv_tum-1.C | 160 + .../g++.target/riscv/rvv/base/vssra_vv_tum-2.C | 160 + .../g++.target/riscv/rvv/base/vssra_vv_tum-3.C | 160 + .../g++.target/riscv/rvv/base/vssra_vv_tumu-1.C | 160 + .../g++.target/riscv/rvv/base/vssra_vv_tumu-2.C | 160 + .../g++.target/riscv/rvv/base/vssra_vv_tumu-3.C | 160 + .../g++.target/riscv/rvv/base/vssra_vx-1.C | 314 + .../g++.target/riscv/rvv/base/vssra_vx-2.C | 314 + .../g++.target/riscv/rvv/base/vssra_vx-3.C | 314 + .../g++.target/riscv/rvv/base/vssra_vx_mu-1.C | 160 + .../g++.target/riscv/rvv/base/vssra_vx_mu-2.C | 160 + .../g++.target/riscv/rvv/base/vssra_vx_mu-3.C | 160 + .../g++.target/riscv/rvv/base/vssra_vx_tu-1.C | 160 + .../g++.target/riscv/rvv/base/vssra_vx_tu-2.C | 160 + .../g++.target/riscv/rvv/base/vssra_vx_tu-3.C | 160 + .../g++.target/riscv/rvv/base/vssra_vx_tum-1.C | 160 + .../g++.target/riscv/rvv/base/vssra_vx_tum-2.C | 160 + .../g++.target/riscv/rvv/base/vssra_vx_tum-3.C | 160 + .../g++.target/riscv/rvv/base/vssra_vx_tumu-1.C | 160 + .../g++.target/riscv/rvv/base/vssra_vx_tumu-2.C | 160 + .../g++.target/riscv/rvv/base/vssra_vx_tumu-3.C | 160 + .../g++.target/riscv/rvv/base/vssrl_vv-1.C | 314 + .../g++.target/riscv/rvv/base/vssrl_vv-2.C | 314 + .../g++.target/riscv/rvv/base/vssrl_vv-3.C | 314 + .../g++.target/riscv/rvv/base/vssrl_vv_mu-1.C | 160 + .../g++.target/riscv/rvv/base/vssrl_vv_mu-2.C | 160 + .../g++.target/riscv/rvv/base/vssrl_vv_mu-3.C | 160 + .../g++.target/riscv/rvv/base/vssrl_vv_tu-1.C | 160 + .../g++.target/riscv/rvv/base/vssrl_vv_tu-2.C | 160 + .../g++.target/riscv/rvv/base/vssrl_vv_tu-3.C | 160 + .../g++.target/riscv/rvv/base/vssrl_vv_tum-1.C | 160 + .../g++.target/riscv/rvv/base/vssrl_vv_tum-2.C | 160 + .../g++.target/riscv/rvv/base/vssrl_vv_tum-3.C | 160 + .../g++.target/riscv/rvv/base/vssrl_vv_tumu-1.C | 160 + .../g++.target/riscv/rvv/base/vssrl_vv_tumu-2.C | 160 + .../g++.target/riscv/rvv/base/vssrl_vv_tumu-3.C | 160 + .../g++.target/riscv/rvv/base/vssrl_vx-1.C | 314 + .../g++.target/riscv/rvv/base/vssrl_vx-2.C | 314 + .../g++.target/riscv/rvv/base/vssrl_vx-3.C | 314 + .../g++.target/riscv/rvv/base/vssrl_vx_mu-1.C | 160 + .../g++.target/riscv/rvv/base/vssrl_vx_mu-2.C | 160 + .../g++.target/riscv/rvv/base/vssrl_vx_mu-3.C | 160 + .../g++.target/riscv/rvv/base/vssrl_vx_tu-1.C | 160 + .../g++.target/riscv/rvv/base/vssrl_vx_tu-2.C | 160 + .../g++.target/riscv/rvv/base/vssrl_vx_tu-3.C | 160 + .../g++.target/riscv/rvv/base/vssrl_vx_tum-1.C | 160 + .../g++.target/riscv/rvv/base/vssrl_vx_tum-2.C | 160 + .../g++.target/riscv/rvv/base/vssrl_vx_tum-3.C | 160 + .../g++.target/riscv/rvv/base/vssrl_vx_tumu-1.C | 160 + .../g++.target/riscv/rvv/base/vssrl_vx_tumu-2.C | 160 + .../g++.target/riscv/rvv/base/vssrl_vx_tumu-3.C | 160 + .../g++.target/riscv/rvv/base/vssub_vv-1.C | 314 + .../g++.target/riscv/rvv/base/vssub_vv-2.C | 314 + .../g++.target/riscv/rvv/base/vssub_vv-3.C | 314 + .../g++.target/riscv/rvv/base/vssub_vv_mu-1.C | 160 + .../g++.target/riscv/rvv/base/vssub_vv_mu-2.C | 160 + .../g++.target/riscv/rvv/base/vssub_vv_mu-3.C | 160 + .../g++.target/riscv/rvv/base/vssub_vv_tu-1.C | 160 + .../g++.target/riscv/rvv/base/vssub_vv_tu-2.C | 160 + .../g++.target/riscv/rvv/base/vssub_vv_tu-3.C | 160 + .../g++.target/riscv/rvv/base/vssub_vv_tum-1.C | 160 + .../g++.target/riscv/rvv/base/vssub_vv_tum-2.C | 160 + .../g++.target/riscv/rvv/base/vssub_vv_tum-3.C | 160 + .../g++.target/riscv/rvv/base/vssub_vv_tumu-1.C | 160 + .../g++.target/riscv/rvv/base/vssub_vv_tumu-2.C | 160 + .../g++.target/riscv/rvv/base/vssub_vv_tumu-3.C | 160 + .../g++.target/riscv/rvv/base/vssub_vx_mu_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vssub_vx_mu_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vssub_vx_mu_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vssub_vx_mu_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vssub_vx_mu_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vssub_vx_mu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vssub_vx_rv32-1.C | 308 + .../g++.target/riscv/rvv/base/vssub_vx_rv32-2.C | 308 + .../g++.target/riscv/rvv/base/vssub_vx_rv32-3.C | 308 + .../g++.target/riscv/rvv/base/vssub_vx_rv64-1.C | 314 + .../g++.target/riscv/rvv/base/vssub_vx_rv64-2.C | 314 + .../g++.target/riscv/rvv/base/vssub_vx_rv64-3.C | 314 + .../g++.target/riscv/rvv/base/vssub_vx_tu_rv32-1.C | 157 + .../g++.target/riscv/rvv/base/vssub_vx_tu_rv32-2.C | 157 + .../g++.target/riscv/rvv/base/vssub_vx_tu_rv32-3.C | 157 + .../g++.target/riscv/rvv/base/vssub_vx_tu_rv64-1.C | 160 + .../g++.target/riscv/rvv/base/vssub_vx_tu_rv64-2.C | 160 + .../g++.target/riscv/rvv/base/vssub_vx_tu_rv64-3.C | 160 + .../riscv/rvv/base/vssub_vx_tum_rv32-1.C | 157 + .../riscv/rvv/base/vssub_vx_tum_rv32-2.C | 157 + .../riscv/rvv/base/vssub_vx_tum_rv32-3.C | 157 + .../riscv/rvv/base/vssub_vx_tum_rv64-1.C | 160 + .../riscv/rvv/base/vssub_vx_tum_rv64-2.C | 160 + .../riscv/rvv/base/vssub_vx_tum_rv64-3.C | 160 + .../riscv/rvv/base/vssub_vx_tumu_rv32-1.C | 157 + .../riscv/rvv/base/vssub_vx_tumu_rv32-2.C | 157 + .../riscv/rvv/base/vssub_vx_tumu_rv32-3.C | 157 + .../riscv/rvv/base/vssub_vx_tumu_rv64-1.C | 160 + .../riscv/rvv/base/vssub_vx_tumu_rv64-2.C | 160 + .../riscv/rvv/base/vssub_vx_tumu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vssubu_vv-1.C | 314 + .../g++.target/riscv/rvv/base/vssubu_vv-2.C | 314 + .../g++.target/riscv/rvv/base/vssubu_vv-3.C | 314 + .../g++.target/riscv/rvv/base/vssubu_vv_mu-1.C | 160 + .../g++.target/riscv/rvv/base/vssubu_vv_mu-2.C | 160 + .../g++.target/riscv/rvv/base/vssubu_vv_mu-3.C | 160 + .../g++.target/riscv/rvv/base/vssubu_vv_tu-1.C | 160 + .../g++.target/riscv/rvv/base/vssubu_vv_tu-2.C | 160 + .../g++.target/riscv/rvv/base/vssubu_vv_tu-3.C | 160 + .../g++.target/riscv/rvv/base/vssubu_vv_tum-1.C | 160 + .../g++.target/riscv/rvv/base/vssubu_vv_tum-2.C | 160 + .../g++.target/riscv/rvv/base/vssubu_vv_tum-3.C | 160 + .../g++.target/riscv/rvv/base/vssubu_vv_tumu-1.C | 160 + .../g++.target/riscv/rvv/base/vssubu_vv_tumu-2.C | 160 + .../g++.target/riscv/rvv/base/vssubu_vv_tumu-3.C | 160 + .../riscv/rvv/base/vssubu_vx_mu_rv32-1.C | 157 + .../riscv/rvv/base/vssubu_vx_mu_rv32-2.C | 157 + .../riscv/rvv/base/vssubu_vx_mu_rv32-3.C | 157 + .../riscv/rvv/base/vssubu_vx_mu_rv64-1.C | 160 + .../riscv/rvv/base/vssubu_vx_mu_rv64-2.C | 160 + .../riscv/rvv/base/vssubu_vx_mu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vssubu_vx_rv32-1.C | 308 + .../g++.target/riscv/rvv/base/vssubu_vx_rv32-2.C | 308 + .../g++.target/riscv/rvv/base/vssubu_vx_rv32-3.C | 308 + .../g++.target/riscv/rvv/base/vssubu_vx_rv64-1.C | 314 + .../g++.target/riscv/rvv/base/vssubu_vx_rv64-2.C | 314 + .../g++.target/riscv/rvv/base/vssubu_vx_rv64-3.C | 314 + .../riscv/rvv/base/vssubu_vx_tu_rv32-1.C | 157 + .../riscv/rvv/base/vssubu_vx_tu_rv32-2.C | 157 + .../riscv/rvv/base/vssubu_vx_tu_rv32-3.C | 157 + .../riscv/rvv/base/vssubu_vx_tu_rv64-1.C | 160 + .../riscv/rvv/base/vssubu_vx_tu_rv64-2.C | 160 + .../riscv/rvv/base/vssubu_vx_tu_rv64-3.C | 160 + .../riscv/rvv/base/vssubu_vx_tum_rv32-1.C | 157 + .../riscv/rvv/base/vssubu_vx_tum_rv32-2.C | 157 + .../riscv/rvv/base/vssubu_vx_tum_rv32-3.C | 157 + .../riscv/rvv/base/vssubu_vx_tum_rv64-1.C | 160 + .../riscv/rvv/base/vssubu_vx_tum_rv64-2.C | 160 + .../riscv/rvv/base/vssubu_vx_tum_rv64-3.C | 160 + .../riscv/rvv/base/vssubu_vx_tumu_rv32-1.C | 157 + .../riscv/rvv/base/vssubu_vx_tumu_rv32-2.C | 157 + .../riscv/rvv/base/vssubu_vx_tumu_rv32-3.C | 157 + .../riscv/rvv/base/vssubu_vx_tumu_rv64-1.C | 160 + .../riscv/rvv/base/vssubu_vx_tumu_rv64-2.C | 160 + .../riscv/rvv/base/vssubu_vx_tumu_rv64-3.C | 160 + .../g++.target/riscv/rvv/base/vsub_vv-1.C | 578 + .../g++.target/riscv/rvv/base/vsub_vv-2.C | 578 + .../g++.target/riscv/rvv/base/vsub_vv-3.C | 578 + .../g++.target/riscv/rvv/base/vsub_vv_mu-1.C | 292 + .../g++.target/riscv/rvv/base/vsub_vv_mu-2.C | 292 + .../g++.target/riscv/rvv/base/vsub_vv_mu-3.C | 292 + .../g++.target/riscv/rvv/base/vsub_vv_tu-1.C | 292 + .../g++.target/riscv/rvv/base/vsub_vv_tu-2.C | 292 + .../g++.target/riscv/rvv/base/vsub_vv_tu-3.C | 292 + .../g++.target/riscv/rvv/base/vsub_vv_tum-1.C | 292 + .../g++.target/riscv/rvv/base/vsub_vv_tum-2.C | 292 + .../g++.target/riscv/rvv/base/vsub_vv_tum-3.C | 292 + .../g++.target/riscv/rvv/base/vsub_vv_tumu-1.C | 292 + .../g++.target/riscv/rvv/base/vsub_vv_tumu-2.C | 292 + .../g++.target/riscv/rvv/base/vsub_vv_tumu-3.C | 292 + .../g++.target/riscv/rvv/base/vsub_vx_mu_rv32-1.C | 289 + .../g++.target/riscv/rvv/base/vsub_vx_mu_rv32-2.C | 289 + .../g++.target/riscv/rvv/base/vsub_vx_mu_rv32-3.C | 289 + .../g++.target/riscv/rvv/base/vsub_vx_mu_rv64-1.C | 292 + .../g++.target/riscv/rvv/base/vsub_vx_mu_rv64-2.C | 292 + .../g++.target/riscv/rvv/base/vsub_vx_mu_rv64-3.C | 292 + .../g++.target/riscv/rvv/base/vsub_vx_rv32-1.C | 572 + .../g++.target/riscv/rvv/base/vsub_vx_rv32-2.C | 572 + .../g++.target/riscv/rvv/base/vsub_vx_rv32-3.C | 572 + .../g++.target/riscv/rvv/base/vsub_vx_rv64-1.C | 578 + .../g++.target/riscv/rvv/base/vsub_vx_rv64-2.C | 578 + .../g++.target/riscv/rvv/base/vsub_vx_rv64-3.C | 578 + .../g++.target/riscv/rvv/base/vsub_vx_tu_rv32-1.C | 289 + .../g++.target/riscv/rvv/base/vsub_vx_tu_rv32-2.C | 289 + .../g++.target/riscv/rvv/base/vsub_vx_tu_rv32-3.C | 289 + .../g++.target/riscv/rvv/base/vsub_vx_tu_rv64-1.C | 292 + .../g++.target/riscv/rvv/base/vsub_vx_tu_rv64-2.C | 292 + .../g++.target/riscv/rvv/base/vsub_vx_tu_rv64-3.C | 292 + .../g++.target/riscv/rvv/base/vsub_vx_tum_rv32-1.C | 289 + .../g++.target/riscv/rvv/base/vsub_vx_tum_rv32-2.C | 289 + .../g++.target/riscv/rvv/base/vsub_vx_tum_rv32-3.C | 289 + .../g++.target/riscv/rvv/base/vsub_vx_tum_rv64-1.C | 292 + .../g++.target/riscv/rvv/base/vsub_vx_tum_rv64-2.C | 292 + .../g++.target/riscv/rvv/base/vsub_vx_tum_rv64-3.C | 292 + .../riscv/rvv/base/vsub_vx_tumu_rv32-1.C | 289 + .../riscv/rvv/base/vsub_vx_tumu_rv32-2.C | 289 + .../riscv/rvv/base/vsub_vx_tumu_rv32-3.C | 289 + .../riscv/rvv/base/vsub_vx_tumu_rv64-1.C | 292 + .../riscv/rvv/base/vsub_vx_tumu_rv64-2.C | 292 + .../riscv/rvv/base/vsub_vx_tumu_rv64-3.C | 292 + .../g++.target/riscv/rvv/base/vwadd_vv-1.C | 216 + .../g++.target/riscv/rvv/base/vwadd_vv-2.C | 216 + .../g++.target/riscv/rvv/base/vwadd_vv-3.C | 216 + .../g++.target/riscv/rvv/base/vwadd_vv_mu-1.C | 111 + .../g++.target/riscv/rvv/base/vwadd_vv_mu-2.C | 111 + .../g++.target/riscv/rvv/base/vwadd_vv_mu-3.C | 111 + .../g++.target/riscv/rvv/base/vwadd_vv_tu-1.C | 111 + .../g++.target/riscv/rvv/base/vwadd_vv_tu-2.C | 111 + .../g++.target/riscv/rvv/base/vwadd_vv_tu-3.C | 111 + .../g++.target/riscv/rvv/base/vwadd_vv_tum-1.C | 111 + .../g++.target/riscv/rvv/base/vwadd_vv_tum-2.C | 111 + .../g++.target/riscv/rvv/base/vwadd_vv_tum-3.C | 111 + .../g++.target/riscv/rvv/base/vwadd_vv_tumu-1.C | 111 + .../g++.target/riscv/rvv/base/vwadd_vv_tumu-2.C | 111 + .../g++.target/riscv/rvv/base/vwadd_vv_tumu-3.C | 111 + .../g++.target/riscv/rvv/base/vwadd_vx-1.C | 216 + .../g++.target/riscv/rvv/base/vwadd_vx-2.C | 216 + .../g++.target/riscv/rvv/base/vwadd_vx-3.C | 216 + .../g++.target/riscv/rvv/base/vwadd_vx_mu-1.C | 111 + .../g++.target/riscv/rvv/base/vwadd_vx_mu-2.C | 111 + .../g++.target/riscv/rvv/base/vwadd_vx_mu-3.C | 111 + .../g++.target/riscv/rvv/base/vwadd_vx_tu-1.C | 111 + .../g++.target/riscv/rvv/base/vwadd_vx_tu-2.C | 111 + .../g++.target/riscv/rvv/base/vwadd_vx_tu-3.C | 111 + .../g++.target/riscv/rvv/base/vwadd_vx_tum-1.C | 111 + .../g++.target/riscv/rvv/base/vwadd_vx_tum-2.C | 111 + .../g++.target/riscv/rvv/base/vwadd_vx_tum-3.C | 111 + .../g++.target/riscv/rvv/base/vwadd_vx_tumu-1.C | 111 + .../g++.target/riscv/rvv/base/vwadd_vx_tumu-2.C | 111 + .../g++.target/riscv/rvv/base/vwadd_vx_tumu-3.C | 111 + .../g++.target/riscv/rvv/base/vwadd_wv-1.C | 216 + .../g++.target/riscv/rvv/base/vwadd_wv-2.C | 216 + .../g++.target/riscv/rvv/base/vwadd_wv-3.C | 216 + .../g++.target/riscv/rvv/base/vwadd_wv_mu-1.C | 111 + .../g++.target/riscv/rvv/base/vwadd_wv_mu-2.C | 111 + .../g++.target/riscv/rvv/base/vwadd_wv_mu-3.C | 111 + .../g++.target/riscv/rvv/base/vwadd_wv_tu-1.C | 111 + .../g++.target/riscv/rvv/base/vwadd_wv_tu-2.C | 111 + .../g++.target/riscv/rvv/base/vwadd_wv_tu-3.C | 111 + .../g++.target/riscv/rvv/base/vwadd_wv_tum-1.C | 111 + .../g++.target/riscv/rvv/base/vwadd_wv_tum-2.C | 111 + .../g++.target/riscv/rvv/base/vwadd_wv_tum-3.C | 111 + .../g++.target/riscv/rvv/base/vwadd_wv_tumu-1.C | 111 + .../g++.target/riscv/rvv/base/vwadd_wv_tumu-2.C | 111 + .../g++.target/riscv/rvv/base/vwadd_wv_tumu-3.C | 111 + .../g++.target/riscv/rvv/base/vwadd_wx-1.C | 216 + .../g++.target/riscv/rvv/base/vwadd_wx-2.C | 216 + .../g++.target/riscv/rvv/base/vwadd_wx-3.C | 216 + .../g++.target/riscv/rvv/base/vwadd_wx_mu-1.C | 111 + .../g++.target/riscv/rvv/base/vwadd_wx_mu-2.C | 111 + .../g++.target/riscv/rvv/base/vwadd_wx_mu-3.C | 111 + .../g++.target/riscv/rvv/base/vwadd_wx_tu-1.C | 111 + .../g++.target/riscv/rvv/base/vwadd_wx_tu-2.C | 111 + .../g++.target/riscv/rvv/base/vwadd_wx_tu-3.C | 111 + .../g++.target/riscv/rvv/base/vwadd_wx_tum-1.C | 111 + .../g++.target/riscv/rvv/base/vwadd_wx_tum-2.C | 111 + .../g++.target/riscv/rvv/base/vwadd_wx_tum-3.C | 111 + .../g++.target/riscv/rvv/base/vwadd_wx_tumu-1.C | 111 + .../g++.target/riscv/rvv/base/vwadd_wx_tumu-2.C | 111 + .../g++.target/riscv/rvv/base/vwadd_wx_tumu-3.C | 111 + .../g++.target/riscv/rvv/base/vwaddu_vv-1.C | 216 + .../g++.target/riscv/rvv/base/vwaddu_vv-2.C | 216 + .../g++.target/riscv/rvv/base/vwaddu_vv-3.C | 216 + .../g++.target/riscv/rvv/base/vwaddu_vv_mu-1.C | 111 + .../g++.target/riscv/rvv/base/vwaddu_vv_mu-2.C | 111 + .../g++.target/riscv/rvv/base/vwaddu_vv_mu-3.C | 111 + .../g++.target/riscv/rvv/base/vwaddu_vv_tu-1.C | 111 + .../g++.target/riscv/rvv/base/vwaddu_vv_tu-2.C | 111 + .../g++.target/riscv/rvv/base/vwaddu_vv_tu-3.C | 111 + .../g++.target/riscv/rvv/base/vwaddu_vv_tum-1.C | 111 + .../g++.target/riscv/rvv/base/vwaddu_vv_tum-2.C | 111 + .../g++.target/riscv/rvv/base/vwaddu_vv_tum-3.C | 111 + .../g++.target/riscv/rvv/base/vwaddu_vv_tumu-1.C | 111 + .../g++.target/riscv/rvv/base/vwaddu_vv_tumu-2.C | 111 + .../g++.target/riscv/rvv/base/vwaddu_vv_tumu-3.C | 111 + .../g++.target/riscv/rvv/base/vwaddu_vx-1.C | 216 + .../g++.target/riscv/rvv/base/vwaddu_vx-2.C | 216 + .../g++.target/riscv/rvv/base/vwaddu_vx-3.C | 216 + .../g++.target/riscv/rvv/base/vwaddu_vx_mu-1.C | 111 + .../g++.target/riscv/rvv/base/vwaddu_vx_mu-2.C | 111 + .../g++.target/riscv/rvv/base/vwaddu_vx_mu-3.C | 111 + .../g++.target/riscv/rvv/base/vwaddu_vx_tu-1.C | 111 + .../g++.target/riscv/rvv/base/vwaddu_vx_tu-2.C | 111 + .../g++.target/riscv/rvv/base/vwaddu_vx_tu-3.C | 111 + .../g++.target/riscv/rvv/base/vwaddu_vx_tum-1.C | 111 + .../g++.target/riscv/rvv/base/vwaddu_vx_tum-2.C | 111 + .../g++.target/riscv/rvv/base/vwaddu_vx_tum-3.C | 111 + .../g++.target/riscv/rvv/base/vwaddu_vx_tumu-1.C | 111 + .../g++.target/riscv/rvv/base/vwaddu_vx_tumu-2.C | 111 + .../g++.target/riscv/rvv/base/vwaddu_vx_tumu-3.C | 111 + .../g++.target/riscv/rvv/base/vwaddu_wv-1.C | 216 + .../g++.target/riscv/rvv/base/vwaddu_wv-2.C | 216 + .../g++.target/riscv/rvv/base/vwaddu_wv-3.C | 216 + .../g++.target/riscv/rvv/base/vwaddu_wv_mu-1.C | 111 + .../g++.target/riscv/rvv/base/vwaddu_wv_mu-2.C | 111 + .../g++.target/riscv/rvv/base/vwaddu_wv_mu-3.C | 111 + .../g++.target/riscv/rvv/base/vwaddu_wv_tu-1.C | 111 + .../g++.target/riscv/rvv/base/vwaddu_wv_tu-2.C | 111 + .../g++.target/riscv/rvv/base/vwaddu_wv_tu-3.C | 111 + .../g++.target/riscv/rvv/base/vwaddu_wv_tum-1.C | 111 + .../g++.target/riscv/rvv/base/vwaddu_wv_tum-2.C | 111 + .../g++.target/riscv/rvv/base/vwaddu_wv_tum-3.C | 111 + .../g++.target/riscv/rvv/base/vwaddu_wv_tumu-1.C | 111 + .../g++.target/riscv/rvv/base/vwaddu_wv_tumu-2.C | 111 + .../g++.target/riscv/rvv/base/vwaddu_wv_tumu-3.C | 111 + .../g++.target/riscv/rvv/base/vwaddu_wx-1.C | 216 + .../g++.target/riscv/rvv/base/vwaddu_wx-2.C | 216 + .../g++.target/riscv/rvv/base/vwaddu_wx-3.C | 216 + .../g++.target/riscv/rvv/base/vwaddu_wx_mu-1.C | 111 + .../g++.target/riscv/rvv/base/vwaddu_wx_mu-2.C | 111 + .../g++.target/riscv/rvv/base/vwaddu_wx_mu-3.C | 111 + .../g++.target/riscv/rvv/base/vwaddu_wx_tu-1.C | 111 + .../g++.target/riscv/rvv/base/vwaddu_wx_tu-2.C | 111 + .../g++.target/riscv/rvv/base/vwaddu_wx_tu-3.C | 111 + .../g++.target/riscv/rvv/base/vwaddu_wx_tum-1.C | 111 + .../g++.target/riscv/rvv/base/vwaddu_wx_tum-2.C | 111 + .../g++.target/riscv/rvv/base/vwaddu_wx_tum-3.C | 111 + .../g++.target/riscv/rvv/base/vwaddu_wx_tumu-1.C | 111 + .../g++.target/riscv/rvv/base/vwaddu_wx_tumu-2.C | 111 + .../g++.target/riscv/rvv/base/vwaddu_wx_tumu-3.C | 111 + .../g++.target/riscv/rvv/base/vwcvt_x-1.C | 216 + .../g++.target/riscv/rvv/base/vwcvt_x-2.C | 216 + .../g++.target/riscv/rvv/base/vwcvt_x-3.C | 216 + .../g++.target/riscv/rvv/base/vwcvt_x_mu-1.C | 111 + .../g++.target/riscv/rvv/base/vwcvt_x_mu-2.C | 111 + .../g++.target/riscv/rvv/base/vwcvt_x_mu-3.C | 111 + .../g++.target/riscv/rvv/base/vwcvt_x_tu-1.C | 111 + .../g++.target/riscv/rvv/base/vwcvt_x_tu-2.C | 111 + .../g++.target/riscv/rvv/base/vwcvt_x_tu-3.C | 111 + .../g++.target/riscv/rvv/base/vwcvt_x_tum-1.C | 111 + .../g++.target/riscv/rvv/base/vwcvt_x_tum-2.C | 111 + .../g++.target/riscv/rvv/base/vwcvt_x_tum-3.C | 111 + .../g++.target/riscv/rvv/base/vwcvt_x_tumu-1.C | 111 + .../g++.target/riscv/rvv/base/vwcvt_x_tumu-2.C | 111 + .../g++.target/riscv/rvv/base/vwcvt_x_tumu-3.C | 111 + .../g++.target/riscv/rvv/base/vwcvtu_x-1.C | 216 + .../g++.target/riscv/rvv/base/vwcvtu_x-2.C | 216 + .../g++.target/riscv/rvv/base/vwcvtu_x-3.C | 216 + .../g++.target/riscv/rvv/base/vwcvtu_x_mu-1.C | 111 + .../g++.target/riscv/rvv/base/vwcvtu_x_mu-2.C | 111 + .../g++.target/riscv/rvv/base/vwcvtu_x_mu-3.C | 111 + .../g++.target/riscv/rvv/base/vwcvtu_x_tu-1.C | 111 + .../g++.target/riscv/rvv/base/vwcvtu_x_tu-2.C | 111 + .../g++.target/riscv/rvv/base/vwcvtu_x_tu-3.C | 111 + .../g++.target/riscv/rvv/base/vwcvtu_x_tum-1.C | 111 + .../g++.target/riscv/rvv/base/vwcvtu_x_tum-2.C | 111 + .../g++.target/riscv/rvv/base/vwcvtu_x_tum-3.C | 111 + .../g++.target/riscv/rvv/base/vwcvtu_x_tumu-1.C | 111 + .../g++.target/riscv/rvv/base/vwcvtu_x_tumu-2.C | 111 + .../g++.target/riscv/rvv/base/vwcvtu_x_tumu-3.C | 111 + .../g++.target/riscv/rvv/base/vwmacc_vv-1.C | 216 + .../g++.target/riscv/rvv/base/vwmacc_vv-2.C | 216 + .../g++.target/riscv/rvv/base/vwmacc_vv-3.C | 216 + .../g++.target/riscv/rvv/base/vwmacc_vv_mu-1.C | 111 + .../g++.target/riscv/rvv/base/vwmacc_vv_mu-2.C | 111 + .../g++.target/riscv/rvv/base/vwmacc_vv_mu-3.C | 111 + .../g++.target/riscv/rvv/base/vwmacc_vv_tu-1.C | 111 + .../g++.target/riscv/rvv/base/vwmacc_vv_tu-2.C | 111 + .../g++.target/riscv/rvv/base/vwmacc_vv_tu-3.C | 111 + .../g++.target/riscv/rvv/base/vwmacc_vv_tum-1.C | 111 + .../g++.target/riscv/rvv/base/vwmacc_vv_tum-2.C | 111 + .../g++.target/riscv/rvv/base/vwmacc_vv_tum-3.C | 111 + .../g++.target/riscv/rvv/base/vwmacc_vv_tumu-1.C | 111 + .../g++.target/riscv/rvv/base/vwmacc_vv_tumu-2.C | 111 + .../g++.target/riscv/rvv/base/vwmacc_vv_tumu-3.C | 111 + .../g++.target/riscv/rvv/base/vwmacc_vx-1.C | 216 + .../g++.target/riscv/rvv/base/vwmacc_vx-2.C | 216 + .../g++.target/riscv/rvv/base/vwmacc_vx-3.C | 216 + .../g++.target/riscv/rvv/base/vwmacc_vx_mu-1.C | 111 + .../g++.target/riscv/rvv/base/vwmacc_vx_mu-2.C | 111 + .../g++.target/riscv/rvv/base/vwmacc_vx_mu-3.C | 111 + .../g++.target/riscv/rvv/base/vwmacc_vx_tu-1.C | 111 + .../g++.target/riscv/rvv/base/vwmacc_vx_tu-2.C | 111 + .../g++.target/riscv/rvv/base/vwmacc_vx_tu-3.C | 111 + .../g++.target/riscv/rvv/base/vwmacc_vx_tum-1.C | 111 + .../g++.target/riscv/rvv/base/vwmacc_vx_tum-2.C | 111 + .../g++.target/riscv/rvv/base/vwmacc_vx_tum-3.C | 111 + .../g++.target/riscv/rvv/base/vwmacc_vx_tumu-1.C | 111 + .../g++.target/riscv/rvv/base/vwmacc_vx_tumu-2.C | 111 + .../g++.target/riscv/rvv/base/vwmacc_vx_tumu-3.C | 111 + .../g++.target/riscv/rvv/base/vwmaccsu_vv-1.C | 216 + .../g++.target/riscv/rvv/base/vwmaccsu_vv-2.C | 216 + .../g++.target/riscv/rvv/base/vwmaccsu_vv-3.C | 216 + .../g++.target/riscv/rvv/base/vwmaccsu_vv_mu-1.C | 111 + .../g++.target/riscv/rvv/base/vwmaccsu_vv_mu-2.C | 111 + .../g++.target/riscv/rvv/base/vwmaccsu_vv_mu-3.C | 111 + .../g++.target/riscv/rvv/base/vwmaccsu_vv_tu-1.C | 111 + .../g++.target/riscv/rvv/base/vwmaccsu_vv_tu-2.C | 111 + .../g++.target/riscv/rvv/base/vwmaccsu_vv_tu-3.C | 111 + .../g++.target/riscv/rvv/base/vwmaccsu_vv_tum-1.C | 111 + .../g++.target/riscv/rvv/base/vwmaccsu_vv_tum-2.C | 111 + .../g++.target/riscv/rvv/base/vwmaccsu_vv_tum-3.C | 111 + .../g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-1.C | 111 + .../g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-2.C | 111 + .../g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-3.C | 111 + .../g++.target/riscv/rvv/base/vwmaccsu_vx-1.C | 216 + .../g++.target/riscv/rvv/base/vwmaccsu_vx-2.C | 216 + .../g++.target/riscv/rvv/base/vwmaccsu_vx-3.C | 216 + .../g++.target/riscv/rvv/base/vwmaccsu_vx_mu-1.C | 111 + .../g++.target/riscv/rvv/base/vwmaccsu_vx_mu-2.C | 111 + .../g++.target/riscv/rvv/base/vwmaccsu_vx_mu-3.C | 111 + .../g++.target/riscv/rvv/base/vwmaccsu_vx_tu-1.C | 111 + .../g++.target/riscv/rvv/base/vwmaccsu_vx_tu-2.C | 111 + .../g++.target/riscv/rvv/base/vwmaccsu_vx_tu-3.C | 111 + .../g++.target/riscv/rvv/base/vwmaccsu_vx_tum-1.C | 111 + .../g++.target/riscv/rvv/base/vwmaccsu_vx_tum-2.C | 111 + .../g++.target/riscv/rvv/base/vwmaccsu_vx_tum-3.C | 111 + .../g++.target/riscv/rvv/base/vwmaccsu_vx_tumu-1.C | 111 + .../g++.target/riscv/rvv/base/vwmaccsu_vx_tumu-2.C | 111 + .../g++.target/riscv/rvv/base/vwmaccsu_vx_tumu-3.C | 111 + .../g++.target/riscv/rvv/base/vwmaccu_vv-1.C | 216 + .../g++.target/riscv/rvv/base/vwmaccu_vv-2.C | 216 + .../g++.target/riscv/rvv/base/vwmaccu_vv-3.C | 216 + .../g++.target/riscv/rvv/base/vwmaccu_vv_mu-1.C | 111 + .../g++.target/riscv/rvv/base/vwmaccu_vv_mu-2.C | 111 + .../g++.target/riscv/rvv/base/vwmaccu_vv_mu-3.C | 111 + .../g++.target/riscv/rvv/base/vwmaccu_vv_tu-1.C | 111 + .../g++.target/riscv/rvv/base/vwmaccu_vv_tu-2.C | 111 + .../g++.target/riscv/rvv/base/vwmaccu_vv_tu-3.C | 111 + .../g++.target/riscv/rvv/base/vwmaccu_vv_tum-1.C | 111 + .../g++.target/riscv/rvv/base/vwmaccu_vv_tum-2.C | 111 + .../g++.target/riscv/rvv/base/vwmaccu_vv_tum-3.C | 111 + .../g++.target/riscv/rvv/base/vwmaccu_vv_tumu-1.C | 111 + .../g++.target/riscv/rvv/base/vwmaccu_vv_tumu-2.C | 111 + .../g++.target/riscv/rvv/base/vwmaccu_vv_tumu-3.C | 111 + .../g++.target/riscv/rvv/base/vwmaccu_vx-1.C | 216 + .../g++.target/riscv/rvv/base/vwmaccu_vx-2.C | 216 + .../g++.target/riscv/rvv/base/vwmaccu_vx-3.C | 216 + .../g++.target/riscv/rvv/base/vwmaccu_vx_mu-1.C | 111 + .../g++.target/riscv/rvv/base/vwmaccu_vx_mu-2.C | 111 + .../g++.target/riscv/rvv/base/vwmaccu_vx_mu-3.C | 111 + .../g++.target/riscv/rvv/base/vwmaccu_vx_tu-1.C | 111 + .../g++.target/riscv/rvv/base/vwmaccu_vx_tu-2.C | 111 + .../g++.target/riscv/rvv/base/vwmaccu_vx_tu-3.C | 111 + .../g++.target/riscv/rvv/base/vwmaccu_vx_tum-1.C | 111 + .../g++.target/riscv/rvv/base/vwmaccu_vx_tum-2.C | 111 + .../g++.target/riscv/rvv/base/vwmaccu_vx_tum-3.C | 111 + .../g++.target/riscv/rvv/base/vwmaccu_vx_tumu-1.C | 111 + .../g++.target/riscv/rvv/base/vwmaccu_vx_tumu-2.C | 111 + .../g++.target/riscv/rvv/base/vwmaccu_vx_tumu-3.C | 111 + .../g++.target/riscv/rvv/base/vwmaccus_vx-1.C | 216 + .../g++.target/riscv/rvv/base/vwmaccus_vx-2.C | 216 + .../g++.target/riscv/rvv/base/vwmaccus_vx-3.C | 216 + .../g++.target/riscv/rvv/base/vwmaccus_vx_mu-1.C | 111 + .../g++.target/riscv/rvv/base/vwmaccus_vx_mu-2.C | 111 + .../g++.target/riscv/rvv/base/vwmaccus_vx_mu-3.C | 111 + .../g++.target/riscv/rvv/base/vwmaccus_vx_tu-1.C | 111 + .../g++.target/riscv/rvv/base/vwmaccus_vx_tu-2.C | 111 + .../g++.target/riscv/rvv/base/vwmaccus_vx_tu-3.C | 111 + .../g++.target/riscv/rvv/base/vwmaccus_vx_tum-1.C | 111 + .../g++.target/riscv/rvv/base/vwmaccus_vx_tum-2.C | 111 + .../g++.target/riscv/rvv/base/vwmaccus_vx_tum-3.C | 111 + .../g++.target/riscv/rvv/base/vwmaccus_vx_tumu-1.C | 111 + .../g++.target/riscv/rvv/base/vwmaccus_vx_tumu-2.C | 111 + .../g++.target/riscv/rvv/base/vwmaccus_vx_tumu-3.C | 111 + .../g++.target/riscv/rvv/base/vwmul_vv-1.C | 216 + .../g++.target/riscv/rvv/base/vwmul_vv-2.C | 216 + .../g++.target/riscv/rvv/base/vwmul_vv-3.C | 216 + .../g++.target/riscv/rvv/base/vwmul_vv_mu-1.C | 111 + .../g++.target/riscv/rvv/base/vwmul_vv_mu-2.C | 111 + .../g++.target/riscv/rvv/base/vwmul_vv_mu-3.C | 111 + .../g++.target/riscv/rvv/base/vwmul_vv_tu-1.C | 111 + .../g++.target/riscv/rvv/base/vwmul_vv_tu-2.C | 111 + .../g++.target/riscv/rvv/base/vwmul_vv_tu-3.C | 111 + .../g++.target/riscv/rvv/base/vwmul_vv_tum-1.C | 111 + .../g++.target/riscv/rvv/base/vwmul_vv_tum-2.C | 111 + .../g++.target/riscv/rvv/base/vwmul_vv_tum-3.C | 111 + .../g++.target/riscv/rvv/base/vwmul_vv_tumu-1.C | 111 + .../g++.target/riscv/rvv/base/vwmul_vv_tumu-2.C | 111 + .../g++.target/riscv/rvv/base/vwmul_vv_tumu-3.C | 111 + .../g++.target/riscv/rvv/base/vwmul_vx-1.C | 216 + .../g++.target/riscv/rvv/base/vwmul_vx-2.C | 216 + .../g++.target/riscv/rvv/base/vwmul_vx-3.C | 216 + .../g++.target/riscv/rvv/base/vwmul_vx_mu-1.C | 111 + .../g++.target/riscv/rvv/base/vwmul_vx_mu-2.C | 111 + .../g++.target/riscv/rvv/base/vwmul_vx_mu-3.C | 111 + .../g++.target/riscv/rvv/base/vwmul_vx_tu-1.C | 111 + .../g++.target/riscv/rvv/base/vwmul_vx_tu-2.C | 111 + .../g++.target/riscv/rvv/base/vwmul_vx_tu-3.C | 111 + .../g++.target/riscv/rvv/base/vwmul_vx_tum-1.C | 111 + .../g++.target/riscv/rvv/base/vwmul_vx_tum-2.C | 111 + .../g++.target/riscv/rvv/base/vwmul_vx_tum-3.C | 111 + .../g++.target/riscv/rvv/base/vwmul_vx_tumu-1.C | 111 + .../g++.target/riscv/rvv/base/vwmul_vx_tumu-2.C | 111 + .../g++.target/riscv/rvv/base/vwmul_vx_tumu-3.C | 111 + .../g++.target/riscv/rvv/base/vwmulsu_vv-1.C | 216 + .../g++.target/riscv/rvv/base/vwmulsu_vv-2.C | 216 + .../g++.target/riscv/rvv/base/vwmulsu_vv-3.C | 216 + .../g++.target/riscv/rvv/base/vwmulsu_vv_mu-1.C | 111 + .../g++.target/riscv/rvv/base/vwmulsu_vv_mu-2.C | 111 + .../g++.target/riscv/rvv/base/vwmulsu_vv_mu-3.C | 111 + .../g++.target/riscv/rvv/base/vwmulsu_vv_tu-1.C | 111 + .../g++.target/riscv/rvv/base/vwmulsu_vv_tu-2.C | 111 + .../g++.target/riscv/rvv/base/vwmulsu_vv_tu-3.C | 111 + .../g++.target/riscv/rvv/base/vwmulsu_vv_tum-1.C | 111 + .../g++.target/riscv/rvv/base/vwmulsu_vv_tum-2.C | 111 + .../g++.target/riscv/rvv/base/vwmulsu_vv_tum-3.C | 111 + .../g++.target/riscv/rvv/base/vwmulsu_vv_tumu-1.C | 111 + .../g++.target/riscv/rvv/base/vwmulsu_vv_tumu-2.C | 111 + .../g++.target/riscv/rvv/base/vwmulsu_vv_tumu-3.C | 111 + .../g++.target/riscv/rvv/base/vwmulsu_vx-1.C | 216 + .../g++.target/riscv/rvv/base/vwmulsu_vx-2.C | 216 + .../g++.target/riscv/rvv/base/vwmulsu_vx-3.C | 216 + .../g++.target/riscv/rvv/base/vwmulsu_vx_mu-1.C | 111 + .../g++.target/riscv/rvv/base/vwmulsu_vx_mu-2.C | 111 + .../g++.target/riscv/rvv/base/vwmulsu_vx_mu-3.C | 111 + .../g++.target/riscv/rvv/base/vwmulsu_vx_tu-1.C | 111 + .../g++.target/riscv/rvv/base/vwmulsu_vx_tu-2.C | 111 + .../g++.target/riscv/rvv/base/vwmulsu_vx_tu-3.C | 111 + .../g++.target/riscv/rvv/base/vwmulsu_vx_tum-1.C | 111 + .../g++.target/riscv/rvv/base/vwmulsu_vx_tum-2.C | 111 + .../g++.target/riscv/rvv/base/vwmulsu_vx_tum-3.C | 111 + .../g++.target/riscv/rvv/base/vwmulsu_vx_tumu-1.C | 111 + .../g++.target/riscv/rvv/base/vwmulsu_vx_tumu-2.C | 111 + .../g++.target/riscv/rvv/base/vwmulsu_vx_tumu-3.C | 111 + .../g++.target/riscv/rvv/base/vwmulu_vv-1.C | 216 + .../g++.target/riscv/rvv/base/vwmulu_vv-2.C | 216 + .../g++.target/riscv/rvv/base/vwmulu_vv-3.C | 216 + .../g++.target/riscv/rvv/base/vwmulu_vv_mu-1.C | 111 + .../g++.target/riscv/rvv/base/vwmulu_vv_mu-2.C | 111 + .../g++.target/riscv/rvv/base/vwmulu_vv_mu-3.C | 111 + .../g++.target/riscv/rvv/base/vwmulu_vv_tu-1.C | 111 + .../g++.target/riscv/rvv/base/vwmulu_vv_tu-2.C | 111 + .../g++.target/riscv/rvv/base/vwmulu_vv_tu-3.C | 111 + .../g++.target/riscv/rvv/base/vwmulu_vv_tum-1.C | 111 + .../g++.target/riscv/rvv/base/vwmulu_vv_tum-2.C | 111 + .../g++.target/riscv/rvv/base/vwmulu_vv_tum-3.C | 111 + .../g++.target/riscv/rvv/base/vwmulu_vv_tumu-1.C | 111 + .../g++.target/riscv/rvv/base/vwmulu_vv_tumu-2.C | 111 + .../g++.target/riscv/rvv/base/vwmulu_vv_tumu-3.C | 111 + .../g++.target/riscv/rvv/base/vwmulu_vx-1.C | 216 + .../g++.target/riscv/rvv/base/vwmulu_vx-2.C | 216 + .../g++.target/riscv/rvv/base/vwmulu_vx-3.C | 216 + .../g++.target/riscv/rvv/base/vwmulu_vx_mu-1.C | 111 + .../g++.target/riscv/rvv/base/vwmulu_vx_mu-2.C | 111 + .../g++.target/riscv/rvv/base/vwmulu_vx_mu-3.C | 111 + .../g++.target/riscv/rvv/base/vwmulu_vx_tu-1.C | 111 + .../g++.target/riscv/rvv/base/vwmulu_vx_tu-2.C | 111 + .../g++.target/riscv/rvv/base/vwmulu_vx_tu-3.C | 111 + .../g++.target/riscv/rvv/base/vwmulu_vx_tum-1.C | 111 + .../g++.target/riscv/rvv/base/vwmulu_vx_tum-2.C | 111 + .../g++.target/riscv/rvv/base/vwmulu_vx_tum-3.C | 111 + .../g++.target/riscv/rvv/base/vwmulu_vx_tumu-1.C | 111 + .../g++.target/riscv/rvv/base/vwmulu_vx_tumu-2.C | 111 + .../g++.target/riscv/rvv/base/vwmulu_vx_tumu-3.C | 111 + .../g++.target/riscv/rvv/base/vwsub_vv-1.C | 216 + .../g++.target/riscv/rvv/base/vwsub_vv-2.C | 216 + .../g++.target/riscv/rvv/base/vwsub_vv-3.C | 216 + .../g++.target/riscv/rvv/base/vwsub_vv_mu-1.C | 111 + .../g++.target/riscv/rvv/base/vwsub_vv_mu-2.C | 111 + .../g++.target/riscv/rvv/base/vwsub_vv_mu-3.C | 111 + .../g++.target/riscv/rvv/base/vwsub_vv_tu-1.C | 111 + .../g++.target/riscv/rvv/base/vwsub_vv_tu-2.C | 111 + .../g++.target/riscv/rvv/base/vwsub_vv_tu-3.C | 111 + .../g++.target/riscv/rvv/base/vwsub_vv_tum-1.C | 111 + .../g++.target/riscv/rvv/base/vwsub_vv_tum-2.C | 111 + .../g++.target/riscv/rvv/base/vwsub_vv_tum-3.C | 111 + .../g++.target/riscv/rvv/base/vwsub_vv_tumu-1.C | 111 + .../g++.target/riscv/rvv/base/vwsub_vv_tumu-2.C | 111 + .../g++.target/riscv/rvv/base/vwsub_vv_tumu-3.C | 111 + .../g++.target/riscv/rvv/base/vwsub_vx-1.C | 216 + .../g++.target/riscv/rvv/base/vwsub_vx-2.C | 216 + .../g++.target/riscv/rvv/base/vwsub_vx-3.C | 216 + .../g++.target/riscv/rvv/base/vwsub_vx_mu-1.C | 111 + .../g++.target/riscv/rvv/base/vwsub_vx_mu-2.C | 111 + .../g++.target/riscv/rvv/base/vwsub_vx_mu-3.C | 111 + .../g++.target/riscv/rvv/base/vwsub_vx_tu-1.C | 111 + .../g++.target/riscv/rvv/base/vwsub_vx_tu-2.C | 111 + .../g++.target/riscv/rvv/base/vwsub_vx_tu-3.C | 111 + .../g++.target/riscv/rvv/base/vwsub_vx_tum-1.C | 111 + .../g++.target/riscv/rvv/base/vwsub_vx_tum-2.C | 111 + .../g++.target/riscv/rvv/base/vwsub_vx_tum-3.C | 111 + .../g++.target/riscv/rvv/base/vwsub_vx_tumu-1.C | 111 + .../g++.target/riscv/rvv/base/vwsub_vx_tumu-2.C | 111 + .../g++.target/riscv/rvv/base/vwsub_vx_tumu-3.C | 111 + .../g++.target/riscv/rvv/base/vwsub_wv-1.C | 216 + .../g++.target/riscv/rvv/base/vwsub_wv-2.C | 216 + .../g++.target/riscv/rvv/base/vwsub_wv-3.C | 216 + .../g++.target/riscv/rvv/base/vwsub_wv_mu-1.C | 111 + .../g++.target/riscv/rvv/base/vwsub_wv_mu-2.C | 111 + .../g++.target/riscv/rvv/base/vwsub_wv_mu-3.C | 111 + .../g++.target/riscv/rvv/base/vwsub_wv_tu-1.C | 111 + .../g++.target/riscv/rvv/base/vwsub_wv_tu-2.C | 111 + .../g++.target/riscv/rvv/base/vwsub_wv_tu-3.C | 111 + .../g++.target/riscv/rvv/base/vwsub_wv_tum-1.C | 111 + .../g++.target/riscv/rvv/base/vwsub_wv_tum-2.C | 111 + .../g++.target/riscv/rvv/base/vwsub_wv_tum-3.C | 111 + .../g++.target/riscv/rvv/base/vwsub_wv_tumu-1.C | 111 + .../g++.target/riscv/rvv/base/vwsub_wv_tumu-2.C | 111 + .../g++.target/riscv/rvv/base/vwsub_wv_tumu-3.C | 111 + .../g++.target/riscv/rvv/base/vwsub_wx-1.C | 216 + .../g++.target/riscv/rvv/base/vwsub_wx-2.C | 216 + .../g++.target/riscv/rvv/base/vwsub_wx-3.C | 216 + .../g++.target/riscv/rvv/base/vwsub_wx_mu-1.C | 111 + .../g++.target/riscv/rvv/base/vwsub_wx_mu-2.C | 111 + .../g++.target/riscv/rvv/base/vwsub_wx_mu-3.C | 111 + .../g++.target/riscv/rvv/base/vwsub_wx_tu-1.C | 111 + .../g++.target/riscv/rvv/base/vwsub_wx_tu-2.C | 111 + .../g++.target/riscv/rvv/base/vwsub_wx_tu-3.C | 111 + .../g++.target/riscv/rvv/base/vwsub_wx_tum-1.C | 111 + .../g++.target/riscv/rvv/base/vwsub_wx_tum-2.C | 111 + .../g++.target/riscv/rvv/base/vwsub_wx_tum-3.C | 111 + .../g++.target/riscv/rvv/base/vwsub_wx_tumu-1.C | 111 + .../g++.target/riscv/rvv/base/vwsub_wx_tumu-2.C | 111 + .../g++.target/riscv/rvv/base/vwsub_wx_tumu-3.C | 111 + .../g++.target/riscv/rvv/base/vwsubu_vv-1.C | 216 + .../g++.target/riscv/rvv/base/vwsubu_vv-2.C | 216 + .../g++.target/riscv/rvv/base/vwsubu_vv-3.C | 216 + .../g++.target/riscv/rvv/base/vwsubu_vv_mu-1.C | 111 + .../g++.target/riscv/rvv/base/vwsubu_vv_mu-2.C | 111 + .../g++.target/riscv/rvv/base/vwsubu_vv_mu-3.C | 111 + .../g++.target/riscv/rvv/base/vwsubu_vv_tu-1.C | 111 + .../g++.target/riscv/rvv/base/vwsubu_vv_tu-2.C | 111 + .../g++.target/riscv/rvv/base/vwsubu_vv_tu-3.C | 111 + .../g++.target/riscv/rvv/base/vwsubu_vv_tum-1.C | 111 + .../g++.target/riscv/rvv/base/vwsubu_vv_tum-2.C | 111 + .../g++.target/riscv/rvv/base/vwsubu_vv_tum-3.C | 111 + .../g++.target/riscv/rvv/base/vwsubu_vv_tumu-1.C | 111 + .../g++.target/riscv/rvv/base/vwsubu_vv_tumu-2.C | 111 + .../g++.target/riscv/rvv/base/vwsubu_vv_tumu-3.C | 111 + .../g++.target/riscv/rvv/base/vwsubu_vx-1.C | 216 + .../g++.target/riscv/rvv/base/vwsubu_vx-2.C | 216 + .../g++.target/riscv/rvv/base/vwsubu_vx-3.C | 216 + .../g++.target/riscv/rvv/base/vwsubu_vx_mu-1.C | 111 + .../g++.target/riscv/rvv/base/vwsubu_vx_mu-2.C | 111 + .../g++.target/riscv/rvv/base/vwsubu_vx_mu-3.C | 111 + .../g++.target/riscv/rvv/base/vwsubu_vx_tu-1.C | 111 + .../g++.target/riscv/rvv/base/vwsubu_vx_tu-2.C | 111 + .../g++.target/riscv/rvv/base/vwsubu_vx_tu-3.C | 111 + .../g++.target/riscv/rvv/base/vwsubu_vx_tum-1.C | 111 + .../g++.target/riscv/rvv/base/vwsubu_vx_tum-2.C | 111 + .../g++.target/riscv/rvv/base/vwsubu_vx_tum-3.C | 111 + .../g++.target/riscv/rvv/base/vwsubu_vx_tumu-1.C | 111 + .../g++.target/riscv/rvv/base/vwsubu_vx_tumu-2.C | 111 + .../g++.target/riscv/rvv/base/vwsubu_vx_tumu-3.C | 111 + .../g++.target/riscv/rvv/base/vwsubu_wv-1.C | 216 + .../g++.target/riscv/rvv/base/vwsubu_wv-2.C | 216 + .../g++.target/riscv/rvv/base/vwsubu_wv-3.C | 216 + .../g++.target/riscv/rvv/base/vwsubu_wv_mu-1.C | 111 + .../g++.target/riscv/rvv/base/vwsubu_wv_mu-2.C | 111 + .../g++.target/riscv/rvv/base/vwsubu_wv_mu-3.C | 111 + .../g++.target/riscv/rvv/base/vwsubu_wv_tu-1.C | 111 + .../g++.target/riscv/rvv/base/vwsubu_wv_tu-2.C | 111 + .../g++.target/riscv/rvv/base/vwsubu_wv_tu-3.C | 111 + .../g++.target/riscv/rvv/base/vwsubu_wv_tum-1.C | 111 + .../g++.target/riscv/rvv/base/vwsubu_wv_tum-2.C | 111 + .../g++.target/riscv/rvv/base/vwsubu_wv_tum-3.C | 111 + .../g++.target/riscv/rvv/base/vwsubu_wv_tumu-1.C | 111 + .../g++.target/riscv/rvv/base/vwsubu_wv_tumu-2.C | 111 + .../g++.target/riscv/rvv/base/vwsubu_wv_tumu-3.C | 111 + .../g++.target/riscv/rvv/base/vwsubu_wx-1.C | 216 + .../g++.target/riscv/rvv/base/vwsubu_wx-2.C | 216 + .../g++.target/riscv/rvv/base/vwsubu_wx-3.C | 216 + .../g++.target/riscv/rvv/base/vwsubu_wx_mu-1.C | 111 + .../g++.target/riscv/rvv/base/vwsubu_wx_mu-2.C | 111 + .../g++.target/riscv/rvv/base/vwsubu_wx_mu-3.C | 111 + .../g++.target/riscv/rvv/base/vwsubu_wx_tu-1.C | 111 + .../g++.target/riscv/rvv/base/vwsubu_wx_tu-2.C | 111 + .../g++.target/riscv/rvv/base/vwsubu_wx_tu-3.C | 111 + .../g++.target/riscv/rvv/base/vwsubu_wx_tum-1.C | 111 + .../g++.target/riscv/rvv/base/vwsubu_wx_tum-2.C | 111 + .../g++.target/riscv/rvv/base/vwsubu_wx_tum-3.C | 111 + .../g++.target/riscv/rvv/base/vwsubu_wx_tumu-1.C | 111 + .../g++.target/riscv/rvv/base/vwsubu_wx_tumu-2.C | 111 + .../g++.target/riscv/rvv/base/vwsubu_wx_tumu-3.C | 111 + .../g++.target/riscv/rvv/base/vxor_vv-1.C | 578 + .../g++.target/riscv/rvv/base/vxor_vv-2.C | 578 + .../g++.target/riscv/rvv/base/vxor_vv-3.C | 578 + .../g++.target/riscv/rvv/base/vxor_vv_mu-1.C | 292 + .../g++.target/riscv/rvv/base/vxor_vv_mu-2.C | 292 + .../g++.target/riscv/rvv/base/vxor_vv_mu-3.C | 292 + .../g++.target/riscv/rvv/base/vxor_vv_tu-1.C | 292 + .../g++.target/riscv/rvv/base/vxor_vv_tu-2.C | 292 + .../g++.target/riscv/rvv/base/vxor_vv_tu-3.C | 292 + .../g++.target/riscv/rvv/base/vxor_vv_tum-1.C | 292 + .../g++.target/riscv/rvv/base/vxor_vv_tum-2.C | 292 + .../g++.target/riscv/rvv/base/vxor_vv_tum-3.C | 292 + .../g++.target/riscv/rvv/base/vxor_vv_tumu-1.C | 292 + .../g++.target/riscv/rvv/base/vxor_vv_tumu-2.C | 292 + .../g++.target/riscv/rvv/base/vxor_vv_tumu-3.C | 292 + .../g++.target/riscv/rvv/base/vxor_vx_mu_rv32-1.C | 289 + .../g++.target/riscv/rvv/base/vxor_vx_mu_rv32-2.C | 289 + .../g++.target/riscv/rvv/base/vxor_vx_mu_rv32-3.C | 289 + .../g++.target/riscv/rvv/base/vxor_vx_mu_rv64-1.C | 292 + .../g++.target/riscv/rvv/base/vxor_vx_mu_rv64-2.C | 292 + .../g++.target/riscv/rvv/base/vxor_vx_mu_rv64-3.C | 292 + .../g++.target/riscv/rvv/base/vxor_vx_rv32-1.C | 572 + .../g++.target/riscv/rvv/base/vxor_vx_rv32-2.C | 572 + .../g++.target/riscv/rvv/base/vxor_vx_rv32-3.C | 572 + .../g++.target/riscv/rvv/base/vxor_vx_rv64-1.C | 578 + .../g++.target/riscv/rvv/base/vxor_vx_rv64-2.C | 578 + .../g++.target/riscv/rvv/base/vxor_vx_rv64-3.C | 578 + .../g++.target/riscv/rvv/base/vxor_vx_tu_rv32-1.C | 289 + .../g++.target/riscv/rvv/base/vxor_vx_tu_rv32-2.C | 289 + .../g++.target/riscv/rvv/base/vxor_vx_tu_rv32-3.C | 289 + .../g++.target/riscv/rvv/base/vxor_vx_tu_rv64-1.C | 292 + .../g++.target/riscv/rvv/base/vxor_vx_tu_rv64-2.C | 292 + .../g++.target/riscv/rvv/base/vxor_vx_tu_rv64-3.C | 292 + .../g++.target/riscv/rvv/base/vxor_vx_tum_rv32-1.C | 289 + .../g++.target/riscv/rvv/base/vxor_vx_tum_rv32-2.C | 289 + .../g++.target/riscv/rvv/base/vxor_vx_tum_rv32-3.C | 289 + .../g++.target/riscv/rvv/base/vxor_vx_tum_rv64-1.C | 292 + .../g++.target/riscv/rvv/base/vxor_vx_tum_rv64-2.C | 292 + .../g++.target/riscv/rvv/base/vxor_vx_tum_rv64-3.C | 292 + .../riscv/rvv/base/vxor_vx_tumu_rv32-1.C | 289 + .../riscv/rvv/base/vxor_vx_tumu_rv32-2.C | 289 + .../riscv/rvv/base/vxor_vx_tumu_rv32-3.C | 289 + .../riscv/rvv/base/vxor_vx_tumu_rv64-1.C | 292 + .../riscv/rvv/base/vxor_vx_tumu_rv64-2.C | 292 + .../riscv/rvv/base/vxor_vx_tumu_rv64-3.C | 292 + .../g++.target/riscv/rvv/base/vzext_vf2-1.C | 216 + .../g++.target/riscv/rvv/base/vzext_vf2-2.C | 216 + .../g++.target/riscv/rvv/base/vzext_vf2-3.C | 216 + .../g++.target/riscv/rvv/base/vzext_vf2_mu-1.C | 111 + .../g++.target/riscv/rvv/base/vzext_vf2_mu-2.C | 111 + .../g++.target/riscv/rvv/base/vzext_vf2_mu-3.C | 111 + .../g++.target/riscv/rvv/base/vzext_vf2_tu-1.C | 111 + .../g++.target/riscv/rvv/base/vzext_vf2_tu-2.C | 111 + .../g++.target/riscv/rvv/base/vzext_vf2_tu-3.C | 111 + .../g++.target/riscv/rvv/base/vzext_vf2_tum-1.C | 111 + .../g++.target/riscv/rvv/base/vzext_vf2_tum-2.C | 111 + .../g++.target/riscv/rvv/base/vzext_vf2_tum-3.C | 111 + .../g++.target/riscv/rvv/base/vzext_vf2_tumu-1.C | 111 + .../g++.target/riscv/rvv/base/vzext_vf2_tumu-2.C | 111 + .../g++.target/riscv/rvv/base/vzext_vf2_tumu-3.C | 111 + .../g++.target/riscv/rvv/base/vzext_vf4-1.C | 132 + .../g++.target/riscv/rvv/base/vzext_vf4-2.C | 132 + .../g++.target/riscv/rvv/base/vzext_vf4-3.C | 132 + .../g++.target/riscv/rvv/base/vzext_vf4_mu-1.C | 69 + .../g++.target/riscv/rvv/base/vzext_vf4_mu-2.C | 69 + .../g++.target/riscv/rvv/base/vzext_vf4_mu-3.C | 69 + .../g++.target/riscv/rvv/base/vzext_vf4_tu-1.C | 69 + .../g++.target/riscv/rvv/base/vzext_vf4_tu-2.C | 69 + .../g++.target/riscv/rvv/base/vzext_vf4_tu-3.C | 69 + .../g++.target/riscv/rvv/base/vzext_vf4_tum-1.C | 69 + .../g++.target/riscv/rvv/base/vzext_vf4_tum-2.C | 69 + .../g++.target/riscv/rvv/base/vzext_vf4_tum-3.C | 69 + .../g++.target/riscv/rvv/base/vzext_vf4_tumu-1.C | 69 + .../g++.target/riscv/rvv/base/vzext_vf4_tumu-2.C | 69 + .../g++.target/riscv/rvv/base/vzext_vf4_tumu-3.C | 69 + .../g++.target/riscv/rvv/base/vzext_vf8-1.C | 62 + .../g++.target/riscv/rvv/base/vzext_vf8-2.C | 62 + .../g++.target/riscv/rvv/base/vzext_vf8-3.C | 62 + .../g++.target/riscv/rvv/base/vzext_vf8_mu-1.C | 34 + .../g++.target/riscv/rvv/base/vzext_vf8_mu-2.C | 34 + .../g++.target/riscv/rvv/base/vzext_vf8_mu-3.C | 34 + .../g++.target/riscv/rvv/base/vzext_vf8_tu-1.C | 34 + .../g++.target/riscv/rvv/base/vzext_vf8_tu-2.C | 34 + .../g++.target/riscv/rvv/base/vzext_vf8_tu-3.C | 34 + .../g++.target/riscv/rvv/base/vzext_vf8_tum-1.C | 34 + .../g++.target/riscv/rvv/base/vzext_vf8_tum-2.C | 34 + .../g++.target/riscv/rvv/base/vzext_vf8_tum-3.C | 34 + .../g++.target/riscv/rvv/base/vzext_vf8_tumu-1.C | 34 + .../g++.target/riscv/rvv/base/vzext_vf8_tumu-2.C | 34 + .../g++.target/riscv/rvv/base/vzext_vf8_tumu-3.C | 34 + .../gcc.c-torture/compile/dce-inline-asm-1.c | 15 + .../gcc.c-torture/compile/dce-inline-asm-2.c | 16 + gcc/testsuite/gcc.c-torture/compile/pr106433.c | 24 + gcc/testsuite/gcc.c-torture/compile/pr108638.c | 12 + gcc/testsuite/gcc.c-torture/compile/pr108639.c | 11 + gcc/testsuite/gcc.c-torture/compile/pr108688-1.c | 14 + gcc/testsuite/gcc.c-torture/compile/pr108783.c | 42 + gcc/testsuite/gcc.c-torture/execute/pr47237.c | 2 +- gcc/testsuite/gcc.dg/Warray-bounds-52.c | 2 +- .../gcc.dg/Wbuiltin-declaration-mismatch-7.c | 2 +- gcc/testsuite/gcc.dg/Wstringop-overflow-62.c | 2 +- .../gcc.dg/analyzer/allocation-size-multiline-3.c | 44 + gcc/testsuite/gcc.dg/analyzer/call-summaries-2.c | 1 + .../gcc.dg/analyzer/coreutils-cksum-pr108664.c | 80 + .../gcc.dg/analyzer/coreutils-sum-pr108666.c | 98 + .../analyzer/deref-before-check-macro-pr108745.c | 54 + .../gcc.dg/analyzer/deref-before-check-macro.c | 25 + .../deref-before-check-qemu-qtest_rsp_args.c | 73 + gcc/testsuite/gcc.dg/analyzer/fd-pr108633.c | 79 + gcc/testsuite/gcc.dg/analyzer/fread-pr108661.c | 40 + .../gcc.dg/analyzer/imprecise-floating-point-1.c | 2 + .../gcc.dg/analyzer/infinite-recursion-alloca.c | 2 + gcc/testsuite/gcc.dg/analyzer/malloc-callbacks.c | 2 + .../gcc.dg/analyzer/null-deref-pr108806-qemu.c | 105 + gcc/testsuite/gcc.dg/analyzer/out-of-bounds-5.c | 9 +- gcc/testsuite/gcc.dg/analyzer/pr103217.c | 2 + gcc/testsuite/gcc.dg/analyzer/putenv-1.c | 1 + gcc/testsuite/gcc.dg/analyzer/read-pr108661.c | 33 + gcc/testsuite/gcc.dg/analyzer/switch.c | 76 + gcc/testsuite/gcc.dg/analyzer/test-alloca.h | 3 + .../gcc.dg/analyzer/torture/uninit-pr108725.c | 19 + .../gcc.dg/analyzer/torture/uninit-pr108733.c | 65 + gcc/testsuite/gcc.dg/analyzer/uninit-7.c | 127 + gcc/testsuite/gcc.dg/analyzer/uninit-pr108704.c | 29 + .../gcc.dg/analyzer/uninit-pr108806-qemu.c | 108 + .../gcc.dg/analyzer/write-to-string-literal-5.c | 1 + gcc/testsuite/gcc.dg/asan/pr108777-1.c | 28 + gcc/testsuite/gcc.dg/asan/pr108777-2.c | 24 + gcc/testsuite/gcc.dg/asan/pr108777-3.c | 28 + gcc/testsuite/gcc.dg/asan/pr108777-4.c | 24 + gcc/testsuite/gcc.dg/asan/pr108777-5.c | 28 + gcc/testsuite/gcc.dg/asan/pr108777-6.c | 24 + gcc/testsuite/gcc.dg/attr-vector_size.c | 4 +- gcc/testsuite/gcc.dg/builtin-apply3.c | 1 + gcc/testsuite/gcc.dg/builtin-apply4.c | 1 + .../gcc.dg/builtin-dynamic-object-size-0.c | 14 +- gcc/testsuite/gcc.dg/builtin-object-size-1.c | 297 +- gcc/testsuite/gcc.dg/builtin-object-size-12.c | 12 +- gcc/testsuite/gcc.dg/builtin-object-size-13.c | 15 +- gcc/testsuite/gcc.dg/builtin-object-size-15.c | 11 +- gcc/testsuite/gcc.dg/builtin-object-size-2.c | 305 +- gcc/testsuite/gcc.dg/builtin-object-size-3.c | 275 +- gcc/testsuite/gcc.dg/builtin-object-size-4.c | 285 +- gcc/testsuite/gcc.dg/builtin-object-size-6.c | 260 +- gcc/testsuite/gcc.dg/builtin-object-size-7.c | 54 +- gcc/testsuite/gcc.dg/builtin-object-size-8.c | 15 +- gcc/testsuite/gcc.dg/builtin-object-size-common.h | 32 + gcc/testsuite/gcc.dg/c2x-constexpr-1.c | 15 + gcc/testsuite/gcc.dg/c2x-constexpr-3.c | 18 +- gcc/testsuite/gcc.dg/c2x-constexpr-8.c | 2 + gcc/testsuite/gcc.dg/c2x-constexpr-9.c | 10 +- gcc/testsuite/gcc.dg/c2x-nullptr-1.c | 33 +- gcc/testsuite/gcc.dg/c2x-nullptr-3.c | 34 +- gcc/testsuite/gcc.dg/completion-3.c | 1 + gcc/testsuite/gcc.dg/dfp/c2x-constexpr-dfp-1.c | 10 + gcc/testsuite/gcc.dg/dfp/c2x-constexpr-dfp-2.c | 8 +- gcc/testsuite/gcc.dg/gomp/pr108435.c | 18 + gcc/testsuite/gcc.dg/ipa/pr108384.c | 25 + gcc/testsuite/gcc.dg/ipa/pr108679.c | 25 + gcc/testsuite/gcc.dg/overflow-warn-9.c | 2 +- gcc/testsuite/gcc.dg/pr100590.c | 2 +- gcc/testsuite/gcc.dg/pr101836.c | 10 +- gcc/testsuite/gcc.dg/pr106923.c | 23 + gcc/testsuite/gcc.dg/pr107300.c | 19 + gcc/testsuite/gcc.dg/pr107570.c | 25 + gcc/testsuite/gcc.dg/pr108356.c | 23 + gcc/testsuite/gcc.dg/pr108359.c | 52 + gcc/testsuite/gcc.dg/pr108385.c | 39 + gcc/testsuite/gcc.dg/pr108463.c | 13 + gcc/testsuite/gcc.dg/pr108573.c | 18 + gcc/testsuite/gcc.dg/pr108625.c | 14 + gcc/testsuite/gcc.dg/pr108655.c | 15 + gcc/testsuite/gcc.dg/pr108657.c | 31 + gcc/testsuite/gcc.dg/pr108688.c | 16 + gcc/testsuite/gcc.dg/pr108691.c | 9 + gcc/testsuite/gcc.dg/pr108692.c | 31 + gcc/testsuite/gcc.dg/pr108787.c | 27 + gcc/testsuite/gcc.dg/pr108805.c | 20 + gcc/testsuite/gcc.dg/pr65658.c | 12 +- gcc/testsuite/gcc.dg/strict-flex-array-3.c | 10 +- gcc/testsuite/gcc.dg/torture/pr100398.c | 2 +- gcc/testsuite/gcc.dg/torture/pr108737.c | 19 + gcc/testsuite/gcc.dg/torture/pr108782.c | 21 + gcc/testsuite/gcc.dg/torture/pr108791.c | 9 + .../gcc.dg/torture/stackalign/builtin-apply-3.c | 1 + .../gcc.dg/torture/stackalign/builtin-apply-4.c | 1 + gcc/testsuite/gcc.dg/tree-ssa/bool-minus-1.c | 11 + gcc/testsuite/gcc.dg/tree-ssa/bool-minus-2.c | 33 + gcc/testsuite/gcc.dg/tree-ssa/pr108354-1.c | 26 + gcc/testsuite/gcc.dg/tree-ssa/pr108684-1.c | 18 + gcc/testsuite/gcc.dg/tree-ssa/ssa-lim-24.c | 25 + gcc/testsuite/gcc.dg/vect/pr108316.c | 11 + gcc/testsuite/gcc.dg/vect/pr108608.c | 24 + gcc/testsuite/gcc.target/aarch64/cpunative/info_19 | 9 + gcc/testsuite/gcc.target/aarch64/cpunative/info_20 | 9 + gcc/testsuite/gcc.target/aarch64/cpunative/info_21 | 9 + gcc/testsuite/gcc.target/aarch64/cpunative/info_22 | 9 + .../gcc.target/aarch64/cpunative/native_cpu_19.c | 14 + .../gcc.target/aarch64/cpunative/native_cpu_20.c | 15 + .../gcc.target/aarch64/cpunative/native_cpu_21.c | 13 + .../gcc.target/aarch64/cpunative/native_cpu_22.c | 13 + gcc/testsuite/gcc.target/aarch64/options_set_10.c | 11 - gcc/testsuite/gcc.target/aarch64/pr104921-1.c | 12 + gcc/testsuite/gcc.target/aarch64/pr104921-2.c | 6 + gcc/testsuite/gcc.target/aarch64/pr104921.x | 9 + gcc/testsuite/gcc.target/aarch64/pr108508.c | 28 + gcc/testsuite/gcc.target/aarch64/pr108589.c | 15 + gcc/testsuite/gcc.target/aarch64/pr108601.c | 11 + gcc/testsuite/gcc.target/aarch64/pr108681.c | 15 + gcc/testsuite/gcc.target/aarch64/sve/fabd_1.c | 2 +- gcc/testsuite/gcc.target/aarch64/sve/fmul_1.c | 12 +- gcc/testsuite/gcc.target/aarch64/sve/fp_arith_1.c | 12 +- gcc/testsuite/gcc.target/aarch64/sve/fsubr_1.c | 2 +- gcc/testsuite/gcc.target/aarch64/sve/pr108608-1.c | 9 + gcc/testsuite/gcc.target/arc/milli-1.c | 2 +- gcc/testsuite/gcc.target/arm/mve/mve_vpt.c | 24 + gcc/testsuite/gcc.target/arm/mve/pr108443-run.c | 29 + gcc/testsuite/gcc.target/arm/mve/pr108443.c | 14 + gcc/testsuite/gcc.target/bpf/ldxdw.c | 12 + gcc/testsuite/gcc.target/gcn/cond_shift_3.c | 37 + .../{aarch64/sve => gcn}/cond_shift_3_run.c | 2 +- gcc/testsuite/gcc.target/gcn/cond_shift_4.c | 38 + .../{aarch64/sve => gcn}/cond_shift_4_run.c | 2 +- gcc/testsuite/gcc.target/gcn/cond_shift_8.c | 35 + .../{aarch64/sve => gcn}/cond_shift_8_run.c | 2 +- gcc/testsuite/gcc.target/gcn/cond_shift_9.c | 36 + .../{aarch64/sve => gcn}/cond_shift_9_run.c | 2 +- .../gcc.target/i386/avx512fp16-reduce-op-2.c | 3 +- gcc/testsuite/gcc.target/i386/pr103541.c | 14 + gcc/testsuite/gcc.target/i386/pr108516-1.c | 19 + gcc/testsuite/gcc.target/i386/pr108516-2.c | 19 + gcc/testsuite/gcc.target/i386/pr108724.c | 15 + gcc/testsuite/gcc.target/i386/pr108774.c | 11 + .../gcc.target/i386/{pr91188-1b.c => pr108831-1.c} | 36 +- .../gcc.target/i386/{pr91188-1b.c => pr108831-2.c} | 46 +- gcc/testsuite/gcc.target/i386/pr85593.c | 2 +- gcc/testsuite/gcc.target/i386/pr90007.c | 2 +- gcc/testsuite/gcc.target/i386/pr92841-2.c | 2 +- gcc/testsuite/gcc.target/i386/pr95464.c | 2 +- gcc/testsuite/gcc.target/i386/pr98063.c | 2 +- gcc/testsuite/gcc.target/i386/pr99464.c | 3 +- gcc/testsuite/gcc.target/i386/pr99530-1.c | 2 +- gcc/testsuite/gcc.target/i386/pr99530-2.c | 2 +- gcc/testsuite/gcc.target/i386/pr99530-3.c | 2 +- gcc/testsuite/gcc.target/i386/pr99530-4.c | 2 +- gcc/testsuite/gcc.target/i386/pr99530-5.c | 2 +- gcc/testsuite/gcc.target/i386/pr99530-6.c | 2 +- gcc/testsuite/gcc.target/i386/pr99531.c | 4 +- .../gcc.target/powerpc/p9-vec-length-epil-1.c | 2 +- .../gcc.target/powerpc/p9-vec-length-epil-2.c | 2 +- .../gcc.target/powerpc/p9-vec-length-epil-3.c | 2 +- .../gcc.target/powerpc/p9-vec-length-epil-4.c | 2 +- .../gcc.target/powerpc/p9-vec-length-epil-5.c | 2 +- .../gcc.target/powerpc/p9-vec-length-epil-6.c | 2 +- .../gcc.target/powerpc/p9-vec-length-epil-8.c | 2 +- .../gcc.target/powerpc/p9-vec-length-full-1.c | 2 +- .../gcc.target/powerpc/p9-vec-length-full-2.c | 2 +- .../gcc.target/powerpc/p9-vec-length-full-3.c | 2 +- .../gcc.target/powerpc/p9-vec-length-full-4.c | 2 +- .../gcc.target/powerpc/p9-vec-length-full-5.c | 2 +- .../gcc.target/powerpc/p9-vec-length-full-6.c | 2 +- .../gcc.target/powerpc/p9-vec-length-full-8.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr103109-1.c | 4 +- gcc/testsuite/gcc.target/powerpc/pr108787.c | 6 + gcc/testsuite/gcc.target/powerpc/pr96373.c | 31 + .../riscv/rvv/base/binop_vv_constraint-1.c | 132 + .../riscv/rvv/base/binop_vv_constraint-2.c | 15 + .../riscv/rvv/base/binop_vv_constraint-3.c | 27 + .../riscv/rvv/base/binop_vv_constraint-4.c | 27 + .../riscv/rvv/base/binop_vv_constraint-5.c | 29 + .../riscv/rvv/base/binop_vv_constraint-6.c | 27 + .../riscv/rvv/base/binop_vv_constraint-7.c | 29 + .../riscv/rvv/base/binop_vx_constraint-1.c | 132 + .../riscv/rvv/base/binop_vx_constraint-10.c | 132 + .../riscv/rvv/base/binop_vx_constraint-100.c | 16 + .../riscv/rvv/base/binop_vx_constraint-101.c | 16 + .../riscv/rvv/base/binop_vx_constraint-102.c | 18 + .../riscv/rvv/base/binop_vx_constraint-103.c | 123 + .../riscv/rvv/base/binop_vx_constraint-104.c | 72 + .../riscv/rvv/base/binop_vx_constraint-105.c | 16 + .../riscv/rvv/base/binop_vx_constraint-106.c | 16 + .../riscv/rvv/base/binop_vx_constraint-107.c | 16 + .../riscv/rvv/base/binop_vx_constraint-108.c | 18 + .../riscv/rvv/base/binop_vx_constraint-109.c | 123 + .../riscv/rvv/base/binop_vx_constraint-11.c | 132 + .../riscv/rvv/base/binop_vx_constraint-110.c | 72 + .../riscv/rvv/base/binop_vx_constraint-111.c | 16 + .../riscv/rvv/base/binop_vx_constraint-112.c | 16 + .../riscv/rvv/base/binop_vx_constraint-113.c | 16 + .../riscv/rvv/base/binop_vx_constraint-114.c | 18 + .../riscv/rvv/base/binop_vx_constraint-115.c | 72 + .../riscv/rvv/base/binop_vx_constraint-116.c | 16 + .../riscv/rvv/base/binop_vx_constraint-117.c | 16 + .../riscv/rvv/base/binop_vx_constraint-118.c | 16 + .../riscv/rvv/base/binop_vx_constraint-119.c | 18 + .../riscv/rvv/base/binop_vx_constraint-12.c | 160 + .../riscv/rvv/base/binop_vx_constraint-120.c | 16 + .../riscv/rvv/base/binop_vx_constraint-121.c | 55 + .../riscv/rvv/base/binop_vx_constraint-122.c | 21 + .../riscv/rvv/base/binop_vx_constraint-123.c | 15 + .../riscv/rvv/base/binop_vx_constraint-124.c | 27 + .../riscv/rvv/base/binop_vx_constraint-125.c | 27 + .../riscv/rvv/base/binop_vx_constraint-126.c | 29 + .../riscv/rvv/base/binop_vx_constraint-127.c | 27 + .../riscv/rvv/base/binop_vx_constraint-128.c | 29 + .../riscv/rvv/base/binop_vx_constraint-129.c | 69 + .../riscv/rvv/base/binop_vx_constraint-13.c | 132 + .../riscv/rvv/base/binop_vx_constraint-130.c | 69 + .../riscv/rvv/base/binop_vx_constraint-131.c | 69 + .../riscv/rvv/base/binop_vx_constraint-132.c | 59 + .../riscv/rvv/base/binop_vx_constraint-133.c | 69 + .../riscv/rvv/base/binop_vx_constraint-134.c | 69 + .../riscv/rvv/base/binop_vx_constraint-135.c | 69 + .../riscv/rvv/base/binop_vx_constraint-136.c | 59 + .../riscv/rvv/base/binop_vx_constraint-137.c | 123 + .../riscv/rvv/base/binop_vx_constraint-138.c | 123 + .../riscv/rvv/base/binop_vx_constraint-139.c | 72 + .../riscv/rvv/base/binop_vx_constraint-14.c | 132 + .../riscv/rvv/base/binop_vx_constraint-140.c | 72 + .../riscv/rvv/base/binop_vx_constraint-141.c | 16 + .../riscv/rvv/base/binop_vx_constraint-142.c | 16 + .../riscv/rvv/base/binop_vx_constraint-143.c | 16 + .../riscv/rvv/base/binop_vx_constraint-144.c | 16 + .../riscv/rvv/base/binop_vx_constraint-145.c | 16 + .../riscv/rvv/base/binop_vx_constraint-146.c | 16 + .../riscv/rvv/base/binop_vx_constraint-147.c | 19 + .../riscv/rvv/base/binop_vx_constraint-148.c | 20 + .../riscv/rvv/base/binop_vx_constraint-149.c | 19 + .../riscv/rvv/base/binop_vx_constraint-15.c | 132 + .../riscv/rvv/base/binop_vx_constraint-150.c | 21 + .../riscv/rvv/base/binop_vx_constraint-151.c | 20 + .../riscv/rvv/base/binop_vx_constraint-152.c | 20 + .../riscv/rvv/base/binop_vx_constraint-153.c | 75 + .../riscv/rvv/base/binop_vx_constraint-154.c | 69 + .../riscv/rvv/base/binop_vx_constraint-155.c | 69 + .../riscv/rvv/base/binop_vx_constraint-156.c | 65 + .../riscv/rvv/base/binop_vx_constraint-157.c | 133 + .../riscv/rvv/base/binop_vx_constraint-158.c | 69 + .../riscv/rvv/base/binop_vx_constraint-159.c | 65 + .../riscv/rvv/base/binop_vx_constraint-16.c | 160 + .../riscv/rvv/base/binop_vx_constraint-160.c | 133 + .../riscv/rvv/base/binop_vx_constraint-161.c | 76 + .../riscv/rvv/base/binop_vx_constraint-162.c | 17 + .../riscv/rvv/base/binop_vx_constraint-163.c | 16 + .../riscv/rvv/base/binop_vx_constraint-164.c | 16 + .../riscv/rvv/base/binop_vx_constraint-165.c | 13 + .../riscv/rvv/base/binop_vx_constraint-166.c | 15 + .../riscv/rvv/base/binop_vx_constraint-17.c | 160 + .../riscv/rvv/base/binop_vx_constraint-18.c | 132 + .../riscv/rvv/base/binop_vx_constraint-19.c | 160 + .../riscv/rvv/base/binop_vx_constraint-2.c | 132 + .../riscv/rvv/base/binop_vx_constraint-20.c | 132 + .../riscv/rvv/base/binop_vx_constraint-21.c | 160 + .../riscv/rvv/base/binop_vx_constraint-22.c | 132 + .../riscv/rvv/base/binop_vx_constraint-23.c | 160 + .../riscv/rvv/base/binop_vx_constraint-24.c | 132 + .../riscv/rvv/base/binop_vx_constraint-25.c | 160 + .../riscv/rvv/base/binop_vx_constraint-26.c | 132 + .../riscv/rvv/base/binop_vx_constraint-27.c | 160 + .../riscv/rvv/base/binop_vx_constraint-28.c | 132 + .../riscv/rvv/base/binop_vx_constraint-29.c | 160 + .../riscv/rvv/base/binop_vx_constraint-3.c | 132 + .../riscv/rvv/base/binop_vx_constraint-30.c | 132 + .../riscv/rvv/base/binop_vx_constraint-31.c | 160 + .../riscv/rvv/base/binop_vx_constraint-32.c | 132 + .../riscv/rvv/base/binop_vx_constraint-33.c | 160 + .../riscv/rvv/base/binop_vx_constraint-34.c | 132 + .../riscv/rvv/base/binop_vx_constraint-35.c | 160 + .../riscv/rvv/base/binop_vx_constraint-36.c | 132 + .../riscv/rvv/base/binop_vx_constraint-37.c | 132 + .../riscv/rvv/base/binop_vx_constraint-38.c | 132 + .../riscv/rvv/base/binop_vx_constraint-39.c | 132 + .../riscv/rvv/base/binop_vx_constraint-4.c | 160 + .../riscv/rvv/base/binop_vx_constraint-40.c | 160 + .../riscv/rvv/base/binop_vx_constraint-41.c | 132 + .../riscv/rvv/base/binop_vx_constraint-42.c | 132 + .../riscv/rvv/base/binop_vx_constraint-43.c | 132 + .../riscv/rvv/base/binop_vx_constraint-44.c | 160 + .../riscv/rvv/base/binop_vx_constraint-45.c | 123 + .../riscv/rvv/base/binop_vx_constraint-46.c | 72 + .../riscv/rvv/base/binop_vx_constraint-47.c | 16 + .../riscv/rvv/base/binop_vx_constraint-48.c | 16 + .../riscv/rvv/base/binop_vx_constraint-49.c | 16 + .../riscv/rvv/base/binop_vx_constraint-5.c | 132 + .../riscv/rvv/base/binop_vx_constraint-50.c | 18 + .../riscv/rvv/base/binop_vx_constraint-51.c | 123 + .../riscv/rvv/base/binop_vx_constraint-52.c | 72 + .../riscv/rvv/base/binop_vx_constraint-53.c | 16 + .../riscv/rvv/base/binop_vx_constraint-54.c | 16 + .../riscv/rvv/base/binop_vx_constraint-55.c | 16 + .../riscv/rvv/base/binop_vx_constraint-56.c | 18 + .../riscv/rvv/base/binop_vx_constraint-57.c | 123 + .../riscv/rvv/base/binop_vx_constraint-58.c | 72 + .../riscv/rvv/base/binop_vx_constraint-59.c | 16 + .../riscv/rvv/base/binop_vx_constraint-6.c | 132 + .../riscv/rvv/base/binop_vx_constraint-60.c | 16 + .../riscv/rvv/base/binop_vx_constraint-61.c | 16 + .../riscv/rvv/base/binop_vx_constraint-62.c | 18 + .../riscv/rvv/base/binop_vx_constraint-63.c | 123 + .../riscv/rvv/base/binop_vx_constraint-64.c | 72 + .../riscv/rvv/base/binop_vx_constraint-65.c | 16 + .../riscv/rvv/base/binop_vx_constraint-66.c | 16 + .../riscv/rvv/base/binop_vx_constraint-67.c | 16 + .../riscv/rvv/base/binop_vx_constraint-68.c | 18 + .../riscv/rvv/base/binop_vx_constraint-69.c | 123 + .../riscv/rvv/base/binop_vx_constraint-7.c | 132 + .../riscv/rvv/base/binop_vx_constraint-70.c | 72 + .../riscv/rvv/base/binop_vx_constraint-71.c | 16 + .../riscv/rvv/base/binop_vx_constraint-72.c | 16 + .../riscv/rvv/base/binop_vx_constraint-73.c | 16 + .../riscv/rvv/base/binop_vx_constraint-74.c | 18 + .../riscv/rvv/base/binop_vx_constraint-75.c | 72 + .../riscv/rvv/base/binop_vx_constraint-76.c | 16 + .../riscv/rvv/base/binop_vx_constraint-77.c | 16 + .../riscv/rvv/base/binop_vx_constraint-78.c | 16 + .../riscv/rvv/base/binop_vx_constraint-79.c | 18 + .../riscv/rvv/base/binop_vx_constraint-8.c | 160 + .../riscv/rvv/base/binop_vx_constraint-80.c | 72 + .../riscv/rvv/base/binop_vx_constraint-81.c | 16 + .../riscv/rvv/base/binop_vx_constraint-82.c | 16 + .../riscv/rvv/base/binop_vx_constraint-83.c | 16 + .../riscv/rvv/base/binop_vx_constraint-84.c | 18 + .../riscv/rvv/base/binop_vx_constraint-85.c | 123 + .../riscv/rvv/base/binop_vx_constraint-86.c | 72 + .../riscv/rvv/base/binop_vx_constraint-87.c | 16 + .../riscv/rvv/base/binop_vx_constraint-88.c | 16 + .../riscv/rvv/base/binop_vx_constraint-89.c | 16 + .../riscv/rvv/base/binop_vx_constraint-9.c | 132 + .../riscv/rvv/base/binop_vx_constraint-90.c | 18 + .../riscv/rvv/base/binop_vx_constraint-91.c | 123 + .../riscv/rvv/base/binop_vx_constraint-92.c | 72 + .../riscv/rvv/base/binop_vx_constraint-93.c | 16 + .../riscv/rvv/base/binop_vx_constraint-94.c | 16 + .../riscv/rvv/base/binop_vx_constraint-95.c | 16 + .../riscv/rvv/base/binop_vx_constraint-96.c | 18 + .../riscv/rvv/base/binop_vx_constraint-97.c | 123 + .../riscv/rvv/base/binop_vx_constraint-98.c | 72 + .../riscv/rvv/base/binop_vx_constraint-99.c | 16 + .../riscv/rvv/base/shift_vx_constraint-1.c | 134 + .../riscv/rvv/base/ternop_vv_constraint-1.c | 83 + .../riscv/rvv/base/ternop_vv_constraint-2.c | 83 + .../riscv/rvv/base/ternop_vx_constraint-1.c | 71 + .../riscv/rvv/base/ternop_vx_constraint-2.c | 38 + .../riscv/rvv/base/ternop_vx_constraint-3.c | 125 + .../riscv/rvv/base/ternop_vx_constraint-4.c | 123 + .../riscv/rvv/base/ternop_vx_constraint-5.c | 123 + .../riscv/rvv/base/ternop_vx_constraint-6.c | 130 + .../riscv/rvv/base/ternop_vx_constraint-7.c | 130 + .../{vle-constraint-1.c => unop_v_constraint-1.c} | 61 +- .../riscv/rvv/base/unop_v_constraint-2.c | 132 + .../gcc.target/riscv/rvv/base/vaadd_vv-1.c | 160 + .../gcc.target/riscv/rvv/base/vaadd_vv-2.c | 160 + .../gcc.target/riscv/rvv/base/vaadd_vv-3.c | 160 + .../gcc.target/riscv/rvv/base/vaadd_vv_m-1.c | 160 + .../gcc.target/riscv/rvv/base/vaadd_vv_m-2.c | 160 + .../gcc.target/riscv/rvv/base/vaadd_vv_m-3.c | 160 + .../gcc.target/riscv/rvv/base/vaadd_vv_mu-1.c | 160 + .../gcc.target/riscv/rvv/base/vaadd_vv_mu-2.c | 160 + .../gcc.target/riscv/rvv/base/vaadd_vv_mu-3.c | 160 + .../gcc.target/riscv/rvv/base/vaadd_vv_tu-1.c | 160 + .../gcc.target/riscv/rvv/base/vaadd_vv_tu-2.c | 160 + .../gcc.target/riscv/rvv/base/vaadd_vv_tu-3.c | 160 + .../gcc.target/riscv/rvv/base/vaadd_vv_tum-1.c | 160 + .../gcc.target/riscv/rvv/base/vaadd_vv_tum-2.c | 160 + .../gcc.target/riscv/rvv/base/vaadd_vv_tum-3.c | 160 + .../gcc.target/riscv/rvv/base/vaadd_vv_tumu-1.c | 160 + .../gcc.target/riscv/rvv/base/vaadd_vv_tumu-2.c | 160 + .../gcc.target/riscv/rvv/base/vaadd_vv_tumu-3.c | 160 + .../gcc.target/riscv/rvv/base/vaadd_vx_m_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vaadd_vx_m_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vaadd_vx_m_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vaadd_vx_m_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vaadd_vx_m_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vaadd_vx_m_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vaadd_vx_mu_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vaadd_vx_mu_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vaadd_vx_mu_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vaadd_vx_mu_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vaadd_vx_mu_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vaadd_vx_mu_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vaadd_vx_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vaadd_vx_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vaadd_vx_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vaadd_vx_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vaadd_vx_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vaadd_vx_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vaadd_vx_tu_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vaadd_vx_tu_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vaadd_vx_tu_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vaadd_vx_tu_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vaadd_vx_tu_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vaadd_vx_tu_rv64-3.c | 160 + .../riscv/rvv/base/vaadd_vx_tum_rv32-1.c | 157 + .../riscv/rvv/base/vaadd_vx_tum_rv32-2.c | 157 + .../riscv/rvv/base/vaadd_vx_tum_rv32-3.c | 157 + .../riscv/rvv/base/vaadd_vx_tum_rv64-1.c | 160 + .../riscv/rvv/base/vaadd_vx_tum_rv64-2.c | 160 + .../riscv/rvv/base/vaadd_vx_tum_rv64-3.c | 160 + .../riscv/rvv/base/vaadd_vx_tumu_rv32-1.c | 157 + .../riscv/rvv/base/vaadd_vx_tumu_rv32-2.c | 157 + .../riscv/rvv/base/vaadd_vx_tumu_rv32-3.c | 157 + .../riscv/rvv/base/vaadd_vx_tumu_rv64-1.c | 160 + .../riscv/rvv/base/vaadd_vx_tumu_rv64-2.c | 160 + .../riscv/rvv/base/vaadd_vx_tumu_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vaaddu_vv-1.c | 160 + .../gcc.target/riscv/rvv/base/vaaddu_vv-2.c | 160 + .../gcc.target/riscv/rvv/base/vaaddu_vv-3.c | 160 + .../gcc.target/riscv/rvv/base/vaaddu_vv_m-1.c | 160 + .../gcc.target/riscv/rvv/base/vaaddu_vv_m-2.c | 160 + .../gcc.target/riscv/rvv/base/vaaddu_vv_m-3.c | 160 + .../gcc.target/riscv/rvv/base/vaaddu_vv_mu-1.c | 160 + .../gcc.target/riscv/rvv/base/vaaddu_vv_mu-2.c | 160 + .../gcc.target/riscv/rvv/base/vaaddu_vv_mu-3.c | 160 + .../gcc.target/riscv/rvv/base/vaaddu_vv_tu-1.c | 160 + .../gcc.target/riscv/rvv/base/vaaddu_vv_tu-2.c | 160 + .../gcc.target/riscv/rvv/base/vaaddu_vv_tu-3.c | 160 + .../gcc.target/riscv/rvv/base/vaaddu_vv_tum-1.c | 160 + .../gcc.target/riscv/rvv/base/vaaddu_vv_tum-2.c | 160 + .../gcc.target/riscv/rvv/base/vaaddu_vv_tum-3.c | 160 + .../gcc.target/riscv/rvv/base/vaaddu_vv_tumu-1.c | 160 + .../gcc.target/riscv/rvv/base/vaaddu_vv_tumu-2.c | 160 + .../gcc.target/riscv/rvv/base/vaaddu_vv_tumu-3.c | 160 + .../gcc.target/riscv/rvv/base/vaaddu_vx_m_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vaaddu_vx_m_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vaaddu_vx_m_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vaaddu_vx_m_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vaaddu_vx_m_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vaaddu_vx_m_rv64-3.c | 160 + .../riscv/rvv/base/vaaddu_vx_mu_rv32-1.c | 157 + .../riscv/rvv/base/vaaddu_vx_mu_rv32-2.c | 157 + .../riscv/rvv/base/vaaddu_vx_mu_rv32-3.c | 157 + .../riscv/rvv/base/vaaddu_vx_mu_rv64-1.c | 160 + .../riscv/rvv/base/vaaddu_vx_mu_rv64-2.c | 160 + .../riscv/rvv/base/vaaddu_vx_mu_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vaaddu_vx_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vaaddu_vx_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vaaddu_vx_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vaaddu_vx_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vaaddu_vx_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vaaddu_vx_rv64-3.c | 160 + .../riscv/rvv/base/vaaddu_vx_tu_rv32-1.c | 157 + .../riscv/rvv/base/vaaddu_vx_tu_rv32-2.c | 157 + .../riscv/rvv/base/vaaddu_vx_tu_rv32-3.c | 157 + .../riscv/rvv/base/vaaddu_vx_tu_rv64-1.c | 160 + .../riscv/rvv/base/vaaddu_vx_tu_rv64-2.c | 160 + .../riscv/rvv/base/vaaddu_vx_tu_rv64-3.c | 160 + .../riscv/rvv/base/vaaddu_vx_tum_rv32-1.c | 157 + .../riscv/rvv/base/vaaddu_vx_tum_rv32-2.c | 157 + .../riscv/rvv/base/vaaddu_vx_tum_rv32-3.c | 157 + .../riscv/rvv/base/vaaddu_vx_tum_rv64-1.c | 160 + .../riscv/rvv/base/vaaddu_vx_tum_rv64-2.c | 160 + .../riscv/rvv/base/vaaddu_vx_tum_rv64-3.c | 160 + .../riscv/rvv/base/vaaddu_vx_tumu_rv32-1.c | 157 + .../riscv/rvv/base/vaaddu_vx_tumu_rv32-2.c | 157 + .../riscv/rvv/base/vaaddu_vx_tumu_rv32-3.c | 157 + .../riscv/rvv/base/vaaddu_vx_tumu_rv64-1.c | 160 + .../riscv/rvv/base/vaaddu_vx_tumu_rv64-2.c | 160 + .../riscv/rvv/base/vaaddu_vx_tumu_rv64-3.c | 160 + gcc/testsuite/gcc.target/riscv/rvv/base/vadc-1.c | 27 + gcc/testsuite/gcc.target/riscv/rvv/base/vadc-2.c | 48 + gcc/testsuite/gcc.target/riscv/rvv/base/vadc-3.c | 78 + gcc/testsuite/gcc.target/riscv/rvv/base/vadc-4.c | 79 + .../gcc.target/riscv/rvv/base/vadc_vvm-1.c | 292 + .../gcc.target/riscv/rvv/base/vadc_vvm-2.c | 292 + .../gcc.target/riscv/rvv/base/vadc_vvm-3.c | 292 + .../gcc.target/riscv/rvv/base/vadc_vvm_tu-1.c | 292 + .../gcc.target/riscv/rvv/base/vadc_vvm_tu-2.c | 292 + .../gcc.target/riscv/rvv/base/vadc_vvm_tu-3.c | 292 + .../gcc.target/riscv/rvv/base/vadc_vxm_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vadc_vxm_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vadc_vxm_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vadc_vxm_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vadc_vxm_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vadc_vxm_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vadc_vxm_tu_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vadc_vxm_tu_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vadc_vxm_tu_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vadc_vxm_tu_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vadc_vxm_tu_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vadc_vxm_tu_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vadd_vv-1.c | 292 + .../gcc.target/riscv/rvv/base/vadd_vv-2.c | 292 + .../gcc.target/riscv/rvv/base/vadd_vv-3.c | 292 + .../gcc.target/riscv/rvv/base/vadd_vv_m-1.c | 292 + .../gcc.target/riscv/rvv/base/vadd_vv_m-2.c | 292 + .../gcc.target/riscv/rvv/base/vadd_vv_m-3.c | 292 + .../gcc.target/riscv/rvv/base/vadd_vv_mu-1.c | 292 + .../gcc.target/riscv/rvv/base/vadd_vv_mu-2.c | 292 + .../gcc.target/riscv/rvv/base/vadd_vv_mu-3.c | 292 + .../gcc.target/riscv/rvv/base/vadd_vv_tu-1.c | 292 + .../gcc.target/riscv/rvv/base/vadd_vv_tu-2.c | 292 + .../gcc.target/riscv/rvv/base/vadd_vv_tu-3.c | 292 + .../gcc.target/riscv/rvv/base/vadd_vv_tum-1.c | 292 + .../gcc.target/riscv/rvv/base/vadd_vv_tum-2.c | 292 + .../gcc.target/riscv/rvv/base/vadd_vv_tum-3.c | 292 + .../gcc.target/riscv/rvv/base/vadd_vv_tumu-1.c | 292 + .../gcc.target/riscv/rvv/base/vadd_vv_tumu-2.c | 292 + .../gcc.target/riscv/rvv/base/vadd_vv_tumu-3.c | 292 + .../gcc.target/riscv/rvv/base/vadd_vx_m_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vadd_vx_m_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vadd_vx_m_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vadd_vx_m_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vadd_vx_m_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vadd_vx_m_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vadd_vx_mu_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vadd_vx_mu_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vadd_vx_mu_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vadd_vx_mu_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vadd_vx_mu_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vadd_vx_mu_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vadd_vx_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vadd_vx_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vadd_vx_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vadd_vx_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vadd_vx_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vadd_vx_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vadd_vx_tu_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vadd_vx_tu_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vadd_vx_tu_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vadd_vx_tu_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vadd_vx_tu_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vadd_vx_tu_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vadd_vx_tum_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vadd_vx_tum_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vadd_vx_tum_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vadd_vx_tum_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vadd_vx_tum_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vadd_vx_tum_rv64-3.c | 292 + .../riscv/rvv/base/vadd_vx_tumu_rv32-1.c | 289 + .../riscv/rvv/base/vadd_vx_tumu_rv32-2.c | 289 + .../riscv/rvv/base/vadd_vx_tumu_rv32-3.c | 289 + .../riscv/rvv/base/vadd_vx_tumu_rv64-1.c | 292 + .../riscv/rvv/base/vadd_vx_tumu_rv64-2.c | 292 + .../riscv/rvv/base/vadd_vx_tumu_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vand_vv-1.c | 292 + .../gcc.target/riscv/rvv/base/vand_vv-2.c | 292 + .../gcc.target/riscv/rvv/base/vand_vv-3.c | 292 + .../gcc.target/riscv/rvv/base/vand_vv_m-1.c | 292 + .../gcc.target/riscv/rvv/base/vand_vv_m-2.c | 292 + .../gcc.target/riscv/rvv/base/vand_vv_m-3.c | 292 + .../gcc.target/riscv/rvv/base/vand_vv_mu-1.c | 292 + .../gcc.target/riscv/rvv/base/vand_vv_mu-2.c | 292 + .../gcc.target/riscv/rvv/base/vand_vv_mu-3.c | 292 + .../gcc.target/riscv/rvv/base/vand_vv_tu-1.c | 292 + .../gcc.target/riscv/rvv/base/vand_vv_tu-2.c | 292 + .../gcc.target/riscv/rvv/base/vand_vv_tu-3.c | 292 + .../gcc.target/riscv/rvv/base/vand_vv_tum-1.c | 292 + .../gcc.target/riscv/rvv/base/vand_vv_tum-2.c | 292 + .../gcc.target/riscv/rvv/base/vand_vv_tum-3.c | 292 + .../gcc.target/riscv/rvv/base/vand_vv_tumu-1.c | 292 + .../gcc.target/riscv/rvv/base/vand_vv_tumu-2.c | 292 + .../gcc.target/riscv/rvv/base/vand_vv_tumu-3.c | 292 + .../gcc.target/riscv/rvv/base/vand_vx_m_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vand_vx_m_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vand_vx_m_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vand_vx_m_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vand_vx_m_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vand_vx_m_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vand_vx_mu_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vand_vx_mu_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vand_vx_mu_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vand_vx_mu_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vand_vx_mu_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vand_vx_mu_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vand_vx_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vand_vx_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vand_vx_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vand_vx_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vand_vx_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vand_vx_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vand_vx_tu_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vand_vx_tu_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vand_vx_tu_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vand_vx_tu_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vand_vx_tu_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vand_vx_tu_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vand_vx_tum_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vand_vx_tum_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vand_vx_tum_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vand_vx_tum_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vand_vx_tum_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vand_vx_tum_rv64-3.c | 292 + .../riscv/rvv/base/vand_vx_tumu_rv32-1.c | 289 + .../riscv/rvv/base/vand_vx_tumu_rv32-2.c | 289 + .../riscv/rvv/base/vand_vx_tumu_rv32-3.c | 289 + .../riscv/rvv/base/vand_vx_tumu_rv64-1.c | 292 + .../riscv/rvv/base/vand_vx_tumu_rv64-2.c | 292 + .../riscv/rvv/base/vand_vx_tumu_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vasub_vv-1.c | 160 + .../gcc.target/riscv/rvv/base/vasub_vv-2.c | 160 + .../gcc.target/riscv/rvv/base/vasub_vv-3.c | 160 + .../gcc.target/riscv/rvv/base/vasub_vv_m-1.c | 160 + .../gcc.target/riscv/rvv/base/vasub_vv_m-2.c | 160 + .../gcc.target/riscv/rvv/base/vasub_vv_m-3.c | 160 + .../gcc.target/riscv/rvv/base/vasub_vv_mu-1.c | 160 + .../gcc.target/riscv/rvv/base/vasub_vv_mu-2.c | 160 + .../gcc.target/riscv/rvv/base/vasub_vv_mu-3.c | 160 + .../gcc.target/riscv/rvv/base/vasub_vv_tu-1.c | 160 + .../gcc.target/riscv/rvv/base/vasub_vv_tu-2.c | 160 + .../gcc.target/riscv/rvv/base/vasub_vv_tu-3.c | 160 + .../gcc.target/riscv/rvv/base/vasub_vv_tum-1.c | 160 + .../gcc.target/riscv/rvv/base/vasub_vv_tum-2.c | 160 + .../gcc.target/riscv/rvv/base/vasub_vv_tum-3.c | 160 + .../gcc.target/riscv/rvv/base/vasub_vv_tumu-1.c | 160 + .../gcc.target/riscv/rvv/base/vasub_vv_tumu-2.c | 160 + .../gcc.target/riscv/rvv/base/vasub_vv_tumu-3.c | 160 + .../gcc.target/riscv/rvv/base/vasub_vx_m_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vasub_vx_m_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vasub_vx_m_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vasub_vx_m_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vasub_vx_m_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vasub_vx_m_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vasub_vx_mu_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vasub_vx_mu_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vasub_vx_mu_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vasub_vx_mu_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vasub_vx_mu_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vasub_vx_mu_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vasub_vx_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vasub_vx_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vasub_vx_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vasub_vx_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vasub_vx_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vasub_vx_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vasub_vx_tu_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vasub_vx_tu_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vasub_vx_tu_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vasub_vx_tu_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vasub_vx_tu_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vasub_vx_tu_rv64-3.c | 160 + .../riscv/rvv/base/vasub_vx_tum_rv32-1.c | 157 + .../riscv/rvv/base/vasub_vx_tum_rv32-2.c | 157 + .../riscv/rvv/base/vasub_vx_tum_rv32-3.c | 157 + .../riscv/rvv/base/vasub_vx_tum_rv64-1.c | 160 + .../riscv/rvv/base/vasub_vx_tum_rv64-2.c | 160 + .../riscv/rvv/base/vasub_vx_tum_rv64-3.c | 160 + .../riscv/rvv/base/vasub_vx_tumu_rv32-1.c | 157 + .../riscv/rvv/base/vasub_vx_tumu_rv32-2.c | 157 + .../riscv/rvv/base/vasub_vx_tumu_rv32-3.c | 157 + .../riscv/rvv/base/vasub_vx_tumu_rv64-1.c | 160 + .../riscv/rvv/base/vasub_vx_tumu_rv64-2.c | 160 + .../riscv/rvv/base/vasub_vx_tumu_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vasubu_vv-1.c | 160 + .../gcc.target/riscv/rvv/base/vasubu_vv-2.c | 160 + .../gcc.target/riscv/rvv/base/vasubu_vv-3.c | 160 + .../gcc.target/riscv/rvv/base/vasubu_vv_m-1.c | 160 + .../gcc.target/riscv/rvv/base/vasubu_vv_m-2.c | 160 + .../gcc.target/riscv/rvv/base/vasubu_vv_m-3.c | 160 + .../gcc.target/riscv/rvv/base/vasubu_vv_mu-1.c | 160 + .../gcc.target/riscv/rvv/base/vasubu_vv_mu-2.c | 160 + .../gcc.target/riscv/rvv/base/vasubu_vv_mu-3.c | 160 + .../gcc.target/riscv/rvv/base/vasubu_vv_tu-1.c | 160 + .../gcc.target/riscv/rvv/base/vasubu_vv_tu-2.c | 160 + .../gcc.target/riscv/rvv/base/vasubu_vv_tu-3.c | 160 + .../gcc.target/riscv/rvv/base/vasubu_vv_tum-1.c | 160 + .../gcc.target/riscv/rvv/base/vasubu_vv_tum-2.c | 160 + .../gcc.target/riscv/rvv/base/vasubu_vv_tum-3.c | 160 + .../gcc.target/riscv/rvv/base/vasubu_vv_tumu-1.c | 160 + .../gcc.target/riscv/rvv/base/vasubu_vv_tumu-2.c | 160 + .../gcc.target/riscv/rvv/base/vasubu_vv_tumu-3.c | 160 + .../gcc.target/riscv/rvv/base/vasubu_vx_m_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vasubu_vx_m_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vasubu_vx_m_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vasubu_vx_m_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vasubu_vx_m_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vasubu_vx_m_rv64-3.c | 160 + .../riscv/rvv/base/vasubu_vx_mu_rv32-1.c | 157 + .../riscv/rvv/base/vasubu_vx_mu_rv32-2.c | 157 + .../riscv/rvv/base/vasubu_vx_mu_rv32-3.c | 157 + .../riscv/rvv/base/vasubu_vx_mu_rv64-1.c | 160 + .../riscv/rvv/base/vasubu_vx_mu_rv64-2.c | 160 + .../riscv/rvv/base/vasubu_vx_mu_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vasubu_vx_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vasubu_vx_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vasubu_vx_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vasubu_vx_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vasubu_vx_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vasubu_vx_rv64-3.c | 160 + .../riscv/rvv/base/vasubu_vx_tu_rv32-1.c | 157 + .../riscv/rvv/base/vasubu_vx_tu_rv32-2.c | 157 + .../riscv/rvv/base/vasubu_vx_tu_rv32-3.c | 157 + .../riscv/rvv/base/vasubu_vx_tu_rv64-1.c | 160 + .../riscv/rvv/base/vasubu_vx_tu_rv64-2.c | 160 + .../riscv/rvv/base/vasubu_vx_tu_rv64-3.c | 160 + .../riscv/rvv/base/vasubu_vx_tum_rv32-1.c | 157 + .../riscv/rvv/base/vasubu_vx_tum_rv32-2.c | 157 + .../riscv/rvv/base/vasubu_vx_tum_rv32-3.c | 157 + .../riscv/rvv/base/vasubu_vx_tum_rv64-1.c | 160 + .../riscv/rvv/base/vasubu_vx_tum_rv64-2.c | 160 + .../riscv/rvv/base/vasubu_vx_tum_rv64-3.c | 160 + .../riscv/rvv/base/vasubu_vx_tumu_rv32-1.c | 157 + .../riscv/rvv/base/vasubu_vx_tumu_rv32-2.c | 157 + .../riscv/rvv/base/vasubu_vx_tumu_rv32-3.c | 157 + .../riscv/rvv/base/vasubu_vx_tumu_rv64-1.c | 160 + .../riscv/rvv/base/vasubu_vx_tumu_rv64-2.c | 160 + .../riscv/rvv/base/vasubu_vx_tumu_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vdiv_vv-1.c | 160 + .../gcc.target/riscv/rvv/base/vdiv_vv-2.c | 160 + .../gcc.target/riscv/rvv/base/vdiv_vv-3.c | 160 + .../gcc.target/riscv/rvv/base/vdiv_vv_m-1.c | 160 + .../gcc.target/riscv/rvv/base/vdiv_vv_m-2.c | 160 + .../gcc.target/riscv/rvv/base/vdiv_vv_m-3.c | 160 + .../gcc.target/riscv/rvv/base/vdiv_vv_mu-1.c | 160 + .../gcc.target/riscv/rvv/base/vdiv_vv_mu-2.c | 160 + .../gcc.target/riscv/rvv/base/vdiv_vv_mu-3.c | 160 + .../gcc.target/riscv/rvv/base/vdiv_vv_tu-1.c | 160 + .../gcc.target/riscv/rvv/base/vdiv_vv_tu-2.c | 160 + .../gcc.target/riscv/rvv/base/vdiv_vv_tu-3.c | 160 + .../gcc.target/riscv/rvv/base/vdiv_vv_tum-1.c | 160 + .../gcc.target/riscv/rvv/base/vdiv_vv_tum-2.c | 160 + .../gcc.target/riscv/rvv/base/vdiv_vv_tum-3.c | 160 + .../gcc.target/riscv/rvv/base/vdiv_vv_tumu-1.c | 160 + .../gcc.target/riscv/rvv/base/vdiv_vv_tumu-2.c | 160 + .../gcc.target/riscv/rvv/base/vdiv_vv_tumu-3.c | 160 + .../gcc.target/riscv/rvv/base/vdiv_vx_m_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vdiv_vx_m_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vdiv_vx_m_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vdiv_vx_m_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vdiv_vx_m_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vdiv_vx_m_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vdiv_vx_mu_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vdiv_vx_mu_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vdiv_vx_mu_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vdiv_vx_mu_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vdiv_vx_mu_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vdiv_vx_mu_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vdiv_vx_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vdiv_vx_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vdiv_vx_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vdiv_vx_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vdiv_vx_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vdiv_vx_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vdiv_vx_tu_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vdiv_vx_tu_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vdiv_vx_tu_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vdiv_vx_tu_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vdiv_vx_tu_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vdiv_vx_tu_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vdiv_vx_tum_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vdiv_vx_tum_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vdiv_vx_tum_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vdiv_vx_tum_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vdiv_vx_tum_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vdiv_vx_tum_rv64-3.c | 160 + .../riscv/rvv/base/vdiv_vx_tumu_rv32-1.c | 157 + .../riscv/rvv/base/vdiv_vx_tumu_rv32-2.c | 157 + .../riscv/rvv/base/vdiv_vx_tumu_rv32-3.c | 157 + .../riscv/rvv/base/vdiv_vx_tumu_rv64-1.c | 160 + .../riscv/rvv/base/vdiv_vx_tumu_rv64-2.c | 160 + .../riscv/rvv/base/vdiv_vx_tumu_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vdivu_vv-1.c | 160 + .../gcc.target/riscv/rvv/base/vdivu_vv-2.c | 160 + .../gcc.target/riscv/rvv/base/vdivu_vv-3.c | 160 + .../gcc.target/riscv/rvv/base/vdivu_vv_m-1.c | 160 + .../gcc.target/riscv/rvv/base/vdivu_vv_m-2.c | 160 + .../gcc.target/riscv/rvv/base/vdivu_vv_m-3.c | 160 + .../gcc.target/riscv/rvv/base/vdivu_vv_mu-1.c | 160 + .../gcc.target/riscv/rvv/base/vdivu_vv_mu-2.c | 160 + .../gcc.target/riscv/rvv/base/vdivu_vv_mu-3.c | 160 + .../gcc.target/riscv/rvv/base/vdivu_vv_tu-1.c | 160 + .../gcc.target/riscv/rvv/base/vdivu_vv_tu-2.c | 160 + .../gcc.target/riscv/rvv/base/vdivu_vv_tu-3.c | 160 + .../gcc.target/riscv/rvv/base/vdivu_vv_tum-1.c | 160 + .../gcc.target/riscv/rvv/base/vdivu_vv_tum-2.c | 160 + .../gcc.target/riscv/rvv/base/vdivu_vv_tum-3.c | 160 + .../gcc.target/riscv/rvv/base/vdivu_vv_tumu-1.c | 160 + .../gcc.target/riscv/rvv/base/vdivu_vv_tumu-2.c | 160 + .../gcc.target/riscv/rvv/base/vdivu_vv_tumu-3.c | 160 + .../gcc.target/riscv/rvv/base/vdivu_vx_m_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vdivu_vx_m_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vdivu_vx_m_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vdivu_vx_m_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vdivu_vx_m_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vdivu_vx_m_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vdivu_vx_mu_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vdivu_vx_mu_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vdivu_vx_mu_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vdivu_vx_mu_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vdivu_vx_mu_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vdivu_vx_mu_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vdivu_vx_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vdivu_vx_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vdivu_vx_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vdivu_vx_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vdivu_vx_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vdivu_vx_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vdivu_vx_tu_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vdivu_vx_tu_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vdivu_vx_tu_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vdivu_vx_tu_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vdivu_vx_tu_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vdivu_vx_tu_rv64-3.c | 160 + .../riscv/rvv/base/vdivu_vx_tum_rv32-1.c | 157 + .../riscv/rvv/base/vdivu_vx_tum_rv32-2.c | 157 + .../riscv/rvv/base/vdivu_vx_tum_rv32-3.c | 157 + .../riscv/rvv/base/vdivu_vx_tum_rv64-1.c | 160 + .../riscv/rvv/base/vdivu_vx_tum_rv64-2.c | 160 + .../riscv/rvv/base/vdivu_vx_tum_rv64-3.c | 160 + .../riscv/rvv/base/vdivu_vx_tumu_rv32-1.c | 157 + .../riscv/rvv/base/vdivu_vx_tumu_rv32-2.c | 157 + .../riscv/rvv/base/vdivu_vx_tumu_rv32-3.c | 157 + .../riscv/rvv/base/vdivu_vx_tumu_rv64-1.c | 160 + .../riscv/rvv/base/vdivu_vx_tumu_rv64-2.c | 160 + .../riscv/rvv/base/vdivu_vx_tumu_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vmacc_vv-1.c | 292 + .../gcc.target/riscv/rvv/base/vmacc_vv-2.c | 292 + .../gcc.target/riscv/rvv/base/vmacc_vv-3.c | 292 + .../gcc.target/riscv/rvv/base/vmacc_vv_m-1.c | 292 + .../gcc.target/riscv/rvv/base/vmacc_vv_m-2.c | 292 + .../gcc.target/riscv/rvv/base/vmacc_vv_m-3.c | 292 + .../gcc.target/riscv/rvv/base/vmacc_vv_mu-1.c | 292 + .../gcc.target/riscv/rvv/base/vmacc_vv_mu-2.c | 292 + .../gcc.target/riscv/rvv/base/vmacc_vv_mu-3.c | 292 + .../gcc.target/riscv/rvv/base/vmacc_vv_tu-1.c | 292 + .../gcc.target/riscv/rvv/base/vmacc_vv_tu-2.c | 292 + .../gcc.target/riscv/rvv/base/vmacc_vv_tu-3.c | 292 + .../gcc.target/riscv/rvv/base/vmacc_vv_tum-1.c | 292 + .../gcc.target/riscv/rvv/base/vmacc_vv_tum-2.c | 292 + .../gcc.target/riscv/rvv/base/vmacc_vv_tum-3.c | 292 + .../gcc.target/riscv/rvv/base/vmacc_vv_tumu-1.c | 292 + .../gcc.target/riscv/rvv/base/vmacc_vv_tumu-2.c | 292 + .../gcc.target/riscv/rvv/base/vmacc_vv_tumu-3.c | 292 + .../gcc.target/riscv/rvv/base/vmacc_vx_m_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vmacc_vx_m_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vmacc_vx_m_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vmacc_vx_m_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vmacc_vx_m_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vmacc_vx_m_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vmacc_vx_mu_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vmacc_vx_mu_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vmacc_vx_mu_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vmacc_vx_mu_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vmacc_vx_mu_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vmacc_vx_mu_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vmacc_vx_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vmacc_vx_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vmacc_vx_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vmacc_vx_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vmacc_vx_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vmacc_vx_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vmacc_vx_tu_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vmacc_vx_tu_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vmacc_vx_tu_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vmacc_vx_tu_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vmacc_vx_tu_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vmacc_vx_tu_rv64-3.c | 292 + .../riscv/rvv/base/vmacc_vx_tum_rv32-1.c | 289 + .../riscv/rvv/base/vmacc_vx_tum_rv32-2.c | 289 + .../riscv/rvv/base/vmacc_vx_tum_rv32-3.c | 289 + .../riscv/rvv/base/vmacc_vx_tum_rv64-1.c | 292 + .../riscv/rvv/base/vmacc_vx_tum_rv64-2.c | 292 + .../riscv/rvv/base/vmacc_vx_tum_rv64-3.c | 292 + .../riscv/rvv/base/vmacc_vx_tumu_rv32-1.c | 289 + .../riscv/rvv/base/vmacc_vx_tumu_rv32-2.c | 289 + .../riscv/rvv/base/vmacc_vx_tumu_rv32-3.c | 289 + .../riscv/rvv/base/vmacc_vx_tumu_rv64-1.c | 292 + .../riscv/rvv/base/vmacc_vx_tumu_rv64-2.c | 292 + .../riscv/rvv/base/vmacc_vx_tumu_rv64-3.c | 292 + gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-1.c | 25 + gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-2.c | 43 + gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-3.c | 78 + gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-4.c | 79 + gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-5.c | 24 + gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-6.c | 43 + gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-7.c | 85 + gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-8.c | 86 + .../gcc.target/riscv/rvv/base/vmadc_vv-1.c | 292 + .../gcc.target/riscv/rvv/base/vmadc_vv-2.c | 292 + .../gcc.target/riscv/rvv/base/vmadc_vv-3.c | 292 + .../gcc.target/riscv/rvv/base/vmadc_vvm-1.c | 292 + .../gcc.target/riscv/rvv/base/vmadc_vvm-2.c | 292 + .../gcc.target/riscv/rvv/base/vmadc_vvm-3.c | 292 + .../gcc.target/riscv/rvv/base/vmadc_vx_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vmadc_vx_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vmadc_vx_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vmadc_vx_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vmadc_vx_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vmadc_vx_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vmadc_vxm_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vmadc_vxm_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vmadc_vxm_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vmadc_vxm_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vmadc_vxm_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vmadc_vxm_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vmadd_vv-1.c | 292 + .../gcc.target/riscv/rvv/base/vmadd_vv-2.c | 292 + .../gcc.target/riscv/rvv/base/vmadd_vv-3.c | 292 + .../gcc.target/riscv/rvv/base/vmadd_vv_m-1.c | 292 + .../gcc.target/riscv/rvv/base/vmadd_vv_m-2.c | 292 + .../gcc.target/riscv/rvv/base/vmadd_vv_m-3.c | 292 + .../gcc.target/riscv/rvv/base/vmadd_vv_mu-1.c | 292 + .../gcc.target/riscv/rvv/base/vmadd_vv_mu-2.c | 292 + .../gcc.target/riscv/rvv/base/vmadd_vv_mu-3.c | 292 + .../gcc.target/riscv/rvv/base/vmadd_vv_tu-1.c | 292 + .../gcc.target/riscv/rvv/base/vmadd_vv_tu-2.c | 292 + .../gcc.target/riscv/rvv/base/vmadd_vv_tu-3.c | 292 + .../gcc.target/riscv/rvv/base/vmadd_vv_tum-1.c | 292 + .../gcc.target/riscv/rvv/base/vmadd_vv_tum-2.c | 292 + .../gcc.target/riscv/rvv/base/vmadd_vv_tum-3.c | 292 + .../gcc.target/riscv/rvv/base/vmadd_vv_tumu-1.c | 292 + .../gcc.target/riscv/rvv/base/vmadd_vv_tumu-2.c | 292 + .../gcc.target/riscv/rvv/base/vmadd_vv_tumu-3.c | 292 + .../gcc.target/riscv/rvv/base/vmadd_vx_m_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vmadd_vx_m_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vmadd_vx_m_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vmadd_vx_m_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vmadd_vx_m_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vmadd_vx_m_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vmadd_vx_mu_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vmadd_vx_mu_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vmadd_vx_mu_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vmadd_vx_mu_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vmadd_vx_mu_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vmadd_vx_mu_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vmadd_vx_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vmadd_vx_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vmadd_vx_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vmadd_vx_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vmadd_vx_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vmadd_vx_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vmadd_vx_tu_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vmadd_vx_tu_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vmadd_vx_tu_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vmadd_vx_tu_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vmadd_vx_tu_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vmadd_vx_tu_rv64-3.c | 292 + .../riscv/rvv/base/vmadd_vx_tum_rv32-1.c | 289 + .../riscv/rvv/base/vmadd_vx_tum_rv32-2.c | 289 + .../riscv/rvv/base/vmadd_vx_tum_rv32-3.c | 289 + .../riscv/rvv/base/vmadd_vx_tum_rv64-1.c | 292 + .../riscv/rvv/base/vmadd_vx_tum_rv64-2.c | 292 + .../riscv/rvv/base/vmadd_vx_tum_rv64-3.c | 292 + .../riscv/rvv/base/vmadd_vx_tumu_rv32-1.c | 289 + .../riscv/rvv/base/vmadd_vx_tumu_rv32-2.c | 289 + .../riscv/rvv/base/vmadd_vx_tumu_rv32-3.c | 289 + .../riscv/rvv/base/vmadd_vx_tumu_rv64-1.c | 292 + .../riscv/rvv/base/vmadd_vx_tumu_rv64-2.c | 292 + .../riscv/rvv/base/vmadd_vx_tumu_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vmax_vv-1.c | 160 + .../gcc.target/riscv/rvv/base/vmax_vv-2.c | 160 + .../gcc.target/riscv/rvv/base/vmax_vv-3.c | 160 + .../gcc.target/riscv/rvv/base/vmax_vv_m-1.c | 160 + .../gcc.target/riscv/rvv/base/vmax_vv_m-2.c | 160 + .../gcc.target/riscv/rvv/base/vmax_vv_m-3.c | 160 + .../gcc.target/riscv/rvv/base/vmax_vv_mu-1.c | 160 + .../gcc.target/riscv/rvv/base/vmax_vv_mu-2.c | 160 + .../gcc.target/riscv/rvv/base/vmax_vv_mu-3.c | 160 + .../gcc.target/riscv/rvv/base/vmax_vv_tu-1.c | 160 + .../gcc.target/riscv/rvv/base/vmax_vv_tu-2.c | 160 + .../gcc.target/riscv/rvv/base/vmax_vv_tu-3.c | 160 + .../gcc.target/riscv/rvv/base/vmax_vv_tum-1.c | 160 + .../gcc.target/riscv/rvv/base/vmax_vv_tum-2.c | 160 + .../gcc.target/riscv/rvv/base/vmax_vv_tum-3.c | 160 + .../gcc.target/riscv/rvv/base/vmax_vv_tumu-1.c | 160 + .../gcc.target/riscv/rvv/base/vmax_vv_tumu-2.c | 160 + .../gcc.target/riscv/rvv/base/vmax_vv_tumu-3.c | 160 + .../gcc.target/riscv/rvv/base/vmax_vx_m_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vmax_vx_m_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vmax_vx_m_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vmax_vx_m_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vmax_vx_m_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vmax_vx_m_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vmax_vx_mu_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vmax_vx_mu_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vmax_vx_mu_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vmax_vx_mu_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vmax_vx_mu_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vmax_vx_mu_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vmax_vx_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vmax_vx_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vmax_vx_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vmax_vx_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vmax_vx_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vmax_vx_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vmax_vx_tu_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vmax_vx_tu_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vmax_vx_tu_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vmax_vx_tu_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vmax_vx_tu_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vmax_vx_tu_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vmax_vx_tum_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vmax_vx_tum_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vmax_vx_tum_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vmax_vx_tum_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vmax_vx_tum_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vmax_vx_tum_rv64-3.c | 160 + .../riscv/rvv/base/vmax_vx_tumu_rv32-1.c | 157 + .../riscv/rvv/base/vmax_vx_tumu_rv32-2.c | 157 + .../riscv/rvv/base/vmax_vx_tumu_rv32-3.c | 157 + .../riscv/rvv/base/vmax_vx_tumu_rv64-1.c | 160 + .../riscv/rvv/base/vmax_vx_tumu_rv64-2.c | 160 + .../riscv/rvv/base/vmax_vx_tumu_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vmaxu_vv-1.c | 160 + .../gcc.target/riscv/rvv/base/vmaxu_vv-2.c | 160 + .../gcc.target/riscv/rvv/base/vmaxu_vv-3.c | 160 + .../gcc.target/riscv/rvv/base/vmaxu_vv_m-1.c | 160 + .../gcc.target/riscv/rvv/base/vmaxu_vv_m-2.c | 160 + .../gcc.target/riscv/rvv/base/vmaxu_vv_m-3.c | 160 + .../gcc.target/riscv/rvv/base/vmaxu_vv_mu-1.c | 160 + .../gcc.target/riscv/rvv/base/vmaxu_vv_mu-2.c | 160 + .../gcc.target/riscv/rvv/base/vmaxu_vv_mu-3.c | 160 + .../gcc.target/riscv/rvv/base/vmaxu_vv_tu-1.c | 160 + .../gcc.target/riscv/rvv/base/vmaxu_vv_tu-2.c | 160 + .../gcc.target/riscv/rvv/base/vmaxu_vv_tu-3.c | 160 + .../gcc.target/riscv/rvv/base/vmaxu_vv_tum-1.c | 160 + .../gcc.target/riscv/rvv/base/vmaxu_vv_tum-2.c | 160 + .../gcc.target/riscv/rvv/base/vmaxu_vv_tum-3.c | 160 + .../gcc.target/riscv/rvv/base/vmaxu_vv_tumu-1.c | 160 + .../gcc.target/riscv/rvv/base/vmaxu_vv_tumu-2.c | 160 + .../gcc.target/riscv/rvv/base/vmaxu_vv_tumu-3.c | 160 + .../gcc.target/riscv/rvv/base/vmaxu_vx_m_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vmaxu_vx_m_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vmaxu_vx_m_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vmaxu_vx_m_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vmaxu_vx_m_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vmaxu_vx_m_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vmaxu_vx_mu_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vmaxu_vx_mu_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vmaxu_vx_mu_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vmaxu_vx_mu_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vmaxu_vx_mu_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vmaxu_vx_mu_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vmaxu_vx_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vmaxu_vx_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vmaxu_vx_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vmaxu_vx_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vmaxu_vx_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vmaxu_vx_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vmaxu_vx_tu_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vmaxu_vx_tu_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vmaxu_vx_tu_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vmaxu_vx_tu_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vmaxu_vx_tu_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vmaxu_vx_tu_rv64-3.c | 160 + .../riscv/rvv/base/vmaxu_vx_tum_rv32-1.c | 157 + .../riscv/rvv/base/vmaxu_vx_tum_rv32-2.c | 157 + .../riscv/rvv/base/vmaxu_vx_tum_rv32-3.c | 157 + .../riscv/rvv/base/vmaxu_vx_tum_rv64-1.c | 160 + .../riscv/rvv/base/vmaxu_vx_tum_rv64-2.c | 160 + .../riscv/rvv/base/vmaxu_vx_tum_rv64-3.c | 160 + .../riscv/rvv/base/vmaxu_vx_tumu_rv32-1.c | 157 + .../riscv/rvv/base/vmaxu_vx_tumu_rv32-2.c | 157 + .../riscv/rvv/base/vmaxu_vx_tumu_rv32-3.c | 157 + .../riscv/rvv/base/vmaxu_vx_tumu_rv64-1.c | 160 + .../riscv/rvv/base/vmaxu_vx_tumu_rv64-2.c | 160 + .../riscv/rvv/base/vmaxu_vx_tumu_rv64-3.c | 160 + gcc/testsuite/gcc.target/riscv/rvv/base/vmerge-1.c | 27 + gcc/testsuite/gcc.target/riscv/rvv/base/vmerge-2.c | 47 + gcc/testsuite/gcc.target/riscv/rvv/base/vmerge-3.c | 78 + gcc/testsuite/gcc.target/riscv/rvv/base/vmerge-4.c | 79 + .../gcc.target/riscv/rvv/base/vmerge_vvm-1.c | 69 + .../gcc.target/riscv/rvv/base/vmerge_vvm-2.c | 69 + .../gcc.target/riscv/rvv/base/vmerge_vvm-3.c | 69 + .../gcc.target/riscv/rvv/base/vmerge_vvm-4.c | 292 + .../gcc.target/riscv/rvv/base/vmerge_vvm-5.c | 292 + .../gcc.target/riscv/rvv/base/vmerge_vvm-6.c | 292 + .../gcc.target/riscv/rvv/base/vmerge_vvm_tu-1.c | 69 + .../gcc.target/riscv/rvv/base/vmerge_vvm_tu-2.c | 69 + .../gcc.target/riscv/rvv/base/vmerge_vvm_tu-3.c | 69 + .../gcc.target/riscv/rvv/base/vmerge_vvm_tu-4.c | 292 + .../gcc.target/riscv/rvv/base/vmerge_vvm_tu-5.c | 292 + .../gcc.target/riscv/rvv/base/vmerge_vvm_tu-6.c | 292 + .../gcc.target/riscv/rvv/base/vmerge_vxm_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vmerge_vxm_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vmerge_vxm_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vmerge_vxm_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vmerge_vxm_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vmerge_vxm_rv64-3.c | 292 + .../riscv/rvv/base/vmerge_vxm_tu_rv32-1.c | 289 + .../riscv/rvv/base/vmerge_vxm_tu_rv32-2.c | 289 + .../riscv/rvv/base/vmerge_vxm_tu_rv32-3.c | 289 + .../riscv/rvv/base/vmerge_vxm_tu_rv64-1.c | 292 + .../riscv/rvv/base/vmerge_vxm_tu_rv64-2.c | 292 + .../riscv/rvv/base/vmerge_vxm_tu_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vmin_vv-1.c | 160 + .../gcc.target/riscv/rvv/base/vmin_vv-2.c | 160 + .../gcc.target/riscv/rvv/base/vmin_vv-3.c | 160 + .../gcc.target/riscv/rvv/base/vmin_vv_m-1.c | 160 + .../gcc.target/riscv/rvv/base/vmin_vv_m-2.c | 160 + .../gcc.target/riscv/rvv/base/vmin_vv_m-3.c | 160 + .../gcc.target/riscv/rvv/base/vmin_vv_mu-1.c | 160 + .../gcc.target/riscv/rvv/base/vmin_vv_mu-2.c | 160 + .../gcc.target/riscv/rvv/base/vmin_vv_mu-3.c | 160 + .../gcc.target/riscv/rvv/base/vmin_vv_tu-1.c | 160 + .../gcc.target/riscv/rvv/base/vmin_vv_tu-2.c | 160 + .../gcc.target/riscv/rvv/base/vmin_vv_tu-3.c | 160 + .../gcc.target/riscv/rvv/base/vmin_vv_tum-1.c | 160 + .../gcc.target/riscv/rvv/base/vmin_vv_tum-2.c | 160 + .../gcc.target/riscv/rvv/base/vmin_vv_tum-3.c | 160 + .../gcc.target/riscv/rvv/base/vmin_vv_tumu-1.c | 160 + .../gcc.target/riscv/rvv/base/vmin_vv_tumu-2.c | 160 + .../gcc.target/riscv/rvv/base/vmin_vv_tumu-3.c | 160 + .../gcc.target/riscv/rvv/base/vmin_vx_m_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vmin_vx_m_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vmin_vx_m_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vmin_vx_m_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vmin_vx_m_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vmin_vx_m_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vmin_vx_mu_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vmin_vx_mu_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vmin_vx_mu_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vmin_vx_mu_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vmin_vx_mu_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vmin_vx_mu_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vmin_vx_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vmin_vx_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vmin_vx_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vmin_vx_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vmin_vx_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vmin_vx_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vmin_vx_tu_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vmin_vx_tu_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vmin_vx_tu_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vmin_vx_tu_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vmin_vx_tu_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vmin_vx_tu_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vmin_vx_tum_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vmin_vx_tum_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vmin_vx_tum_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vmin_vx_tum_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vmin_vx_tum_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vmin_vx_tum_rv64-3.c | 160 + .../riscv/rvv/base/vmin_vx_tumu_rv32-1.c | 157 + .../riscv/rvv/base/vmin_vx_tumu_rv32-2.c | 157 + .../riscv/rvv/base/vmin_vx_tumu_rv32-3.c | 157 + .../riscv/rvv/base/vmin_vx_tumu_rv64-1.c | 160 + .../riscv/rvv/base/vmin_vx_tumu_rv64-2.c | 160 + .../riscv/rvv/base/vmin_vx_tumu_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vminu_vv-1.c | 160 + .../gcc.target/riscv/rvv/base/vminu_vv-2.c | 160 + .../gcc.target/riscv/rvv/base/vminu_vv-3.c | 160 + .../gcc.target/riscv/rvv/base/vminu_vv_m-1.c | 160 + .../gcc.target/riscv/rvv/base/vminu_vv_m-2.c | 160 + .../gcc.target/riscv/rvv/base/vminu_vv_m-3.c | 160 + .../gcc.target/riscv/rvv/base/vminu_vv_mu-1.c | 160 + .../gcc.target/riscv/rvv/base/vminu_vv_mu-2.c | 160 + .../gcc.target/riscv/rvv/base/vminu_vv_mu-3.c | 160 + .../gcc.target/riscv/rvv/base/vminu_vv_tu-1.c | 160 + .../gcc.target/riscv/rvv/base/vminu_vv_tu-2.c | 160 + .../gcc.target/riscv/rvv/base/vminu_vv_tu-3.c | 160 + .../gcc.target/riscv/rvv/base/vminu_vv_tum-1.c | 160 + .../gcc.target/riscv/rvv/base/vminu_vv_tum-2.c | 160 + .../gcc.target/riscv/rvv/base/vminu_vv_tum-3.c | 160 + .../gcc.target/riscv/rvv/base/vminu_vv_tumu-1.c | 160 + .../gcc.target/riscv/rvv/base/vminu_vv_tumu-2.c | 160 + .../gcc.target/riscv/rvv/base/vminu_vv_tumu-3.c | 160 + .../gcc.target/riscv/rvv/base/vminu_vx_m_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vminu_vx_m_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vminu_vx_m_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vminu_vx_m_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vminu_vx_m_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vminu_vx_m_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vminu_vx_mu_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vminu_vx_mu_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vminu_vx_mu_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vminu_vx_mu_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vminu_vx_mu_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vminu_vx_mu_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vminu_vx_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vminu_vx_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vminu_vx_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vminu_vx_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vminu_vx_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vminu_vx_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vminu_vx_tu_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vminu_vx_tu_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vminu_vx_tu_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vminu_vx_tu_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vminu_vx_tu_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vminu_vx_tu_rv64-3.c | 160 + .../riscv/rvv/base/vminu_vx_tum_rv32-1.c | 157 + .../riscv/rvv/base/vminu_vx_tum_rv32-2.c | 157 + .../riscv/rvv/base/vminu_vx_tum_rv32-3.c | 157 + .../riscv/rvv/base/vminu_vx_tum_rv64-1.c | 160 + .../riscv/rvv/base/vminu_vx_tum_rv64-2.c | 160 + .../riscv/rvv/base/vminu_vx_tum_rv64-3.c | 160 + .../riscv/rvv/base/vminu_vx_tumu_rv32-1.c | 157 + .../riscv/rvv/base/vminu_vx_tumu_rv32-2.c | 157 + .../riscv/rvv/base/vminu_vx_tumu_rv32-3.c | 157 + .../riscv/rvv/base/vminu_vx_tumu_rv64-1.c | 160 + .../riscv/rvv/base/vminu_vx_tumu_rv64-2.c | 160 + .../riscv/rvv/base/vminu_vx_tumu_rv64-3.c | 160 + gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc-1.c | 25 + gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc-2.c | 42 + gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc-3.c | 77 + gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc-4.c | 78 + gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc-5.c | 24 + gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc-6.c | 42 + gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc-7.c | 84 + gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc-8.c | 84 + .../gcc.target/riscv/rvv/base/vmsbc_vv-1.c | 292 + .../gcc.target/riscv/rvv/base/vmsbc_vv-2.c | 292 + .../gcc.target/riscv/rvv/base/vmsbc_vv-3.c | 292 + .../gcc.target/riscv/rvv/base/vmsbc_vvm-1.c | 292 + .../gcc.target/riscv/rvv/base/vmsbc_vvm-2.c | 292 + .../gcc.target/riscv/rvv/base/vmsbc_vvm-3.c | 292 + .../gcc.target/riscv/rvv/base/vmsbc_vx_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vmsbc_vx_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vmsbc_vx_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vmsbc_vx_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vmsbc_vx_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vmsbc_vx_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vmsbc_vxm_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vmsbc_vxm_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vmsbc_vxm_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vmsbc_vxm_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vmsbc_vxm_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vmsbc_vxm_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vmseq_vv-1.c | 292 + .../gcc.target/riscv/rvv/base/vmseq_vv-2.c | 292 + .../gcc.target/riscv/rvv/base/vmseq_vv-3.c | 292 + .../gcc.target/riscv/rvv/base/vmseq_vv_m-1.c | 292 + .../gcc.target/riscv/rvv/base/vmseq_vv_m-2.c | 292 + .../gcc.target/riscv/rvv/base/vmseq_vv_m-3.c | 292 + .../gcc.target/riscv/rvv/base/vmseq_vv_mu-1.c | 292 + .../gcc.target/riscv/rvv/base/vmseq_vv_mu-2.c | 292 + .../gcc.target/riscv/rvv/base/vmseq_vv_mu-3.c | 292 + .../gcc.target/riscv/rvv/base/vmseq_vx_m_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vmseq_vx_m_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vmseq_vx_m_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vmseq_vx_m_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vmseq_vx_m_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vmseq_vx_m_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vmseq_vx_mu_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vmseq_vx_mu_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vmseq_vx_mu_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vmseq_vx_mu_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vmseq_vx_mu_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vmseq_vx_mu_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vmseq_vx_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vmseq_vx_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vmseq_vx_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vmseq_vx_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vmseq_vx_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vmseq_vx_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vmsge_vv-1.c | 160 + .../gcc.target/riscv/rvv/base/vmsge_vv-2.c | 160 + .../gcc.target/riscv/rvv/base/vmsge_vv-3.c | 160 + .../gcc.target/riscv/rvv/base/vmsge_vv_m-1.c | 160 + .../gcc.target/riscv/rvv/base/vmsge_vv_m-2.c | 160 + .../gcc.target/riscv/rvv/base/vmsge_vv_m-3.c | 160 + .../gcc.target/riscv/rvv/base/vmsge_vv_mu-1.c | 160 + .../gcc.target/riscv/rvv/base/vmsge_vv_mu-2.c | 160 + .../gcc.target/riscv/rvv/base/vmsge_vv_mu-3.c | 160 + .../gcc.target/riscv/rvv/base/vmsge_vx_m_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vmsge_vx_m_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vmsge_vx_m_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vmsge_vx_m_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vmsge_vx_m_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vmsge_vx_m_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vmsge_vx_mu_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vmsge_vx_mu_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vmsge_vx_mu_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vmsge_vx_mu_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vmsge_vx_mu_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vmsge_vx_mu_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vmsge_vx_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vmsge_vx_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vmsge_vx_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vmsge_vx_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vmsge_vx_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vmsge_vx_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vmsgeu_vv-1.c | 160 + .../gcc.target/riscv/rvv/base/vmsgeu_vv-2.c | 160 + .../gcc.target/riscv/rvv/base/vmsgeu_vv-3.c | 160 + .../gcc.target/riscv/rvv/base/vmsgeu_vv_m-1.c | 160 + .../gcc.target/riscv/rvv/base/vmsgeu_vv_m-2.c | 160 + .../gcc.target/riscv/rvv/base/vmsgeu_vv_m-3.c | 160 + .../gcc.target/riscv/rvv/base/vmsgeu_vv_mu-1.c | 160 + .../gcc.target/riscv/rvv/base/vmsgeu_vv_mu-2.c | 160 + .../gcc.target/riscv/rvv/base/vmsgeu_vv_mu-3.c | 160 + .../gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv64-3.c | 160 + .../riscv/rvv/base/vmsgeu_vx_mu_rv32-1.c | 157 + .../riscv/rvv/base/vmsgeu_vx_mu_rv32-2.c | 157 + .../riscv/rvv/base/vmsgeu_vx_mu_rv32-3.c | 157 + .../riscv/rvv/base/vmsgeu_vx_mu_rv64-1.c | 160 + .../riscv/rvv/base/vmsgeu_vx_mu_rv64-2.c | 160 + .../riscv/rvv/base/vmsgeu_vx_mu_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vmsgeu_vx_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vmsgeu_vx_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vmsgeu_vx_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vmsgeu_vx_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vmsgeu_vx_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vmsgeu_vx_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vmsgt_vv-1.c | 160 + .../gcc.target/riscv/rvv/base/vmsgt_vv-2.c | 160 + .../gcc.target/riscv/rvv/base/vmsgt_vv-3.c | 160 + .../gcc.target/riscv/rvv/base/vmsgt_vv_m-1.c | 160 + .../gcc.target/riscv/rvv/base/vmsgt_vv_m-2.c | 160 + .../gcc.target/riscv/rvv/base/vmsgt_vv_m-3.c | 160 + .../gcc.target/riscv/rvv/base/vmsgt_vv_mu-1.c | 160 + .../gcc.target/riscv/rvv/base/vmsgt_vv_mu-2.c | 160 + .../gcc.target/riscv/rvv/base/vmsgt_vv_mu-3.c | 160 + .../gcc.target/riscv/rvv/base/vmsgt_vx_m_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vmsgt_vx_m_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vmsgt_vx_m_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vmsgt_vx_m_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vmsgt_vx_m_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vmsgt_vx_m_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vmsgt_vx_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vmsgt_vx_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vmsgt_vx_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vmsgt_vx_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vmsgt_vx_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vmsgt_vx_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vmsgtu_vv-1.c | 160 + .../gcc.target/riscv/rvv/base/vmsgtu_vv-2.c | 160 + .../gcc.target/riscv/rvv/base/vmsgtu_vv-3.c | 160 + .../gcc.target/riscv/rvv/base/vmsgtu_vv_m-1.c | 160 + .../gcc.target/riscv/rvv/base/vmsgtu_vv_m-2.c | 160 + .../gcc.target/riscv/rvv/base/vmsgtu_vv_m-3.c | 160 + .../gcc.target/riscv/rvv/base/vmsgtu_vv_mu-1.c | 160 + .../gcc.target/riscv/rvv/base/vmsgtu_vv_mu-2.c | 160 + .../gcc.target/riscv/rvv/base/vmsgtu_vv_mu-3.c | 160 + .../gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv64-3.c | 160 + .../riscv/rvv/base/vmsgtu_vx_mu_rv32-1.c | 157 + .../riscv/rvv/base/vmsgtu_vx_mu_rv32-2.c | 157 + .../riscv/rvv/base/vmsgtu_vx_mu_rv32-3.c | 157 + .../riscv/rvv/base/vmsgtu_vx_mu_rv64-1.c | 160 + .../riscv/rvv/base/vmsgtu_vx_mu_rv64-2.c | 160 + .../riscv/rvv/base/vmsgtu_vx_mu_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vmsgtu_vx_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vmsgtu_vx_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vmsgtu_vx_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vmsgtu_vx_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vmsgtu_vx_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vmsgtu_vx_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vmsle_vv-1.c | 160 + .../gcc.target/riscv/rvv/base/vmsle_vv-2.c | 160 + .../gcc.target/riscv/rvv/base/vmsle_vv-3.c | 160 + .../gcc.target/riscv/rvv/base/vmsle_vv_m-1.c | 160 + .../gcc.target/riscv/rvv/base/vmsle_vv_m-2.c | 160 + .../gcc.target/riscv/rvv/base/vmsle_vv_m-3.c | 160 + .../gcc.target/riscv/rvv/base/vmsle_vv_mu-1.c | 160 + .../gcc.target/riscv/rvv/base/vmsle_vv_mu-2.c | 160 + .../gcc.target/riscv/rvv/base/vmsle_vv_mu-3.c | 160 + .../gcc.target/riscv/rvv/base/vmsle_vx_m_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vmsle_vx_m_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vmsle_vx_m_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vmsle_vx_m_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vmsle_vx_m_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vmsle_vx_m_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vmsle_vx_mu_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vmsle_vx_mu_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vmsle_vx_mu_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vmsle_vx_mu_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vmsle_vx_mu_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vmsle_vx_mu_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vmsle_vx_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vmsle_vx_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vmsle_vx_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vmsle_vx_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vmsle_vx_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vmsle_vx_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vmsleu_vv-1.c | 160 + .../gcc.target/riscv/rvv/base/vmsleu_vv-2.c | 160 + .../gcc.target/riscv/rvv/base/vmsleu_vv-3.c | 160 + .../gcc.target/riscv/rvv/base/vmsleu_vv_m-1.c | 160 + .../gcc.target/riscv/rvv/base/vmsleu_vv_m-2.c | 160 + .../gcc.target/riscv/rvv/base/vmsleu_vv_m-3.c | 160 + .../gcc.target/riscv/rvv/base/vmsleu_vv_mu-1.c | 160 + .../gcc.target/riscv/rvv/base/vmsleu_vv_mu-2.c | 160 + .../gcc.target/riscv/rvv/base/vmsleu_vv_mu-3.c | 160 + .../gcc.target/riscv/rvv/base/vmsleu_vx_m_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vmsleu_vx_m_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vmsleu_vx_m_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vmsleu_vx_m_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vmsleu_vx_m_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vmsleu_vx_m_rv64-3.c | 160 + .../riscv/rvv/base/vmsleu_vx_mu_rv32-1.c | 157 + .../riscv/rvv/base/vmsleu_vx_mu_rv32-2.c | 157 + .../riscv/rvv/base/vmsleu_vx_mu_rv32-3.c | 157 + .../riscv/rvv/base/vmsleu_vx_mu_rv64-1.c | 160 + .../riscv/rvv/base/vmsleu_vx_mu_rv64-2.c | 160 + .../riscv/rvv/base/vmsleu_vx_mu_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vmsleu_vx_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vmsleu_vx_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vmsleu_vx_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vmsleu_vx_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vmsleu_vx_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vmsleu_vx_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vmslt_vv-1.c | 160 + .../gcc.target/riscv/rvv/base/vmslt_vv-2.c | 160 + .../gcc.target/riscv/rvv/base/vmslt_vv-3.c | 160 + .../gcc.target/riscv/rvv/base/vmslt_vv_m-1.c | 160 + .../gcc.target/riscv/rvv/base/vmslt_vv_m-2.c | 160 + .../gcc.target/riscv/rvv/base/vmslt_vv_m-3.c | 160 + .../gcc.target/riscv/rvv/base/vmslt_vv_mu-1.c | 160 + .../gcc.target/riscv/rvv/base/vmslt_vv_mu-2.c | 160 + .../gcc.target/riscv/rvv/base/vmslt_vv_mu-3.c | 160 + .../gcc.target/riscv/rvv/base/vmslt_vx_m_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vmslt_vx_m_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vmslt_vx_m_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vmslt_vx_m_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vmslt_vx_m_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vmslt_vx_m_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vmslt_vx_mu_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vmslt_vx_mu_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vmslt_vx_mu_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vmslt_vx_mu_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vmslt_vx_mu_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vmslt_vx_mu_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vmslt_vx_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vmslt_vx_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vmslt_vx_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vmslt_vx_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vmslt_vx_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vmslt_vx_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vmsltu_vv-1.c | 160 + .../gcc.target/riscv/rvv/base/vmsltu_vv-2.c | 160 + .../gcc.target/riscv/rvv/base/vmsltu_vv-3.c | 160 + .../gcc.target/riscv/rvv/base/vmsltu_vv_m-1.c | 160 + .../gcc.target/riscv/rvv/base/vmsltu_vv_m-2.c | 160 + .../gcc.target/riscv/rvv/base/vmsltu_vv_m-3.c | 160 + .../gcc.target/riscv/rvv/base/vmsltu_vv_mu-1.c | 160 + .../gcc.target/riscv/rvv/base/vmsltu_vv_mu-2.c | 160 + .../gcc.target/riscv/rvv/base/vmsltu_vv_mu-3.c | 160 + .../gcc.target/riscv/rvv/base/vmsltu_vx_m_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vmsltu_vx_m_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vmsltu_vx_m_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vmsltu_vx_m_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vmsltu_vx_m_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vmsltu_vx_m_rv64-3.c | 160 + .../riscv/rvv/base/vmsltu_vx_mu_rv32-1.c | 157 + .../riscv/rvv/base/vmsltu_vx_mu_rv32-2.c | 157 + .../riscv/rvv/base/vmsltu_vx_mu_rv32-3.c | 157 + .../riscv/rvv/base/vmsltu_vx_mu_rv64-1.c | 160 + .../riscv/rvv/base/vmsltu_vx_mu_rv64-2.c | 160 + .../riscv/rvv/base/vmsltu_vx_mu_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vmsltu_vx_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vmsltu_vx_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vmsltu_vx_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vmsltu_vx_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vmsltu_vx_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vmsltu_vx_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vmsne_vv-1.c | 292 + .../gcc.target/riscv/rvv/base/vmsne_vv-2.c | 292 + .../gcc.target/riscv/rvv/base/vmsne_vv-3.c | 292 + .../gcc.target/riscv/rvv/base/vmsne_vv_m-1.c | 292 + .../gcc.target/riscv/rvv/base/vmsne_vv_m-2.c | 292 + .../gcc.target/riscv/rvv/base/vmsne_vv_m-3.c | 292 + .../gcc.target/riscv/rvv/base/vmsne_vv_mu-1.c | 292 + .../gcc.target/riscv/rvv/base/vmsne_vv_mu-2.c | 292 + .../gcc.target/riscv/rvv/base/vmsne_vv_mu-3.c | 292 + .../gcc.target/riscv/rvv/base/vmsne_vx_m_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vmsne_vx_m_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vmsne_vx_m_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vmsne_vx_m_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vmsne_vx_m_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vmsne_vx_m_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vmsne_vx_mu_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vmsne_vx_mu_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vmsne_vx_mu_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vmsne_vx_mu_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vmsne_vx_mu_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vmsne_vx_mu_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vmsne_vx_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vmsne_vx_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vmsne_vx_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vmsne_vx_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vmsne_vx_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vmsne_vx_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vmul_vv-1.c | 292 + .../gcc.target/riscv/rvv/base/vmul_vv-2.c | 292 + .../gcc.target/riscv/rvv/base/vmul_vv-3.c | 292 + .../gcc.target/riscv/rvv/base/vmul_vv_m-1.c | 292 + .../gcc.target/riscv/rvv/base/vmul_vv_m-2.c | 292 + .../gcc.target/riscv/rvv/base/vmul_vv_m-3.c | 292 + .../gcc.target/riscv/rvv/base/vmul_vv_mu-1.c | 292 + .../gcc.target/riscv/rvv/base/vmul_vv_mu-2.c | 292 + .../gcc.target/riscv/rvv/base/vmul_vv_mu-3.c | 292 + .../gcc.target/riscv/rvv/base/vmul_vv_tu-1.c | 292 + .../gcc.target/riscv/rvv/base/vmul_vv_tu-2.c | 292 + .../gcc.target/riscv/rvv/base/vmul_vv_tu-3.c | 292 + .../gcc.target/riscv/rvv/base/vmul_vv_tum-1.c | 292 + .../gcc.target/riscv/rvv/base/vmul_vv_tum-2.c | 292 + .../gcc.target/riscv/rvv/base/vmul_vv_tum-3.c | 292 + .../gcc.target/riscv/rvv/base/vmul_vv_tumu-1.c | 292 + .../gcc.target/riscv/rvv/base/vmul_vv_tumu-2.c | 292 + .../gcc.target/riscv/rvv/base/vmul_vv_tumu-3.c | 292 + .../gcc.target/riscv/rvv/base/vmul_vx_m_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vmul_vx_m_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vmul_vx_m_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vmul_vx_m_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vmul_vx_m_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vmul_vx_m_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vmul_vx_mu_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vmul_vx_mu_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vmul_vx_mu_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vmul_vx_mu_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vmul_vx_mu_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vmul_vx_mu_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vmul_vx_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vmul_vx_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vmul_vx_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vmul_vx_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vmul_vx_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vmul_vx_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vmul_vx_tu_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vmul_vx_tu_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vmul_vx_tu_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vmul_vx_tu_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vmul_vx_tu_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vmul_vx_tu_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vmul_vx_tum_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vmul_vx_tum_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vmul_vx_tum_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vmul_vx_tum_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vmul_vx_tum_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vmul_vx_tum_rv64-3.c | 292 + .../riscv/rvv/base/vmul_vx_tumu_rv32-1.c | 289 + .../riscv/rvv/base/vmul_vx_tumu_rv32-2.c | 289 + .../riscv/rvv/base/vmul_vx_tumu_rv32-3.c | 289 + .../riscv/rvv/base/vmul_vx_tumu_rv64-1.c | 292 + .../riscv/rvv/base/vmul_vx_tumu_rv64-2.c | 292 + .../riscv/rvv/base/vmul_vx_tumu_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vmulh_vv-1.c | 160 + .../gcc.target/riscv/rvv/base/vmulh_vv-2.c | 160 + .../gcc.target/riscv/rvv/base/vmulh_vv-3.c | 160 + .../gcc.target/riscv/rvv/base/vmulh_vv_m-1.c | 160 + .../gcc.target/riscv/rvv/base/vmulh_vv_m-2.c | 160 + .../gcc.target/riscv/rvv/base/vmulh_vv_m-3.c | 160 + .../gcc.target/riscv/rvv/base/vmulh_vv_mu-1.c | 160 + .../gcc.target/riscv/rvv/base/vmulh_vv_mu-2.c | 160 + .../gcc.target/riscv/rvv/base/vmulh_vv_mu-3.c | 160 + .../gcc.target/riscv/rvv/base/vmulh_vv_tu-1.c | 160 + .../gcc.target/riscv/rvv/base/vmulh_vv_tu-2.c | 160 + .../gcc.target/riscv/rvv/base/vmulh_vv_tu-3.c | 160 + .../gcc.target/riscv/rvv/base/vmulh_vv_tum-1.c | 160 + .../gcc.target/riscv/rvv/base/vmulh_vv_tum-2.c | 160 + .../gcc.target/riscv/rvv/base/vmulh_vv_tum-3.c | 160 + .../gcc.target/riscv/rvv/base/vmulh_vv_tumu-1.c | 160 + .../gcc.target/riscv/rvv/base/vmulh_vv_tumu-2.c | 160 + .../gcc.target/riscv/rvv/base/vmulh_vv_tumu-3.c | 160 + .../gcc.target/riscv/rvv/base/vmulh_vx_m_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vmulh_vx_m_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vmulh_vx_m_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vmulh_vx_m_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vmulh_vx_m_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vmulh_vx_m_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vmulh_vx_mu_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vmulh_vx_mu_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vmulh_vx_mu_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vmulh_vx_mu_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vmulh_vx_mu_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vmulh_vx_mu_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vmulh_vx_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vmulh_vx_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vmulh_vx_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vmulh_vx_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vmulh_vx_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vmulh_vx_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vmulh_vx_tu_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vmulh_vx_tu_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vmulh_vx_tu_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vmulh_vx_tu_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vmulh_vx_tu_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vmulh_vx_tu_rv64-3.c | 160 + .../riscv/rvv/base/vmulh_vx_tum_rv32-1.c | 157 + .../riscv/rvv/base/vmulh_vx_tum_rv32-2.c | 157 + .../riscv/rvv/base/vmulh_vx_tum_rv32-3.c | 157 + .../riscv/rvv/base/vmulh_vx_tum_rv64-1.c | 160 + .../riscv/rvv/base/vmulh_vx_tum_rv64-2.c | 160 + .../riscv/rvv/base/vmulh_vx_tum_rv64-3.c | 160 + .../riscv/rvv/base/vmulh_vx_tumu_rv32-1.c | 157 + .../riscv/rvv/base/vmulh_vx_tumu_rv32-2.c | 157 + .../riscv/rvv/base/vmulh_vx_tumu_rv32-3.c | 157 + .../riscv/rvv/base/vmulh_vx_tumu_rv64-1.c | 160 + .../riscv/rvv/base/vmulh_vx_tumu_rv64-2.c | 160 + .../riscv/rvv/base/vmulh_vx_tumu_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vmulhsu_vv-1.c | 160 + .../gcc.target/riscv/rvv/base/vmulhsu_vv-2.c | 160 + .../gcc.target/riscv/rvv/base/vmulhsu_vv-3.c | 160 + .../gcc.target/riscv/rvv/base/vmulhsu_vv_m-1.c | 160 + .../gcc.target/riscv/rvv/base/vmulhsu_vv_m-2.c | 160 + .../gcc.target/riscv/rvv/base/vmulhsu_vv_m-3.c | 160 + .../gcc.target/riscv/rvv/base/vmulhsu_vv_mu-1.c | 160 + .../gcc.target/riscv/rvv/base/vmulhsu_vv_mu-2.c | 160 + .../gcc.target/riscv/rvv/base/vmulhsu_vv_mu-3.c | 160 + .../gcc.target/riscv/rvv/base/vmulhsu_vv_tu-1.c | 160 + .../gcc.target/riscv/rvv/base/vmulhsu_vv_tu-2.c | 160 + .../gcc.target/riscv/rvv/base/vmulhsu_vv_tu-3.c | 160 + .../gcc.target/riscv/rvv/base/vmulhsu_vv_tum-1.c | 160 + .../gcc.target/riscv/rvv/base/vmulhsu_vv_tum-2.c | 160 + .../gcc.target/riscv/rvv/base/vmulhsu_vv_tum-3.c | 160 + .../gcc.target/riscv/rvv/base/vmulhsu_vv_tumu-1.c | 160 + .../gcc.target/riscv/rvv/base/vmulhsu_vv_tumu-2.c | 160 + .../gcc.target/riscv/rvv/base/vmulhsu_vv_tumu-3.c | 160 + .../riscv/rvv/base/vmulhsu_vx_m_rv32-1.c | 157 + .../riscv/rvv/base/vmulhsu_vx_m_rv32-2.c | 157 + .../riscv/rvv/base/vmulhsu_vx_m_rv32-3.c | 157 + .../riscv/rvv/base/vmulhsu_vx_m_rv64-1.c | 160 + .../riscv/rvv/base/vmulhsu_vx_m_rv64-2.c | 160 + .../riscv/rvv/base/vmulhsu_vx_m_rv64-3.c | 160 + .../riscv/rvv/base/vmulhsu_vx_mu_rv32-1.c | 157 + .../riscv/rvv/base/vmulhsu_vx_mu_rv32-2.c | 157 + .../riscv/rvv/base/vmulhsu_vx_mu_rv32-3.c | 157 + .../riscv/rvv/base/vmulhsu_vx_mu_rv64-1.c | 160 + .../riscv/rvv/base/vmulhsu_vx_mu_rv64-2.c | 160 + .../riscv/rvv/base/vmulhsu_vx_mu_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vmulhsu_vx_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vmulhsu_vx_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vmulhsu_vx_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vmulhsu_vx_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vmulhsu_vx_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vmulhsu_vx_rv64-3.c | 160 + .../riscv/rvv/base/vmulhsu_vx_tu_rv32-1.c | 157 + .../riscv/rvv/base/vmulhsu_vx_tu_rv32-2.c | 157 + .../riscv/rvv/base/vmulhsu_vx_tu_rv32-3.c | 157 + .../riscv/rvv/base/vmulhsu_vx_tu_rv64-1.c | 160 + .../riscv/rvv/base/vmulhsu_vx_tu_rv64-2.c | 160 + .../riscv/rvv/base/vmulhsu_vx_tu_rv64-3.c | 160 + .../riscv/rvv/base/vmulhsu_vx_tum_rv32-1.c | 157 + .../riscv/rvv/base/vmulhsu_vx_tum_rv32-2.c | 157 + .../riscv/rvv/base/vmulhsu_vx_tum_rv32-3.c | 157 + .../riscv/rvv/base/vmulhsu_vx_tum_rv64-1.c | 160 + .../riscv/rvv/base/vmulhsu_vx_tum_rv64-2.c | 160 + .../riscv/rvv/base/vmulhsu_vx_tum_rv64-3.c | 160 + .../riscv/rvv/base/vmulhsu_vx_tumu_rv32-1.c | 157 + .../riscv/rvv/base/vmulhsu_vx_tumu_rv32-2.c | 157 + .../riscv/rvv/base/vmulhsu_vx_tumu_rv32-3.c | 157 + .../riscv/rvv/base/vmulhsu_vx_tumu_rv64-1.c | 160 + .../riscv/rvv/base/vmulhsu_vx_tumu_rv64-2.c | 160 + .../riscv/rvv/base/vmulhsu_vx_tumu_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vmulhu_vv-1.c | 160 + .../gcc.target/riscv/rvv/base/vmulhu_vv-2.c | 160 + .../gcc.target/riscv/rvv/base/vmulhu_vv-3.c | 160 + .../gcc.target/riscv/rvv/base/vmulhu_vv_m-1.c | 160 + .../gcc.target/riscv/rvv/base/vmulhu_vv_m-2.c | 160 + .../gcc.target/riscv/rvv/base/vmulhu_vv_m-3.c | 160 + .../gcc.target/riscv/rvv/base/vmulhu_vv_mu-1.c | 160 + .../gcc.target/riscv/rvv/base/vmulhu_vv_mu-2.c | 160 + .../gcc.target/riscv/rvv/base/vmulhu_vv_mu-3.c | 160 + .../gcc.target/riscv/rvv/base/vmulhu_vv_tu-1.c | 160 + .../gcc.target/riscv/rvv/base/vmulhu_vv_tu-2.c | 160 + .../gcc.target/riscv/rvv/base/vmulhu_vv_tu-3.c | 160 + .../gcc.target/riscv/rvv/base/vmulhu_vv_tum-1.c | 160 + .../gcc.target/riscv/rvv/base/vmulhu_vv_tum-2.c | 160 + .../gcc.target/riscv/rvv/base/vmulhu_vv_tum-3.c | 160 + .../gcc.target/riscv/rvv/base/vmulhu_vv_tumu-1.c | 160 + .../gcc.target/riscv/rvv/base/vmulhu_vv_tumu-2.c | 160 + .../gcc.target/riscv/rvv/base/vmulhu_vv_tumu-3.c | 160 + .../gcc.target/riscv/rvv/base/vmulhu_vx_m_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vmulhu_vx_m_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vmulhu_vx_m_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vmulhu_vx_m_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vmulhu_vx_m_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vmulhu_vx_m_rv64-3.c | 160 + .../riscv/rvv/base/vmulhu_vx_mu_rv32-1.c | 157 + .../riscv/rvv/base/vmulhu_vx_mu_rv32-2.c | 157 + .../riscv/rvv/base/vmulhu_vx_mu_rv32-3.c | 157 + .../riscv/rvv/base/vmulhu_vx_mu_rv64-1.c | 160 + .../riscv/rvv/base/vmulhu_vx_mu_rv64-2.c | 160 + .../riscv/rvv/base/vmulhu_vx_mu_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vmulhu_vx_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vmulhu_vx_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vmulhu_vx_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vmulhu_vx_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vmulhu_vx_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vmulhu_vx_rv64-3.c | 160 + .../riscv/rvv/base/vmulhu_vx_tu_rv32-1.c | 157 + .../riscv/rvv/base/vmulhu_vx_tu_rv32-2.c | 157 + .../riscv/rvv/base/vmulhu_vx_tu_rv32-3.c | 157 + .../riscv/rvv/base/vmulhu_vx_tu_rv64-1.c | 160 + .../riscv/rvv/base/vmulhu_vx_tu_rv64-2.c | 160 + .../riscv/rvv/base/vmulhu_vx_tu_rv64-3.c | 160 + .../riscv/rvv/base/vmulhu_vx_tum_rv32-1.c | 157 + .../riscv/rvv/base/vmulhu_vx_tum_rv32-2.c | 157 + .../riscv/rvv/base/vmulhu_vx_tum_rv32-3.c | 157 + .../riscv/rvv/base/vmulhu_vx_tum_rv64-1.c | 160 + .../riscv/rvv/base/vmulhu_vx_tum_rv64-2.c | 160 + .../riscv/rvv/base/vmulhu_vx_tum_rv64-3.c | 160 + .../riscv/rvv/base/vmulhu_vx_tumu_rv32-1.c | 157 + .../riscv/rvv/base/vmulhu_vx_tumu_rv32-2.c | 157 + .../riscv/rvv/base/vmulhu_vx_tumu_rv32-3.c | 157 + .../riscv/rvv/base/vmulhu_vx_tumu_rv64-1.c | 160 + .../riscv/rvv/base/vmulhu_vx_tumu_rv64-2.c | 160 + .../riscv/rvv/base/vmulhu_vx_tumu_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vmv_v_v-1.c | 276 + .../gcc.target/riscv/rvv/base/vmv_v_v-2.c | 276 + .../gcc.target/riscv/rvv/base/vmv_v_v-3.c | 276 + .../gcc.target/riscv/rvv/base/vmv_v_v_tu-1.c | 276 + .../gcc.target/riscv/rvv/base/vmv_v_v_tu-2.c | 276 + .../gcc.target/riscv/rvv/base/vmv_v_v_tu-3.c | 276 + .../gcc.target/riscv/rvv/base/vmv_v_x_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vmv_v_x_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vmv_v_x_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vmv_v_x_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vmv_v_x_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vmv_v_x_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vmv_v_x_tu_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vmv_v_x_tu_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vmv_v_x_tu_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vmv_v_x_tu_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vmv_v_x_tu_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vmv_v_x_tu_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vnclip_wv-1.c | 111 + .../gcc.target/riscv/rvv/base/vnclip_wv-2.c | 111 + .../gcc.target/riscv/rvv/base/vnclip_wv-3.c | 111 + .../gcc.target/riscv/rvv/base/vnclip_wv_m-1.c | 111 + .../gcc.target/riscv/rvv/base/vnclip_wv_m-2.c | 111 + .../gcc.target/riscv/rvv/base/vnclip_wv_m-3.c | 111 + .../gcc.target/riscv/rvv/base/vnclip_wv_mu-1.c | 111 + .../gcc.target/riscv/rvv/base/vnclip_wv_mu-2.c | 111 + .../gcc.target/riscv/rvv/base/vnclip_wv_mu-3.c | 111 + .../gcc.target/riscv/rvv/base/vnclip_wv_tu-1.c | 111 + .../gcc.target/riscv/rvv/base/vnclip_wv_tu-2.c | 111 + .../gcc.target/riscv/rvv/base/vnclip_wv_tu-3.c | 111 + .../gcc.target/riscv/rvv/base/vnclip_wv_tum-1.c | 111 + .../gcc.target/riscv/rvv/base/vnclip_wv_tum-2.c | 111 + .../gcc.target/riscv/rvv/base/vnclip_wv_tum-3.c | 111 + .../gcc.target/riscv/rvv/base/vnclip_wv_tumu-1.c | 111 + .../gcc.target/riscv/rvv/base/vnclip_wv_tumu-2.c | 111 + .../gcc.target/riscv/rvv/base/vnclip_wv_tumu-3.c | 111 + .../gcc.target/riscv/rvv/base/vnclip_wx-1.c | 111 + .../gcc.target/riscv/rvv/base/vnclip_wx-2.c | 111 + .../gcc.target/riscv/rvv/base/vnclip_wx-3.c | 111 + .../gcc.target/riscv/rvv/base/vnclip_wx_m-1.c | 111 + .../gcc.target/riscv/rvv/base/vnclip_wx_m-2.c | 111 + .../gcc.target/riscv/rvv/base/vnclip_wx_m-3.c | 111 + .../gcc.target/riscv/rvv/base/vnclip_wx_mu-1.c | 111 + .../gcc.target/riscv/rvv/base/vnclip_wx_mu-2.c | 111 + .../gcc.target/riscv/rvv/base/vnclip_wx_mu-3.c | 111 + .../gcc.target/riscv/rvv/base/vnclip_wx_tu-1.c | 111 + .../gcc.target/riscv/rvv/base/vnclip_wx_tu-2.c | 111 + .../gcc.target/riscv/rvv/base/vnclip_wx_tu-3.c | 111 + .../gcc.target/riscv/rvv/base/vnclip_wx_tum-1.c | 111 + .../gcc.target/riscv/rvv/base/vnclip_wx_tum-2.c | 111 + .../gcc.target/riscv/rvv/base/vnclip_wx_tum-3.c | 111 + .../gcc.target/riscv/rvv/base/vnclip_wx_tumu-1.c | 111 + .../gcc.target/riscv/rvv/base/vnclip_wx_tumu-2.c | 111 + .../gcc.target/riscv/rvv/base/vnclip_wx_tumu-3.c | 111 + .../gcc.target/riscv/rvv/base/vnclipu_wv-1.c | 111 + .../gcc.target/riscv/rvv/base/vnclipu_wv-2.c | 111 + .../gcc.target/riscv/rvv/base/vnclipu_wv-3.c | 111 + .../gcc.target/riscv/rvv/base/vnclipu_wv_m-1.c | 111 + .../gcc.target/riscv/rvv/base/vnclipu_wv_m-2.c | 111 + .../gcc.target/riscv/rvv/base/vnclipu_wv_m-3.c | 111 + .../gcc.target/riscv/rvv/base/vnclipu_wv_mu-1.c | 111 + .../gcc.target/riscv/rvv/base/vnclipu_wv_mu-2.c | 111 + .../gcc.target/riscv/rvv/base/vnclipu_wv_mu-3.c | 111 + .../gcc.target/riscv/rvv/base/vnclipu_wv_tu-1.c | 111 + .../gcc.target/riscv/rvv/base/vnclipu_wv_tu-2.c | 111 + .../gcc.target/riscv/rvv/base/vnclipu_wv_tu-3.c | 111 + .../gcc.target/riscv/rvv/base/vnclipu_wv_tum-1.c | 111 + .../gcc.target/riscv/rvv/base/vnclipu_wv_tum-2.c | 111 + .../gcc.target/riscv/rvv/base/vnclipu_wv_tum-3.c | 111 + .../gcc.target/riscv/rvv/base/vnclipu_wv_tumu-1.c | 111 + .../gcc.target/riscv/rvv/base/vnclipu_wv_tumu-2.c | 111 + .../gcc.target/riscv/rvv/base/vnclipu_wv_tumu-3.c | 111 + .../gcc.target/riscv/rvv/base/vnclipu_wx-1.c | 111 + .../gcc.target/riscv/rvv/base/vnclipu_wx-2.c | 111 + .../gcc.target/riscv/rvv/base/vnclipu_wx-3.c | 111 + .../gcc.target/riscv/rvv/base/vnclipu_wx_m-1.c | 111 + .../gcc.target/riscv/rvv/base/vnclipu_wx_m-2.c | 111 + .../gcc.target/riscv/rvv/base/vnclipu_wx_m-3.c | 111 + .../gcc.target/riscv/rvv/base/vnclipu_wx_mu-1.c | 111 + .../gcc.target/riscv/rvv/base/vnclipu_wx_mu-2.c | 111 + .../gcc.target/riscv/rvv/base/vnclipu_wx_mu-3.c | 111 + .../gcc.target/riscv/rvv/base/vnclipu_wx_tu-1.c | 111 + .../gcc.target/riscv/rvv/base/vnclipu_wx_tu-2.c | 111 + .../gcc.target/riscv/rvv/base/vnclipu_wx_tu-3.c | 111 + .../gcc.target/riscv/rvv/base/vnclipu_wx_tum-1.c | 111 + .../gcc.target/riscv/rvv/base/vnclipu_wx_tum-2.c | 111 + .../gcc.target/riscv/rvv/base/vnclipu_wx_tum-3.c | 111 + .../gcc.target/riscv/rvv/base/vnclipu_wx_tumu-1.c | 111 + .../gcc.target/riscv/rvv/base/vnclipu_wx_tumu-2.c | 111 + .../gcc.target/riscv/rvv/base/vnclipu_wx_tumu-3.c | 111 + .../gcc.target/riscv/rvv/base/vncvt_x-1.c | 201 + .../gcc.target/riscv/rvv/base/vncvt_x-2.c | 201 + .../gcc.target/riscv/rvv/base/vncvt_x-3.c | 201 + .../gcc.target/riscv/rvv/base/vncvt_x_m-1.c | 201 + .../gcc.target/riscv/rvv/base/vncvt_x_m-2.c | 201 + .../gcc.target/riscv/rvv/base/vncvt_x_m-3.c | 201 + .../gcc.target/riscv/rvv/base/vncvt_x_mu-1.c | 201 + .../gcc.target/riscv/rvv/base/vncvt_x_mu-2.c | 201 + .../gcc.target/riscv/rvv/base/vncvt_x_mu-3.c | 201 + .../gcc.target/riscv/rvv/base/vncvt_x_tu-1.c | 201 + .../gcc.target/riscv/rvv/base/vncvt_x_tu-2.c | 201 + .../gcc.target/riscv/rvv/base/vncvt_x_tu-3.c | 201 + .../gcc.target/riscv/rvv/base/vncvt_x_tum-1.c | 201 + .../gcc.target/riscv/rvv/base/vncvt_x_tum-2.c | 201 + .../gcc.target/riscv/rvv/base/vncvt_x_tum-3.c | 201 + .../gcc.target/riscv/rvv/base/vncvt_x_tumu-1.c | 201 + .../gcc.target/riscv/rvv/base/vncvt_x_tumu-2.c | 201 + .../gcc.target/riscv/rvv/base/vncvt_x_tumu-3.c | 201 + gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v-1.c | 160 + gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v-2.c | 160 + gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v-3.c | 160 + .../gcc.target/riscv/rvv/base/vneg_v_m-1.c | 160 + .../gcc.target/riscv/rvv/base/vneg_v_m-2.c | 160 + .../gcc.target/riscv/rvv/base/vneg_v_m-3.c | 160 + .../gcc.target/riscv/rvv/base/vneg_v_mu-1.c | 160 + .../gcc.target/riscv/rvv/base/vneg_v_mu-2.c | 160 + .../gcc.target/riscv/rvv/base/vneg_v_mu-3.c | 160 + .../gcc.target/riscv/rvv/base/vneg_v_tu-1.c | 160 + .../gcc.target/riscv/rvv/base/vneg_v_tu-2.c | 160 + .../gcc.target/riscv/rvv/base/vneg_v_tu-3.c | 160 + .../gcc.target/riscv/rvv/base/vneg_v_tum-1.c | 160 + .../gcc.target/riscv/rvv/base/vneg_v_tum-2.c | 160 + .../gcc.target/riscv/rvv/base/vneg_v_tum-3.c | 160 + .../gcc.target/riscv/rvv/base/vneg_v_tumu-1.c | 160 + .../gcc.target/riscv/rvv/base/vneg_v_tumu-2.c | 160 + .../gcc.target/riscv/rvv/base/vneg_v_tumu-3.c | 160 + .../gcc.target/riscv/rvv/base/vnmsac_vv-1.c | 292 + .../gcc.target/riscv/rvv/base/vnmsac_vv-2.c | 292 + .../gcc.target/riscv/rvv/base/vnmsac_vv-3.c | 292 + .../gcc.target/riscv/rvv/base/vnmsac_vv_m-1.c | 292 + .../gcc.target/riscv/rvv/base/vnmsac_vv_m-2.c | 292 + .../gcc.target/riscv/rvv/base/vnmsac_vv_m-3.c | 292 + .../gcc.target/riscv/rvv/base/vnmsac_vv_mu-1.c | 292 + .../gcc.target/riscv/rvv/base/vnmsac_vv_mu-2.c | 292 + .../gcc.target/riscv/rvv/base/vnmsac_vv_mu-3.c | 292 + .../gcc.target/riscv/rvv/base/vnmsac_vv_tu-1.c | 292 + .../gcc.target/riscv/rvv/base/vnmsac_vv_tu-2.c | 292 + .../gcc.target/riscv/rvv/base/vnmsac_vv_tu-3.c | 292 + .../gcc.target/riscv/rvv/base/vnmsac_vv_tum-1.c | 292 + .../gcc.target/riscv/rvv/base/vnmsac_vv_tum-2.c | 292 + .../gcc.target/riscv/rvv/base/vnmsac_vv_tum-3.c | 292 + .../gcc.target/riscv/rvv/base/vnmsac_vv_tumu-1.c | 292 + .../gcc.target/riscv/rvv/base/vnmsac_vv_tumu-2.c | 292 + .../gcc.target/riscv/rvv/base/vnmsac_vv_tumu-3.c | 292 + .../gcc.target/riscv/rvv/base/vnmsac_vx_m_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vnmsac_vx_m_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vnmsac_vx_m_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vnmsac_vx_m_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vnmsac_vx_m_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vnmsac_vx_m_rv64-3.c | 292 + .../riscv/rvv/base/vnmsac_vx_mu_rv32-1.c | 289 + .../riscv/rvv/base/vnmsac_vx_mu_rv32-2.c | 289 + .../riscv/rvv/base/vnmsac_vx_mu_rv32-3.c | 289 + .../riscv/rvv/base/vnmsac_vx_mu_rv64-1.c | 292 + .../riscv/rvv/base/vnmsac_vx_mu_rv64-2.c | 292 + .../riscv/rvv/base/vnmsac_vx_mu_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vnmsac_vx_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vnmsac_vx_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vnmsac_vx_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vnmsac_vx_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vnmsac_vx_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vnmsac_vx_rv64-3.c | 292 + .../riscv/rvv/base/vnmsac_vx_tu_rv32-1.c | 289 + .../riscv/rvv/base/vnmsac_vx_tu_rv32-2.c | 289 + .../riscv/rvv/base/vnmsac_vx_tu_rv32-3.c | 289 + .../riscv/rvv/base/vnmsac_vx_tu_rv64-1.c | 292 + .../riscv/rvv/base/vnmsac_vx_tu_rv64-2.c | 292 + .../riscv/rvv/base/vnmsac_vx_tu_rv64-3.c | 292 + .../riscv/rvv/base/vnmsac_vx_tum_rv32-1.c | 289 + .../riscv/rvv/base/vnmsac_vx_tum_rv32-2.c | 289 + .../riscv/rvv/base/vnmsac_vx_tum_rv32-3.c | 289 + .../riscv/rvv/base/vnmsac_vx_tum_rv64-1.c | 292 + .../riscv/rvv/base/vnmsac_vx_tum_rv64-2.c | 292 + .../riscv/rvv/base/vnmsac_vx_tum_rv64-3.c | 292 + .../riscv/rvv/base/vnmsac_vx_tumu_rv32-1.c | 289 + .../riscv/rvv/base/vnmsac_vx_tumu_rv32-2.c | 289 + .../riscv/rvv/base/vnmsac_vx_tumu_rv32-3.c | 289 + .../riscv/rvv/base/vnmsac_vx_tumu_rv64-1.c | 292 + .../riscv/rvv/base/vnmsac_vx_tumu_rv64-2.c | 292 + .../riscv/rvv/base/vnmsac_vx_tumu_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vnmsub_vv-1.c | 292 + .../gcc.target/riscv/rvv/base/vnmsub_vv-2.c | 292 + .../gcc.target/riscv/rvv/base/vnmsub_vv-3.c | 292 + .../gcc.target/riscv/rvv/base/vnmsub_vv_m-1.c | 292 + .../gcc.target/riscv/rvv/base/vnmsub_vv_m-2.c | 292 + .../gcc.target/riscv/rvv/base/vnmsub_vv_m-3.c | 292 + .../gcc.target/riscv/rvv/base/vnmsub_vv_mu-1.c | 292 + .../gcc.target/riscv/rvv/base/vnmsub_vv_mu-2.c | 292 + .../gcc.target/riscv/rvv/base/vnmsub_vv_mu-3.c | 292 + .../gcc.target/riscv/rvv/base/vnmsub_vv_tu-1.c | 292 + .../gcc.target/riscv/rvv/base/vnmsub_vv_tu-2.c | 292 + .../gcc.target/riscv/rvv/base/vnmsub_vv_tu-3.c | 292 + .../gcc.target/riscv/rvv/base/vnmsub_vv_tum-1.c | 292 + .../gcc.target/riscv/rvv/base/vnmsub_vv_tum-2.c | 292 + .../gcc.target/riscv/rvv/base/vnmsub_vv_tum-3.c | 292 + .../gcc.target/riscv/rvv/base/vnmsub_vv_tumu-1.c | 292 + .../gcc.target/riscv/rvv/base/vnmsub_vv_tumu-2.c | 292 + .../gcc.target/riscv/rvv/base/vnmsub_vv_tumu-3.c | 292 + .../gcc.target/riscv/rvv/base/vnmsub_vx_m_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vnmsub_vx_m_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vnmsub_vx_m_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vnmsub_vx_m_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vnmsub_vx_m_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vnmsub_vx_m_rv64-3.c | 292 + .../riscv/rvv/base/vnmsub_vx_mu_rv32-1.c | 289 + .../riscv/rvv/base/vnmsub_vx_mu_rv32-2.c | 289 + .../riscv/rvv/base/vnmsub_vx_mu_rv32-3.c | 289 + .../riscv/rvv/base/vnmsub_vx_mu_rv64-1.c | 292 + .../riscv/rvv/base/vnmsub_vx_mu_rv64-2.c | 292 + .../riscv/rvv/base/vnmsub_vx_mu_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vnmsub_vx_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vnmsub_vx_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vnmsub_vx_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vnmsub_vx_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vnmsub_vx_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vnmsub_vx_rv64-3.c | 292 + .../riscv/rvv/base/vnmsub_vx_tu_rv32-1.c | 289 + .../riscv/rvv/base/vnmsub_vx_tu_rv32-2.c | 289 + .../riscv/rvv/base/vnmsub_vx_tu_rv32-3.c | 289 + .../riscv/rvv/base/vnmsub_vx_tu_rv64-1.c | 292 + .../riscv/rvv/base/vnmsub_vx_tu_rv64-2.c | 292 + .../riscv/rvv/base/vnmsub_vx_tu_rv64-3.c | 292 + .../riscv/rvv/base/vnmsub_vx_tum_rv32-1.c | 289 + .../riscv/rvv/base/vnmsub_vx_tum_rv32-2.c | 289 + .../riscv/rvv/base/vnmsub_vx_tum_rv32-3.c | 289 + .../riscv/rvv/base/vnmsub_vx_tum_rv64-1.c | 292 + .../riscv/rvv/base/vnmsub_vx_tum_rv64-2.c | 292 + .../riscv/rvv/base/vnmsub_vx_tum_rv64-3.c | 292 + .../riscv/rvv/base/vnmsub_vx_tumu_rv32-1.c | 289 + .../riscv/rvv/base/vnmsub_vx_tumu_rv32-2.c | 289 + .../riscv/rvv/base/vnmsub_vx_tumu_rv32-3.c | 289 + .../riscv/rvv/base/vnmsub_vx_tumu_rv64-1.c | 292 + .../riscv/rvv/base/vnmsub_vx_tumu_rv64-2.c | 292 + .../riscv/rvv/base/vnmsub_vx_tumu_rv64-3.c | 292 + gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v-1.c | 160 + gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v-2.c | 160 + gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v-3.c | 160 + .../gcc.target/riscv/rvv/base/vnot_v_m-1.c | 160 + .../gcc.target/riscv/rvv/base/vnot_v_m-2.c | 160 + .../gcc.target/riscv/rvv/base/vnot_v_m-3.c | 160 + .../gcc.target/riscv/rvv/base/vnot_v_mu-1.c | 160 + .../gcc.target/riscv/rvv/base/vnot_v_mu-2.c | 160 + .../gcc.target/riscv/rvv/base/vnot_v_mu-3.c | 160 + .../gcc.target/riscv/rvv/base/vnot_v_tu-1.c | 160 + .../gcc.target/riscv/rvv/base/vnot_v_tu-2.c | 160 + .../gcc.target/riscv/rvv/base/vnot_v_tu-3.c | 160 + .../gcc.target/riscv/rvv/base/vnot_v_tum-1.c | 160 + .../gcc.target/riscv/rvv/base/vnot_v_tum-2.c | 160 + .../gcc.target/riscv/rvv/base/vnot_v_tum-3.c | 160 + .../gcc.target/riscv/rvv/base/vnot_v_tumu-1.c | 160 + .../gcc.target/riscv/rvv/base/vnot_v_tumu-2.c | 160 + .../gcc.target/riscv/rvv/base/vnot_v_tumu-3.c | 160 + .../gcc.target/riscv/rvv/base/vnsra_wv-1.c | 111 + .../gcc.target/riscv/rvv/base/vnsra_wv-2.c | 111 + .../gcc.target/riscv/rvv/base/vnsra_wv-3.c | 111 + .../gcc.target/riscv/rvv/base/vnsra_wv_m-1.c | 111 + .../gcc.target/riscv/rvv/base/vnsra_wv_m-2.c | 111 + .../gcc.target/riscv/rvv/base/vnsra_wv_m-3.c | 111 + .../gcc.target/riscv/rvv/base/vnsra_wv_mu-1.c | 111 + .../gcc.target/riscv/rvv/base/vnsra_wv_mu-2.c | 111 + .../gcc.target/riscv/rvv/base/vnsra_wv_mu-3.c | 111 + .../gcc.target/riscv/rvv/base/vnsra_wv_tu-1.c | 111 + .../gcc.target/riscv/rvv/base/vnsra_wv_tu-2.c | 111 + .../gcc.target/riscv/rvv/base/vnsra_wv_tu-3.c | 111 + .../gcc.target/riscv/rvv/base/vnsra_wv_tum-1.c | 111 + .../gcc.target/riscv/rvv/base/vnsra_wv_tum-2.c | 111 + .../gcc.target/riscv/rvv/base/vnsra_wv_tum-3.c | 111 + .../gcc.target/riscv/rvv/base/vnsra_wv_tumu-1.c | 111 + .../gcc.target/riscv/rvv/base/vnsra_wv_tumu-2.c | 111 + .../gcc.target/riscv/rvv/base/vnsra_wv_tumu-3.c | 111 + .../gcc.target/riscv/rvv/base/vnsra_wx-1.c | 111 + .../gcc.target/riscv/rvv/base/vnsra_wx-2.c | 111 + .../gcc.target/riscv/rvv/base/vnsra_wx-3.c | 111 + .../gcc.target/riscv/rvv/base/vnsra_wx_m-1.c | 111 + .../gcc.target/riscv/rvv/base/vnsra_wx_m-2.c | 111 + .../gcc.target/riscv/rvv/base/vnsra_wx_m-3.c | 111 + .../gcc.target/riscv/rvv/base/vnsra_wx_mu-1.c | 111 + .../gcc.target/riscv/rvv/base/vnsra_wx_mu-2.c | 111 + .../gcc.target/riscv/rvv/base/vnsra_wx_mu-3.c | 111 + .../gcc.target/riscv/rvv/base/vnsra_wx_tu-1.c | 111 + .../gcc.target/riscv/rvv/base/vnsra_wx_tu-2.c | 111 + .../gcc.target/riscv/rvv/base/vnsra_wx_tu-3.c | 111 + .../gcc.target/riscv/rvv/base/vnsra_wx_tum-1.c | 111 + .../gcc.target/riscv/rvv/base/vnsra_wx_tum-2.c | 111 + .../gcc.target/riscv/rvv/base/vnsra_wx_tum-3.c | 111 + .../gcc.target/riscv/rvv/base/vnsra_wx_tumu-1.c | 111 + .../gcc.target/riscv/rvv/base/vnsra_wx_tumu-2.c | 111 + .../gcc.target/riscv/rvv/base/vnsra_wx_tumu-3.c | 111 + .../gcc.target/riscv/rvv/base/vnsrl_wv-1.c | 111 + .../gcc.target/riscv/rvv/base/vnsrl_wv-2.c | 111 + .../gcc.target/riscv/rvv/base/vnsrl_wv-3.c | 111 + .../gcc.target/riscv/rvv/base/vnsrl_wv_m-1.c | 111 + .../gcc.target/riscv/rvv/base/vnsrl_wv_m-2.c | 111 + .../gcc.target/riscv/rvv/base/vnsrl_wv_m-3.c | 111 + .../gcc.target/riscv/rvv/base/vnsrl_wv_mu-1.c | 111 + .../gcc.target/riscv/rvv/base/vnsrl_wv_mu-2.c | 111 + .../gcc.target/riscv/rvv/base/vnsrl_wv_mu-3.c | 111 + .../gcc.target/riscv/rvv/base/vnsrl_wv_tu-1.c | 111 + .../gcc.target/riscv/rvv/base/vnsrl_wv_tu-2.c | 111 + .../gcc.target/riscv/rvv/base/vnsrl_wv_tu-3.c | 111 + .../gcc.target/riscv/rvv/base/vnsrl_wv_tum-1.c | 111 + .../gcc.target/riscv/rvv/base/vnsrl_wv_tum-2.c | 111 + .../gcc.target/riscv/rvv/base/vnsrl_wv_tum-3.c | 111 + .../gcc.target/riscv/rvv/base/vnsrl_wv_tumu-1.c | 111 + .../gcc.target/riscv/rvv/base/vnsrl_wv_tumu-2.c | 111 + .../gcc.target/riscv/rvv/base/vnsrl_wv_tumu-3.c | 111 + .../gcc.target/riscv/rvv/base/vnsrl_wx-1.c | 111 + .../gcc.target/riscv/rvv/base/vnsrl_wx-2.c | 111 + .../gcc.target/riscv/rvv/base/vnsrl_wx-3.c | 111 + .../gcc.target/riscv/rvv/base/vnsrl_wx_m-1.c | 111 + .../gcc.target/riscv/rvv/base/vnsrl_wx_m-2.c | 111 + .../gcc.target/riscv/rvv/base/vnsrl_wx_m-3.c | 111 + .../gcc.target/riscv/rvv/base/vnsrl_wx_mu-1.c | 111 + .../gcc.target/riscv/rvv/base/vnsrl_wx_mu-2.c | 111 + .../gcc.target/riscv/rvv/base/vnsrl_wx_mu-3.c | 111 + .../gcc.target/riscv/rvv/base/vnsrl_wx_tu-1.c | 111 + .../gcc.target/riscv/rvv/base/vnsrl_wx_tu-2.c | 111 + .../gcc.target/riscv/rvv/base/vnsrl_wx_tu-3.c | 111 + .../gcc.target/riscv/rvv/base/vnsrl_wx_tum-1.c | 111 + .../gcc.target/riscv/rvv/base/vnsrl_wx_tum-2.c | 111 + .../gcc.target/riscv/rvv/base/vnsrl_wx_tum-3.c | 111 + .../gcc.target/riscv/rvv/base/vnsrl_wx_tumu-1.c | 111 + .../gcc.target/riscv/rvv/base/vnsrl_wx_tumu-2.c | 111 + .../gcc.target/riscv/rvv/base/vnsrl_wx_tumu-3.c | 111 + gcc/testsuite/gcc.target/riscv/rvv/base/vor_vv-1.c | 292 + gcc/testsuite/gcc.target/riscv/rvv/base/vor_vv-2.c | 292 + gcc/testsuite/gcc.target/riscv/rvv/base/vor_vv-3.c | 292 + .../gcc.target/riscv/rvv/base/vor_vv_m-1.c | 292 + .../gcc.target/riscv/rvv/base/vor_vv_m-2.c | 292 + .../gcc.target/riscv/rvv/base/vor_vv_m-3.c | 292 + .../gcc.target/riscv/rvv/base/vor_vv_mu-1.c | 292 + .../gcc.target/riscv/rvv/base/vor_vv_mu-2.c | 292 + .../gcc.target/riscv/rvv/base/vor_vv_mu-3.c | 292 + .../gcc.target/riscv/rvv/base/vor_vv_tu-1.c | 292 + .../gcc.target/riscv/rvv/base/vor_vv_tu-2.c | 292 + .../gcc.target/riscv/rvv/base/vor_vv_tu-3.c | 292 + .../gcc.target/riscv/rvv/base/vor_vv_tum-1.c | 292 + .../gcc.target/riscv/rvv/base/vor_vv_tum-2.c | 292 + .../gcc.target/riscv/rvv/base/vor_vv_tum-3.c | 292 + .../gcc.target/riscv/rvv/base/vor_vv_tumu-1.c | 292 + .../gcc.target/riscv/rvv/base/vor_vv_tumu-2.c | 292 + .../gcc.target/riscv/rvv/base/vor_vv_tumu-3.c | 292 + .../gcc.target/riscv/rvv/base/vor_vx_m_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vor_vx_m_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vor_vx_m_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vor_vx_m_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vor_vx_m_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vor_vx_m_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vor_vx_mu_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vor_vx_mu_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vor_vx_mu_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vor_vx_mu_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vor_vx_mu_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vor_vx_mu_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vor_vx_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vor_vx_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vor_vx_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vor_vx_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vor_vx_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vor_vx_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vor_vx_tu_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vor_vx_tu_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vor_vx_tu_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vor_vx_tu_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vor_vx_tu_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vor_vx_tu_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vor_vx_tum_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vor_vx_tum_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vor_vx_tum_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vor_vx_tum_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vor_vx_tum_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vor_vx_tum_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vor_vx_tumu_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vor_vx_tumu_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vor_vx_tumu_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vor_vx_tumu_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vor_vx_tumu_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vor_vx_tumu_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vrem_vv-1.c | 160 + .../gcc.target/riscv/rvv/base/vrem_vv-2.c | 160 + .../gcc.target/riscv/rvv/base/vrem_vv-3.c | 160 + .../gcc.target/riscv/rvv/base/vrem_vv_m-1.c | 160 + .../gcc.target/riscv/rvv/base/vrem_vv_m-2.c | 160 + .../gcc.target/riscv/rvv/base/vrem_vv_m-3.c | 160 + .../gcc.target/riscv/rvv/base/vrem_vv_mu-1.c | 160 + .../gcc.target/riscv/rvv/base/vrem_vv_mu-2.c | 160 + .../gcc.target/riscv/rvv/base/vrem_vv_mu-3.c | 160 + .../gcc.target/riscv/rvv/base/vrem_vv_tu-1.c | 160 + .../gcc.target/riscv/rvv/base/vrem_vv_tu-2.c | 160 + .../gcc.target/riscv/rvv/base/vrem_vv_tu-3.c | 160 + .../gcc.target/riscv/rvv/base/vrem_vv_tum-1.c | 160 + .../gcc.target/riscv/rvv/base/vrem_vv_tum-2.c | 160 + .../gcc.target/riscv/rvv/base/vrem_vv_tum-3.c | 160 + .../gcc.target/riscv/rvv/base/vrem_vv_tumu-1.c | 160 + .../gcc.target/riscv/rvv/base/vrem_vv_tumu-2.c | 160 + .../gcc.target/riscv/rvv/base/vrem_vv_tumu-3.c | 160 + .../gcc.target/riscv/rvv/base/vrem_vx_m_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vrem_vx_m_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vrem_vx_m_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vrem_vx_m_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vrem_vx_m_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vrem_vx_m_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vrem_vx_mu_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vrem_vx_mu_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vrem_vx_mu_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vrem_vx_mu_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vrem_vx_mu_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vrem_vx_mu_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vrem_vx_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vrem_vx_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vrem_vx_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vrem_vx_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vrem_vx_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vrem_vx_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vrem_vx_tu_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vrem_vx_tu_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vrem_vx_tu_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vrem_vx_tu_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vrem_vx_tu_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vrem_vx_tu_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vrem_vx_tum_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vrem_vx_tum_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vrem_vx_tum_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vrem_vx_tum_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vrem_vx_tum_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vrem_vx_tum_rv64-3.c | 160 + .../riscv/rvv/base/vrem_vx_tumu_rv32-1.c | 157 + .../riscv/rvv/base/vrem_vx_tumu_rv32-2.c | 157 + .../riscv/rvv/base/vrem_vx_tumu_rv32-3.c | 157 + .../riscv/rvv/base/vrem_vx_tumu_rv64-1.c | 160 + .../riscv/rvv/base/vrem_vx_tumu_rv64-2.c | 160 + .../riscv/rvv/base/vrem_vx_tumu_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vremu_vv-1.c | 160 + .../gcc.target/riscv/rvv/base/vremu_vv-2.c | 160 + .../gcc.target/riscv/rvv/base/vremu_vv-3.c | 160 + .../gcc.target/riscv/rvv/base/vremu_vv_m-1.c | 160 + .../gcc.target/riscv/rvv/base/vremu_vv_m-2.c | 160 + .../gcc.target/riscv/rvv/base/vremu_vv_m-3.c | 160 + .../gcc.target/riscv/rvv/base/vremu_vv_mu-1.c | 160 + .../gcc.target/riscv/rvv/base/vremu_vv_mu-2.c | 160 + .../gcc.target/riscv/rvv/base/vremu_vv_mu-3.c | 160 + .../gcc.target/riscv/rvv/base/vremu_vv_tu-1.c | 160 + .../gcc.target/riscv/rvv/base/vremu_vv_tu-2.c | 160 + .../gcc.target/riscv/rvv/base/vremu_vv_tu-3.c | 160 + .../gcc.target/riscv/rvv/base/vremu_vv_tum-1.c | 160 + .../gcc.target/riscv/rvv/base/vremu_vv_tum-2.c | 160 + .../gcc.target/riscv/rvv/base/vremu_vv_tum-3.c | 160 + .../gcc.target/riscv/rvv/base/vremu_vv_tumu-1.c | 160 + .../gcc.target/riscv/rvv/base/vremu_vv_tumu-2.c | 160 + .../gcc.target/riscv/rvv/base/vremu_vv_tumu-3.c | 160 + .../gcc.target/riscv/rvv/base/vremu_vx_m_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vremu_vx_m_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vremu_vx_m_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vremu_vx_m_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vremu_vx_m_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vremu_vx_m_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vremu_vx_mu_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vremu_vx_mu_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vremu_vx_mu_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vremu_vx_mu_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vremu_vx_mu_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vremu_vx_mu_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vremu_vx_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vremu_vx_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vremu_vx_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vremu_vx_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vremu_vx_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vremu_vx_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vremu_vx_tu_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vremu_vx_tu_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vremu_vx_tu_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vremu_vx_tu_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vremu_vx_tu_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vremu_vx_tu_rv64-3.c | 160 + .../riscv/rvv/base/vremu_vx_tum_rv32-1.c | 157 + .../riscv/rvv/base/vremu_vx_tum_rv32-2.c | 157 + .../riscv/rvv/base/vremu_vx_tum_rv32-3.c | 157 + .../riscv/rvv/base/vremu_vx_tum_rv64-1.c | 160 + .../riscv/rvv/base/vremu_vx_tum_rv64-2.c | 160 + .../riscv/rvv/base/vremu_vx_tum_rv64-3.c | 160 + .../riscv/rvv/base/vremu_vx_tumu_rv32-1.c | 157 + .../riscv/rvv/base/vremu_vx_tumu_rv32-2.c | 157 + .../riscv/rvv/base/vremu_vx_tumu_rv32-3.c | 157 + .../riscv/rvv/base/vremu_vx_tumu_rv64-1.c | 160 + .../riscv/rvv/base/vremu_vx_tumu_rv64-2.c | 160 + .../riscv/rvv/base/vremu_vx_tumu_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vrsub_vx_m_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vrsub_vx_m_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vrsub_vx_m_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vrsub_vx_m_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vrsub_vx_m_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vrsub_vx_m_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vrsub_vx_mu_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vrsub_vx_mu_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vrsub_vx_mu_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vrsub_vx_mu_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vrsub_vx_mu_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vrsub_vx_mu_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vrsub_vx_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vrsub_vx_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vrsub_vx_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vrsub_vx_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vrsub_vx_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vrsub_vx_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vrsub_vx_tu_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vrsub_vx_tu_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vrsub_vx_tu_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vrsub_vx_tu_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vrsub_vx_tu_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vrsub_vx_tu_rv64-3.c | 292 + .../riscv/rvv/base/vrsub_vx_tum_rv32-1.c | 289 + .../riscv/rvv/base/vrsub_vx_tum_rv32-2.c | 289 + .../riscv/rvv/base/vrsub_vx_tum_rv32-3.c | 289 + .../riscv/rvv/base/vrsub_vx_tum_rv64-1.c | 292 + .../riscv/rvv/base/vrsub_vx_tum_rv64-2.c | 292 + .../riscv/rvv/base/vrsub_vx_tum_rv64-3.c | 292 + .../riscv/rvv/base/vrsub_vx_tumu_rv32-1.c | 289 + .../riscv/rvv/base/vrsub_vx_tumu_rv32-2.c | 289 + .../riscv/rvv/base/vrsub_vx_tumu_rv32-3.c | 289 + .../riscv/rvv/base/vrsub_vx_tumu_rv64-1.c | 292 + .../riscv/rvv/base/vrsub_vx_tumu_rv64-2.c | 292 + .../riscv/rvv/base/vrsub_vx_tumu_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vsadd_vv-1.c | 160 + .../gcc.target/riscv/rvv/base/vsadd_vv-2.c | 160 + .../gcc.target/riscv/rvv/base/vsadd_vv-3.c | 160 + .../gcc.target/riscv/rvv/base/vsadd_vv_m-1.c | 160 + .../gcc.target/riscv/rvv/base/vsadd_vv_m-2.c | 160 + .../gcc.target/riscv/rvv/base/vsadd_vv_m-3.c | 160 + .../gcc.target/riscv/rvv/base/vsadd_vv_mu-1.c | 160 + .../gcc.target/riscv/rvv/base/vsadd_vv_mu-2.c | 160 + .../gcc.target/riscv/rvv/base/vsadd_vv_mu-3.c | 160 + .../gcc.target/riscv/rvv/base/vsadd_vv_tu-1.c | 160 + .../gcc.target/riscv/rvv/base/vsadd_vv_tu-2.c | 160 + .../gcc.target/riscv/rvv/base/vsadd_vv_tu-3.c | 160 + .../gcc.target/riscv/rvv/base/vsadd_vv_tum-1.c | 160 + .../gcc.target/riscv/rvv/base/vsadd_vv_tum-2.c | 160 + .../gcc.target/riscv/rvv/base/vsadd_vv_tum-3.c | 160 + .../gcc.target/riscv/rvv/base/vsadd_vv_tumu-1.c | 160 + .../gcc.target/riscv/rvv/base/vsadd_vv_tumu-2.c | 160 + .../gcc.target/riscv/rvv/base/vsadd_vv_tumu-3.c | 160 + .../gcc.target/riscv/rvv/base/vsadd_vx_m_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vsadd_vx_m_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vsadd_vx_m_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vsadd_vx_m_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vsadd_vx_m_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vsadd_vx_m_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vsadd_vx_mu_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vsadd_vx_mu_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vsadd_vx_mu_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vsadd_vx_mu_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vsadd_vx_mu_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vsadd_vx_mu_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vsadd_vx_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vsadd_vx_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vsadd_vx_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vsadd_vx_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vsadd_vx_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vsadd_vx_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vsadd_vx_tu_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vsadd_vx_tu_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vsadd_vx_tu_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vsadd_vx_tu_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vsadd_vx_tu_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vsadd_vx_tu_rv64-3.c | 160 + .../riscv/rvv/base/vsadd_vx_tum_rv32-1.c | 157 + .../riscv/rvv/base/vsadd_vx_tum_rv32-2.c | 157 + .../riscv/rvv/base/vsadd_vx_tum_rv32-3.c | 157 + .../riscv/rvv/base/vsadd_vx_tum_rv64-1.c | 160 + .../riscv/rvv/base/vsadd_vx_tum_rv64-2.c | 160 + .../riscv/rvv/base/vsadd_vx_tum_rv64-3.c | 160 + .../riscv/rvv/base/vsadd_vx_tumu_rv32-1.c | 157 + .../riscv/rvv/base/vsadd_vx_tumu_rv32-2.c | 157 + .../riscv/rvv/base/vsadd_vx_tumu_rv32-3.c | 157 + .../riscv/rvv/base/vsadd_vx_tumu_rv64-1.c | 160 + .../riscv/rvv/base/vsadd_vx_tumu_rv64-2.c | 160 + .../riscv/rvv/base/vsadd_vx_tumu_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vsaddu_vv-1.c | 160 + .../gcc.target/riscv/rvv/base/vsaddu_vv-2.c | 160 + .../gcc.target/riscv/rvv/base/vsaddu_vv-3.c | 160 + .../gcc.target/riscv/rvv/base/vsaddu_vv_m-1.c | 160 + .../gcc.target/riscv/rvv/base/vsaddu_vv_m-2.c | 160 + .../gcc.target/riscv/rvv/base/vsaddu_vv_m-3.c | 160 + .../gcc.target/riscv/rvv/base/vsaddu_vv_mu-1.c | 160 + .../gcc.target/riscv/rvv/base/vsaddu_vv_mu-2.c | 160 + .../gcc.target/riscv/rvv/base/vsaddu_vv_mu-3.c | 160 + .../gcc.target/riscv/rvv/base/vsaddu_vv_tu-1.c | 160 + .../gcc.target/riscv/rvv/base/vsaddu_vv_tu-2.c | 160 + .../gcc.target/riscv/rvv/base/vsaddu_vv_tu-3.c | 160 + .../gcc.target/riscv/rvv/base/vsaddu_vv_tum-1.c | 160 + .../gcc.target/riscv/rvv/base/vsaddu_vv_tum-2.c | 160 + .../gcc.target/riscv/rvv/base/vsaddu_vv_tum-3.c | 160 + .../gcc.target/riscv/rvv/base/vsaddu_vv_tumu-1.c | 160 + .../gcc.target/riscv/rvv/base/vsaddu_vv_tumu-2.c | 160 + .../gcc.target/riscv/rvv/base/vsaddu_vv_tumu-3.c | 160 + .../gcc.target/riscv/rvv/base/vsaddu_vx_m_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vsaddu_vx_m_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vsaddu_vx_m_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vsaddu_vx_m_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vsaddu_vx_m_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vsaddu_vx_m_rv64-3.c | 160 + .../riscv/rvv/base/vsaddu_vx_mu_rv32-1.c | 157 + .../riscv/rvv/base/vsaddu_vx_mu_rv32-2.c | 157 + .../riscv/rvv/base/vsaddu_vx_mu_rv32-3.c | 157 + .../riscv/rvv/base/vsaddu_vx_mu_rv64-1.c | 160 + .../riscv/rvv/base/vsaddu_vx_mu_rv64-2.c | 160 + .../riscv/rvv/base/vsaddu_vx_mu_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vsaddu_vx_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vsaddu_vx_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vsaddu_vx_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vsaddu_vx_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vsaddu_vx_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vsaddu_vx_rv64-3.c | 160 + .../riscv/rvv/base/vsaddu_vx_tu_rv32-1.c | 157 + .../riscv/rvv/base/vsaddu_vx_tu_rv32-2.c | 157 + .../riscv/rvv/base/vsaddu_vx_tu_rv32-3.c | 157 + .../riscv/rvv/base/vsaddu_vx_tu_rv64-1.c | 160 + .../riscv/rvv/base/vsaddu_vx_tu_rv64-2.c | 160 + .../riscv/rvv/base/vsaddu_vx_tu_rv64-3.c | 160 + .../riscv/rvv/base/vsaddu_vx_tum_rv32-1.c | 157 + .../riscv/rvv/base/vsaddu_vx_tum_rv32-2.c | 157 + .../riscv/rvv/base/vsaddu_vx_tum_rv32-3.c | 157 + .../riscv/rvv/base/vsaddu_vx_tum_rv64-1.c | 160 + .../riscv/rvv/base/vsaddu_vx_tum_rv64-2.c | 160 + .../riscv/rvv/base/vsaddu_vx_tum_rv64-3.c | 160 + .../riscv/rvv/base/vsaddu_vx_tumu_rv32-1.c | 157 + .../riscv/rvv/base/vsaddu_vx_tumu_rv32-2.c | 157 + .../riscv/rvv/base/vsaddu_vx_tumu_rv32-3.c | 157 + .../riscv/rvv/base/vsaddu_vx_tumu_rv64-1.c | 160 + .../riscv/rvv/base/vsaddu_vx_tumu_rv64-2.c | 160 + .../riscv/rvv/base/vsaddu_vx_tumu_rv64-3.c | 160 + gcc/testsuite/gcc.target/riscv/rvv/base/vsbc-1.c | 27 + gcc/testsuite/gcc.target/riscv/rvv/base/vsbc-2.c | 56 + gcc/testsuite/gcc.target/riscv/rvv/base/vsbc-3.c | 77 + gcc/testsuite/gcc.target/riscv/rvv/base/vsbc-4.c | 78 + .../gcc.target/riscv/rvv/base/vsbc_vvm-1.c | 292 + .../gcc.target/riscv/rvv/base/vsbc_vvm-2.c | 292 + .../gcc.target/riscv/rvv/base/vsbc_vvm-3.c | 292 + .../gcc.target/riscv/rvv/base/vsbc_vvm_tu-1.c | 292 + .../gcc.target/riscv/rvv/base/vsbc_vvm_tu-2.c | 292 + .../gcc.target/riscv/rvv/base/vsbc_vvm_tu-3.c | 292 + .../gcc.target/riscv/rvv/base/vsbc_vxm_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vsbc_vxm_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vsbc_vxm_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vsbc_vxm_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vsbc_vxm_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vsbc_vxm_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vsext_vf2-1.c | 111 + .../gcc.target/riscv/rvv/base/vsext_vf2-2.c | 111 + .../gcc.target/riscv/rvv/base/vsext_vf2-3.c | 111 + .../gcc.target/riscv/rvv/base/vsext_vf2_m-1.c | 111 + .../gcc.target/riscv/rvv/base/vsext_vf2_m-2.c | 111 + .../gcc.target/riscv/rvv/base/vsext_vf2_m-3.c | 111 + .../gcc.target/riscv/rvv/base/vsext_vf2_mu-1.c | 111 + .../gcc.target/riscv/rvv/base/vsext_vf2_mu-2.c | 111 + .../gcc.target/riscv/rvv/base/vsext_vf2_mu-3.c | 111 + .../gcc.target/riscv/rvv/base/vsext_vf2_tu-1.c | 111 + .../gcc.target/riscv/rvv/base/vsext_vf2_tu-2.c | 111 + .../gcc.target/riscv/rvv/base/vsext_vf2_tu-3.c | 111 + .../gcc.target/riscv/rvv/base/vsext_vf2_tum-1.c | 111 + .../gcc.target/riscv/rvv/base/vsext_vf2_tum-2.c | 111 + .../gcc.target/riscv/rvv/base/vsext_vf2_tum-3.c | 111 + .../gcc.target/riscv/rvv/base/vsext_vf2_tumu-1.c | 111 + .../gcc.target/riscv/rvv/base/vsext_vf2_tumu-2.c | 111 + .../gcc.target/riscv/rvv/base/vsext_vf2_tumu-3.c | 111 + .../gcc.target/riscv/rvv/base/vsext_vf4-1.c | 69 + .../gcc.target/riscv/rvv/base/vsext_vf4-2.c | 69 + .../gcc.target/riscv/rvv/base/vsext_vf4-3.c | 69 + .../gcc.target/riscv/rvv/base/vsext_vf4_m-1.c | 69 + .../gcc.target/riscv/rvv/base/vsext_vf4_m-2.c | 69 + .../gcc.target/riscv/rvv/base/vsext_vf4_m-3.c | 69 + .../gcc.target/riscv/rvv/base/vsext_vf4_mu-1.c | 69 + .../gcc.target/riscv/rvv/base/vsext_vf4_mu-2.c | 69 + .../gcc.target/riscv/rvv/base/vsext_vf4_mu-3.c | 69 + .../gcc.target/riscv/rvv/base/vsext_vf4_tu-1.c | 69 + .../gcc.target/riscv/rvv/base/vsext_vf4_tu-2.c | 69 + .../gcc.target/riscv/rvv/base/vsext_vf4_tu-3.c | 69 + .../gcc.target/riscv/rvv/base/vsext_vf4_tum-1.c | 69 + .../gcc.target/riscv/rvv/base/vsext_vf4_tum-2.c | 69 + .../gcc.target/riscv/rvv/base/vsext_vf4_tum-3.c | 69 + .../gcc.target/riscv/rvv/base/vsext_vf4_tumu-1.c | 69 + .../gcc.target/riscv/rvv/base/vsext_vf4_tumu-2.c | 69 + .../gcc.target/riscv/rvv/base/vsext_vf4_tumu-3.c | 69 + .../gcc.target/riscv/rvv/base/vsext_vf8-1.c | 34 + .../gcc.target/riscv/rvv/base/vsext_vf8-2.c | 34 + .../gcc.target/riscv/rvv/base/vsext_vf8-3.c | 34 + .../gcc.target/riscv/rvv/base/vsext_vf8_m-1.c | 34 + .../gcc.target/riscv/rvv/base/vsext_vf8_m-2.c | 34 + .../gcc.target/riscv/rvv/base/vsext_vf8_m-3.c | 34 + .../gcc.target/riscv/rvv/base/vsext_vf8_mu-1.c | 34 + .../gcc.target/riscv/rvv/base/vsext_vf8_mu-2.c | 34 + .../gcc.target/riscv/rvv/base/vsext_vf8_mu-3.c | 34 + .../gcc.target/riscv/rvv/base/vsext_vf8_tu-1.c | 34 + .../gcc.target/riscv/rvv/base/vsext_vf8_tu-2.c | 34 + .../gcc.target/riscv/rvv/base/vsext_vf8_tu-3.c | 34 + .../gcc.target/riscv/rvv/base/vsext_vf8_tum-1.c | 34 + .../gcc.target/riscv/rvv/base/vsext_vf8_tum-2.c | 34 + .../gcc.target/riscv/rvv/base/vsext_vf8_tum-3.c | 34 + .../gcc.target/riscv/rvv/base/vsext_vf8_tumu-1.c | 34 + .../gcc.target/riscv/rvv/base/vsext_vf8_tumu-2.c | 34 + .../gcc.target/riscv/rvv/base/vsext_vf8_tumu-3.c | 34 + .../gcc.target/riscv/rvv/base/vsll_vv-1.c | 292 + .../gcc.target/riscv/rvv/base/vsll_vv-2.c | 292 + .../gcc.target/riscv/rvv/base/vsll_vv-3.c | 292 + .../gcc.target/riscv/rvv/base/vsll_vv_m-1.c | 292 + .../gcc.target/riscv/rvv/base/vsll_vv_m-2.c | 292 + .../gcc.target/riscv/rvv/base/vsll_vv_m-3.c | 292 + .../gcc.target/riscv/rvv/base/vsll_vv_mu-1.c | 292 + .../gcc.target/riscv/rvv/base/vsll_vv_mu-2.c | 292 + .../gcc.target/riscv/rvv/base/vsll_vv_mu-3.c | 292 + .../gcc.target/riscv/rvv/base/vsll_vv_tu-1.c | 292 + .../gcc.target/riscv/rvv/base/vsll_vv_tu-2.c | 292 + .../gcc.target/riscv/rvv/base/vsll_vv_tu-3.c | 292 + .../gcc.target/riscv/rvv/base/vsll_vv_tum-1.c | 292 + .../gcc.target/riscv/rvv/base/vsll_vv_tum-2.c | 292 + .../gcc.target/riscv/rvv/base/vsll_vv_tum-3.c | 292 + .../gcc.target/riscv/rvv/base/vsll_vv_tumu-1.c | 292 + .../gcc.target/riscv/rvv/base/vsll_vv_tumu-2.c | 292 + .../gcc.target/riscv/rvv/base/vsll_vv_tumu-3.c | 292 + .../gcc.target/riscv/rvv/base/vsll_vx-1.c | 292 + .../gcc.target/riscv/rvv/base/vsll_vx-2.c | 292 + .../gcc.target/riscv/rvv/base/vsll_vx-3.c | 292 + .../gcc.target/riscv/rvv/base/vsll_vx_m-1.c | 292 + .../gcc.target/riscv/rvv/base/vsll_vx_m-2.c | 292 + .../gcc.target/riscv/rvv/base/vsll_vx_m-3.c | 292 + .../gcc.target/riscv/rvv/base/vsll_vx_mu-1.c | 292 + .../gcc.target/riscv/rvv/base/vsll_vx_mu-2.c | 292 + .../gcc.target/riscv/rvv/base/vsll_vx_mu-3.c | 292 + .../gcc.target/riscv/rvv/base/vsll_vx_tu-1.c | 292 + .../gcc.target/riscv/rvv/base/vsll_vx_tu-2.c | 292 + .../gcc.target/riscv/rvv/base/vsll_vx_tu-3.c | 292 + .../gcc.target/riscv/rvv/base/vsll_vx_tum-1.c | 292 + .../gcc.target/riscv/rvv/base/vsll_vx_tum-2.c | 292 + .../gcc.target/riscv/rvv/base/vsll_vx_tum-3.c | 292 + .../gcc.target/riscv/rvv/base/vsll_vx_tumu-1.c | 292 + .../gcc.target/riscv/rvv/base/vsll_vx_tumu-2.c | 292 + .../gcc.target/riscv/rvv/base/vsll_vx_tumu-3.c | 292 + .../gcc.target/riscv/rvv/base/vsmul_vv-1.c | 160 + .../gcc.target/riscv/rvv/base/vsmul_vv-2.c | 160 + .../gcc.target/riscv/rvv/base/vsmul_vv-3.c | 160 + .../gcc.target/riscv/rvv/base/vsmul_vv_m-1.c | 160 + .../gcc.target/riscv/rvv/base/vsmul_vv_m-2.c | 160 + .../gcc.target/riscv/rvv/base/vsmul_vv_m-3.c | 160 + .../gcc.target/riscv/rvv/base/vsmul_vv_mu-1.c | 160 + .../gcc.target/riscv/rvv/base/vsmul_vv_mu-2.c | 160 + .../gcc.target/riscv/rvv/base/vsmul_vv_mu-3.c | 160 + .../gcc.target/riscv/rvv/base/vsmul_vv_tu-1.c | 160 + .../gcc.target/riscv/rvv/base/vsmul_vv_tu-2.c | 160 + .../gcc.target/riscv/rvv/base/vsmul_vv_tu-3.c | 160 + .../gcc.target/riscv/rvv/base/vsmul_vv_tum-1.c | 160 + .../gcc.target/riscv/rvv/base/vsmul_vv_tum-2.c | 160 + .../gcc.target/riscv/rvv/base/vsmul_vv_tum-3.c | 160 + .../gcc.target/riscv/rvv/base/vsmul_vv_tumu-1.c | 160 + .../gcc.target/riscv/rvv/base/vsmul_vv_tumu-2.c | 160 + .../gcc.target/riscv/rvv/base/vsmul_vv_tumu-3.c | 160 + .../gcc.target/riscv/rvv/base/vsmul_vx_m_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vsmul_vx_m_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vsmul_vx_m_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vsmul_vx_m_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vsmul_vx_m_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vsmul_vx_m_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vsmul_vx_mu_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vsmul_vx_mu_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vsmul_vx_mu_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vsmul_vx_mu_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vsmul_vx_mu_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vsmul_vx_mu_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vsmul_vx_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vsmul_vx_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vsmul_vx_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vsmul_vx_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vsmul_vx_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vsmul_vx_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vsmul_vx_tu_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vsmul_vx_tu_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vsmul_vx_tu_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vsmul_vx_tu_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vsmul_vx_tu_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vsmul_vx_tu_rv64-3.c | 160 + .../riscv/rvv/base/vsmul_vx_tum_rv32-1.c | 157 + .../riscv/rvv/base/vsmul_vx_tum_rv32-2.c | 157 + .../riscv/rvv/base/vsmul_vx_tum_rv32-3.c | 157 + .../riscv/rvv/base/vsmul_vx_tum_rv64-1.c | 160 + .../riscv/rvv/base/vsmul_vx_tum_rv64-2.c | 160 + .../riscv/rvv/base/vsmul_vx_tum_rv64-3.c | 160 + .../riscv/rvv/base/vsmul_vx_tumu_rv32-1.c | 157 + .../riscv/rvv/base/vsmul_vx_tumu_rv32-2.c | 157 + .../riscv/rvv/base/vsmul_vx_tumu_rv32-3.c | 157 + .../riscv/rvv/base/vsmul_vx_tumu_rv64-1.c | 160 + .../riscv/rvv/base/vsmul_vx_tumu_rv64-2.c | 160 + .../riscv/rvv/base/vsmul_vx_tumu_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vsra_vv-1.c | 160 + .../gcc.target/riscv/rvv/base/vsra_vv-2.c | 160 + .../gcc.target/riscv/rvv/base/vsra_vv-3.c | 160 + .../gcc.target/riscv/rvv/base/vsra_vv_m-1.c | 160 + .../gcc.target/riscv/rvv/base/vsra_vv_m-2.c | 160 + .../gcc.target/riscv/rvv/base/vsra_vv_m-3.c | 160 + .../gcc.target/riscv/rvv/base/vsra_vv_mu-1.c | 160 + .../gcc.target/riscv/rvv/base/vsra_vv_mu-2.c | 160 + .../gcc.target/riscv/rvv/base/vsra_vv_mu-3.c | 160 + .../gcc.target/riscv/rvv/base/vsra_vv_tu-1.c | 160 + .../gcc.target/riscv/rvv/base/vsra_vv_tu-2.c | 160 + .../gcc.target/riscv/rvv/base/vsra_vv_tu-3.c | 160 + .../gcc.target/riscv/rvv/base/vsra_vv_tum-1.c | 160 + .../gcc.target/riscv/rvv/base/vsra_vv_tum-2.c | 160 + .../gcc.target/riscv/rvv/base/vsra_vv_tum-3.c | 160 + .../gcc.target/riscv/rvv/base/vsra_vv_tumu-1.c | 160 + .../gcc.target/riscv/rvv/base/vsra_vv_tumu-2.c | 160 + .../gcc.target/riscv/rvv/base/vsra_vv_tumu-3.c | 160 + .../gcc.target/riscv/rvv/base/vsra_vx-1.c | 160 + .../gcc.target/riscv/rvv/base/vsra_vx-2.c | 160 + .../gcc.target/riscv/rvv/base/vsra_vx-3.c | 160 + .../gcc.target/riscv/rvv/base/vsra_vx_m-1.c | 160 + .../gcc.target/riscv/rvv/base/vsra_vx_m-2.c | 160 + .../gcc.target/riscv/rvv/base/vsra_vx_m-3.c | 160 + .../gcc.target/riscv/rvv/base/vsra_vx_mu-1.c | 160 + .../gcc.target/riscv/rvv/base/vsra_vx_mu-2.c | 160 + .../gcc.target/riscv/rvv/base/vsra_vx_mu-3.c | 160 + .../gcc.target/riscv/rvv/base/vsra_vx_tu-1.c | 160 + .../gcc.target/riscv/rvv/base/vsra_vx_tu-2.c | 160 + .../gcc.target/riscv/rvv/base/vsra_vx_tu-3.c | 160 + .../gcc.target/riscv/rvv/base/vsra_vx_tum-1.c | 160 + .../gcc.target/riscv/rvv/base/vsra_vx_tum-2.c | 160 + .../gcc.target/riscv/rvv/base/vsra_vx_tum-3.c | 160 + .../gcc.target/riscv/rvv/base/vsra_vx_tumu-1.c | 160 + .../gcc.target/riscv/rvv/base/vsra_vx_tumu-2.c | 160 + .../gcc.target/riscv/rvv/base/vsra_vx_tumu-3.c | 160 + .../gcc.target/riscv/rvv/base/vsrl_vv-1.c | 160 + .../gcc.target/riscv/rvv/base/vsrl_vv-2.c | 160 + .../gcc.target/riscv/rvv/base/vsrl_vv-3.c | 160 + .../gcc.target/riscv/rvv/base/vsrl_vv_m-1.c | 160 + .../gcc.target/riscv/rvv/base/vsrl_vv_m-2.c | 160 + .../gcc.target/riscv/rvv/base/vsrl_vv_m-3.c | 160 + .../gcc.target/riscv/rvv/base/vsrl_vv_mu-1.c | 160 + .../gcc.target/riscv/rvv/base/vsrl_vv_mu-2.c | 160 + .../gcc.target/riscv/rvv/base/vsrl_vv_mu-3.c | 160 + .../gcc.target/riscv/rvv/base/vsrl_vv_tu-1.c | 160 + .../gcc.target/riscv/rvv/base/vsrl_vv_tu-2.c | 160 + .../gcc.target/riscv/rvv/base/vsrl_vv_tu-3.c | 160 + .../gcc.target/riscv/rvv/base/vsrl_vv_tum-1.c | 160 + .../gcc.target/riscv/rvv/base/vsrl_vv_tum-2.c | 160 + .../gcc.target/riscv/rvv/base/vsrl_vv_tum-3.c | 160 + .../gcc.target/riscv/rvv/base/vsrl_vv_tumu-1.c | 160 + .../gcc.target/riscv/rvv/base/vsrl_vv_tumu-2.c | 160 + .../gcc.target/riscv/rvv/base/vsrl_vv_tumu-3.c | 160 + .../gcc.target/riscv/rvv/base/vsrl_vx-1.c | 160 + .../gcc.target/riscv/rvv/base/vsrl_vx-2.c | 160 + .../gcc.target/riscv/rvv/base/vsrl_vx-3.c | 160 + .../gcc.target/riscv/rvv/base/vsrl_vx_m-1.c | 160 + .../gcc.target/riscv/rvv/base/vsrl_vx_m-2.c | 160 + .../gcc.target/riscv/rvv/base/vsrl_vx_m-3.c | 160 + .../gcc.target/riscv/rvv/base/vsrl_vx_mu-1.c | 160 + .../gcc.target/riscv/rvv/base/vsrl_vx_mu-2.c | 160 + .../gcc.target/riscv/rvv/base/vsrl_vx_mu-3.c | 160 + .../gcc.target/riscv/rvv/base/vsrl_vx_tu-1.c | 160 + .../gcc.target/riscv/rvv/base/vsrl_vx_tu-2.c | 160 + .../gcc.target/riscv/rvv/base/vsrl_vx_tu-3.c | 160 + .../gcc.target/riscv/rvv/base/vsrl_vx_tum-1.c | 160 + .../gcc.target/riscv/rvv/base/vsrl_vx_tum-2.c | 160 + .../gcc.target/riscv/rvv/base/vsrl_vx_tum-3.c | 160 + .../gcc.target/riscv/rvv/base/vsrl_vx_tumu-1.c | 160 + .../gcc.target/riscv/rvv/base/vsrl_vx_tumu-2.c | 160 + .../gcc.target/riscv/rvv/base/vsrl_vx_tumu-3.c | 160 + .../gcc.target/riscv/rvv/base/vssra_vv-1.c | 160 + .../gcc.target/riscv/rvv/base/vssra_vv-2.c | 160 + .../gcc.target/riscv/rvv/base/vssra_vv-3.c | 160 + .../gcc.target/riscv/rvv/base/vssra_vv_m-1.c | 160 + .../gcc.target/riscv/rvv/base/vssra_vv_m-2.c | 160 + .../gcc.target/riscv/rvv/base/vssra_vv_m-3.c | 160 + .../gcc.target/riscv/rvv/base/vssra_vv_mu-1.c | 160 + .../gcc.target/riscv/rvv/base/vssra_vv_mu-2.c | 160 + .../gcc.target/riscv/rvv/base/vssra_vv_mu-3.c | 160 + .../gcc.target/riscv/rvv/base/vssra_vv_tu-1.c | 160 + .../gcc.target/riscv/rvv/base/vssra_vv_tu-2.c | 160 + .../gcc.target/riscv/rvv/base/vssra_vv_tu-3.c | 160 + .../gcc.target/riscv/rvv/base/vssra_vv_tum-1.c | 160 + .../gcc.target/riscv/rvv/base/vssra_vv_tum-2.c | 160 + .../gcc.target/riscv/rvv/base/vssra_vv_tum-3.c | 160 + .../gcc.target/riscv/rvv/base/vssra_vv_tumu-1.c | 160 + .../gcc.target/riscv/rvv/base/vssra_vv_tumu-2.c | 160 + .../gcc.target/riscv/rvv/base/vssra_vv_tumu-3.c | 160 + .../gcc.target/riscv/rvv/base/vssra_vx-1.c | 160 + .../gcc.target/riscv/rvv/base/vssra_vx-2.c | 160 + .../gcc.target/riscv/rvv/base/vssra_vx-3.c | 160 + .../gcc.target/riscv/rvv/base/vssra_vx_m-1.c | 160 + .../gcc.target/riscv/rvv/base/vssra_vx_m-2.c | 160 + .../gcc.target/riscv/rvv/base/vssra_vx_m-3.c | 160 + .../gcc.target/riscv/rvv/base/vssra_vx_mu-1.c | 160 + .../gcc.target/riscv/rvv/base/vssra_vx_mu-2.c | 160 + .../gcc.target/riscv/rvv/base/vssra_vx_mu-3.c | 160 + .../gcc.target/riscv/rvv/base/vssra_vx_tu-1.c | 160 + .../gcc.target/riscv/rvv/base/vssra_vx_tu-2.c | 160 + .../gcc.target/riscv/rvv/base/vssra_vx_tu-3.c | 160 + .../gcc.target/riscv/rvv/base/vssra_vx_tum-1.c | 160 + .../gcc.target/riscv/rvv/base/vssra_vx_tum-2.c | 160 + .../gcc.target/riscv/rvv/base/vssra_vx_tum-3.c | 160 + .../gcc.target/riscv/rvv/base/vssra_vx_tumu-1.c | 160 + .../gcc.target/riscv/rvv/base/vssra_vx_tumu-2.c | 160 + .../gcc.target/riscv/rvv/base/vssra_vx_tumu-3.c | 160 + .../gcc.target/riscv/rvv/base/vssrl_vv-1.c | 160 + .../gcc.target/riscv/rvv/base/vssrl_vv-2.c | 160 + .../gcc.target/riscv/rvv/base/vssrl_vv-3.c | 160 + .../gcc.target/riscv/rvv/base/vssrl_vv_m-1.c | 160 + .../gcc.target/riscv/rvv/base/vssrl_vv_m-2.c | 160 + .../gcc.target/riscv/rvv/base/vssrl_vv_m-3.c | 160 + .../gcc.target/riscv/rvv/base/vssrl_vv_mu-1.c | 160 + .../gcc.target/riscv/rvv/base/vssrl_vv_mu-2.c | 160 + .../gcc.target/riscv/rvv/base/vssrl_vv_mu-3.c | 160 + .../gcc.target/riscv/rvv/base/vssrl_vv_tu-1.c | 160 + .../gcc.target/riscv/rvv/base/vssrl_vv_tu-2.c | 160 + .../gcc.target/riscv/rvv/base/vssrl_vv_tu-3.c | 160 + .../gcc.target/riscv/rvv/base/vssrl_vv_tum-1.c | 160 + .../gcc.target/riscv/rvv/base/vssrl_vv_tum-2.c | 160 + .../gcc.target/riscv/rvv/base/vssrl_vv_tum-3.c | 160 + .../gcc.target/riscv/rvv/base/vssrl_vv_tumu-1.c | 160 + .../gcc.target/riscv/rvv/base/vssrl_vv_tumu-2.c | 160 + .../gcc.target/riscv/rvv/base/vssrl_vv_tumu-3.c | 160 + .../gcc.target/riscv/rvv/base/vssrl_vx-1.c | 160 + .../gcc.target/riscv/rvv/base/vssrl_vx-2.c | 160 + .../gcc.target/riscv/rvv/base/vssrl_vx-3.c | 160 + .../gcc.target/riscv/rvv/base/vssrl_vx_m-1.c | 160 + .../gcc.target/riscv/rvv/base/vssrl_vx_m-2.c | 160 + .../gcc.target/riscv/rvv/base/vssrl_vx_m-3.c | 160 + .../gcc.target/riscv/rvv/base/vssrl_vx_mu-1.c | 160 + .../gcc.target/riscv/rvv/base/vssrl_vx_mu-2.c | 160 + .../gcc.target/riscv/rvv/base/vssrl_vx_mu-3.c | 160 + .../gcc.target/riscv/rvv/base/vssrl_vx_tu-1.c | 160 + .../gcc.target/riscv/rvv/base/vssrl_vx_tu-2.c | 160 + .../gcc.target/riscv/rvv/base/vssrl_vx_tu-3.c | 160 + .../gcc.target/riscv/rvv/base/vssrl_vx_tum-1.c | 160 + .../gcc.target/riscv/rvv/base/vssrl_vx_tum-2.c | 160 + .../gcc.target/riscv/rvv/base/vssrl_vx_tum-3.c | 160 + .../gcc.target/riscv/rvv/base/vssrl_vx_tumu-1.c | 160 + .../gcc.target/riscv/rvv/base/vssrl_vx_tumu-2.c | 160 + .../gcc.target/riscv/rvv/base/vssrl_vx_tumu-3.c | 160 + .../gcc.target/riscv/rvv/base/vssub_vv-1.c | 160 + .../gcc.target/riscv/rvv/base/vssub_vv-2.c | 160 + .../gcc.target/riscv/rvv/base/vssub_vv-3.c | 160 + .../gcc.target/riscv/rvv/base/vssub_vv_m-1.c | 160 + .../gcc.target/riscv/rvv/base/vssub_vv_m-2.c | 160 + .../gcc.target/riscv/rvv/base/vssub_vv_m-3.c | 160 + .../gcc.target/riscv/rvv/base/vssub_vv_mu-1.c | 160 + .../gcc.target/riscv/rvv/base/vssub_vv_mu-2.c | 160 + .../gcc.target/riscv/rvv/base/vssub_vv_mu-3.c | 160 + .../gcc.target/riscv/rvv/base/vssub_vv_tu-1.c | 160 + .../gcc.target/riscv/rvv/base/vssub_vv_tu-2.c | 160 + .../gcc.target/riscv/rvv/base/vssub_vv_tu-3.c | 160 + .../gcc.target/riscv/rvv/base/vssub_vv_tum-1.c | 160 + .../gcc.target/riscv/rvv/base/vssub_vv_tum-2.c | 160 + .../gcc.target/riscv/rvv/base/vssub_vv_tum-3.c | 160 + .../gcc.target/riscv/rvv/base/vssub_vv_tumu-1.c | 160 + .../gcc.target/riscv/rvv/base/vssub_vv_tumu-2.c | 160 + .../gcc.target/riscv/rvv/base/vssub_vv_tumu-3.c | 160 + .../gcc.target/riscv/rvv/base/vssub_vx_m_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vssub_vx_m_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vssub_vx_m_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vssub_vx_m_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vssub_vx_m_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vssub_vx_m_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vssub_vx_mu_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vssub_vx_mu_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vssub_vx_mu_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vssub_vx_mu_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vssub_vx_mu_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vssub_vx_mu_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vssub_vx_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vssub_vx_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vssub_vx_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vssub_vx_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vssub_vx_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vssub_vx_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vssub_vx_tu_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vssub_vx_tu_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vssub_vx_tu_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vssub_vx_tu_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vssub_vx_tu_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vssub_vx_tu_rv64-3.c | 160 + .../riscv/rvv/base/vssub_vx_tum_rv32-1.c | 157 + .../riscv/rvv/base/vssub_vx_tum_rv32-2.c | 157 + .../riscv/rvv/base/vssub_vx_tum_rv32-3.c | 157 + .../riscv/rvv/base/vssub_vx_tum_rv64-1.c | 160 + .../riscv/rvv/base/vssub_vx_tum_rv64-2.c | 160 + .../riscv/rvv/base/vssub_vx_tum_rv64-3.c | 160 + .../riscv/rvv/base/vssub_vx_tumu_rv32-1.c | 157 + .../riscv/rvv/base/vssub_vx_tumu_rv32-2.c | 157 + .../riscv/rvv/base/vssub_vx_tumu_rv32-3.c | 157 + .../riscv/rvv/base/vssub_vx_tumu_rv64-1.c | 160 + .../riscv/rvv/base/vssub_vx_tumu_rv64-2.c | 160 + .../riscv/rvv/base/vssub_vx_tumu_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vssubu_vv-1.c | 160 + .../gcc.target/riscv/rvv/base/vssubu_vv-2.c | 160 + .../gcc.target/riscv/rvv/base/vssubu_vv-3.c | 160 + .../gcc.target/riscv/rvv/base/vssubu_vv_m-1.c | 160 + .../gcc.target/riscv/rvv/base/vssubu_vv_m-2.c | 160 + .../gcc.target/riscv/rvv/base/vssubu_vv_m-3.c | 160 + .../gcc.target/riscv/rvv/base/vssubu_vv_mu-1.c | 160 + .../gcc.target/riscv/rvv/base/vssubu_vv_mu-2.c | 160 + .../gcc.target/riscv/rvv/base/vssubu_vv_mu-3.c | 160 + .../gcc.target/riscv/rvv/base/vssubu_vv_tu-1.c | 160 + .../gcc.target/riscv/rvv/base/vssubu_vv_tu-2.c | 160 + .../gcc.target/riscv/rvv/base/vssubu_vv_tu-3.c | 160 + .../gcc.target/riscv/rvv/base/vssubu_vv_tum-1.c | 160 + .../gcc.target/riscv/rvv/base/vssubu_vv_tum-2.c | 160 + .../gcc.target/riscv/rvv/base/vssubu_vv_tum-3.c | 160 + .../gcc.target/riscv/rvv/base/vssubu_vv_tumu-1.c | 160 + .../gcc.target/riscv/rvv/base/vssubu_vv_tumu-2.c | 160 + .../gcc.target/riscv/rvv/base/vssubu_vv_tumu-3.c | 160 + .../gcc.target/riscv/rvv/base/vssubu_vx_m_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vssubu_vx_m_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vssubu_vx_m_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vssubu_vx_m_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vssubu_vx_m_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vssubu_vx_m_rv64-3.c | 160 + .../riscv/rvv/base/vssubu_vx_mu_rv32-1.c | 157 + .../riscv/rvv/base/vssubu_vx_mu_rv32-2.c | 157 + .../riscv/rvv/base/vssubu_vx_mu_rv32-3.c | 157 + .../riscv/rvv/base/vssubu_vx_mu_rv64-1.c | 160 + .../riscv/rvv/base/vssubu_vx_mu_rv64-2.c | 160 + .../riscv/rvv/base/vssubu_vx_mu_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vssubu_vx_rv32-1.c | 157 + .../gcc.target/riscv/rvv/base/vssubu_vx_rv32-2.c | 157 + .../gcc.target/riscv/rvv/base/vssubu_vx_rv32-3.c | 157 + .../gcc.target/riscv/rvv/base/vssubu_vx_rv64-1.c | 160 + .../gcc.target/riscv/rvv/base/vssubu_vx_rv64-2.c | 160 + .../gcc.target/riscv/rvv/base/vssubu_vx_rv64-3.c | 160 + .../riscv/rvv/base/vssubu_vx_tu_rv32-1.c | 157 + .../riscv/rvv/base/vssubu_vx_tu_rv32-2.c | 157 + .../riscv/rvv/base/vssubu_vx_tu_rv32-3.c | 157 + .../riscv/rvv/base/vssubu_vx_tu_rv64-1.c | 160 + .../riscv/rvv/base/vssubu_vx_tu_rv64-2.c | 160 + .../riscv/rvv/base/vssubu_vx_tu_rv64-3.c | 160 + .../riscv/rvv/base/vssubu_vx_tum_rv32-1.c | 157 + .../riscv/rvv/base/vssubu_vx_tum_rv32-2.c | 157 + .../riscv/rvv/base/vssubu_vx_tum_rv32-3.c | 157 + .../riscv/rvv/base/vssubu_vx_tum_rv64-1.c | 160 + .../riscv/rvv/base/vssubu_vx_tum_rv64-2.c | 160 + .../riscv/rvv/base/vssubu_vx_tum_rv64-3.c | 160 + .../riscv/rvv/base/vssubu_vx_tumu_rv32-1.c | 157 + .../riscv/rvv/base/vssubu_vx_tumu_rv32-2.c | 157 + .../riscv/rvv/base/vssubu_vx_tumu_rv32-3.c | 157 + .../riscv/rvv/base/vssubu_vx_tumu_rv64-1.c | 160 + .../riscv/rvv/base/vssubu_vx_tumu_rv64-2.c | 160 + .../riscv/rvv/base/vssubu_vx_tumu_rv64-3.c | 160 + .../gcc.target/riscv/rvv/base/vsub_vv-1.c | 292 + .../gcc.target/riscv/rvv/base/vsub_vv-2.c | 292 + .../gcc.target/riscv/rvv/base/vsub_vv-3.c | 292 + .../gcc.target/riscv/rvv/base/vsub_vv_m-1.c | 292 + .../gcc.target/riscv/rvv/base/vsub_vv_m-2.c | 292 + .../gcc.target/riscv/rvv/base/vsub_vv_m-3.c | 292 + .../gcc.target/riscv/rvv/base/vsub_vv_mu-1.c | 292 + .../gcc.target/riscv/rvv/base/vsub_vv_mu-2.c | 292 + .../gcc.target/riscv/rvv/base/vsub_vv_mu-3.c | 292 + .../gcc.target/riscv/rvv/base/vsub_vv_tu-1.c | 292 + .../gcc.target/riscv/rvv/base/vsub_vv_tu-2.c | 292 + .../gcc.target/riscv/rvv/base/vsub_vv_tu-3.c | 292 + .../gcc.target/riscv/rvv/base/vsub_vv_tum-1.c | 292 + .../gcc.target/riscv/rvv/base/vsub_vv_tum-2.c | 292 + .../gcc.target/riscv/rvv/base/vsub_vv_tum-3.c | 292 + .../gcc.target/riscv/rvv/base/vsub_vv_tumu-1.c | 292 + .../gcc.target/riscv/rvv/base/vsub_vv_tumu-2.c | 292 + .../gcc.target/riscv/rvv/base/vsub_vv_tumu-3.c | 292 + .../gcc.target/riscv/rvv/base/vsub_vx_m_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vsub_vx_m_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vsub_vx_m_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vsub_vx_m_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vsub_vx_m_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vsub_vx_m_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vsub_vx_mu_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vsub_vx_mu_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vsub_vx_mu_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vsub_vx_mu_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vsub_vx_mu_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vsub_vx_mu_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vsub_vx_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vsub_vx_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vsub_vx_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vsub_vx_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vsub_vx_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vsub_vx_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vsub_vx_tu_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vsub_vx_tu_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vsub_vx_tu_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vsub_vx_tu_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vsub_vx_tu_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vsub_vx_tu_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vsub_vx_tum_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vsub_vx_tum_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vsub_vx_tum_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vsub_vx_tum_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vsub_vx_tum_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vsub_vx_tum_rv64-3.c | 292 + .../riscv/rvv/base/vsub_vx_tumu_rv32-1.c | 289 + .../riscv/rvv/base/vsub_vx_tumu_rv32-2.c | 289 + .../riscv/rvv/base/vsub_vx_tumu_rv32-3.c | 289 + .../riscv/rvv/base/vsub_vx_tumu_rv64-1.c | 292 + .../riscv/rvv/base/vsub_vx_tumu_rv64-2.c | 292 + .../riscv/rvv/base/vsub_vx_tumu_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vwadd_vv-1.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_vv-2.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_vv-3.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_vv_m-1.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_vv_m-2.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_vv_m-3.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_vv_mu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_vv_mu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_vv_mu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_vv_tu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_vv_tu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_vv_tu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_vv_tum-1.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_vv_tum-2.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_vv_tum-3.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_vv_tumu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_vv_tumu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_vv_tumu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_vx-1.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_vx-2.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_vx-3.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_vx_m-1.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_vx_m-2.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_vx_m-3.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_vx_mu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_vx_mu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_vx_mu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_vx_tu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_vx_tu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_vx_tu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_vx_tum-1.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_vx_tum-2.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_vx_tum-3.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_vx_tumu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_vx_tumu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_vx_tumu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_wv-1.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_wv-2.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_wv-3.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_wv_m-1.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_wv_m-2.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_wv_m-3.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_wv_mu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_wv_mu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_wv_mu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_wv_tu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_wv_tu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_wv_tu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_wv_tum-1.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_wv_tum-2.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_wv_tum-3.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_wv_tumu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_wv_tumu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_wv_tumu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_wx-1.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_wx-2.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_wx-3.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_wx_m-1.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_wx_m-2.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_wx_m-3.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_wx_mu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_wx_mu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_wx_mu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_wx_tu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_wx_tu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_wx_tu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_wx_tum-1.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_wx_tum-2.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_wx_tum-3.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_wx_tumu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_wx_tumu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwadd_wx_tumu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_vv-1.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_vv-2.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_vv-3.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_vv_m-1.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_vv_m-2.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_vv_m-3.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_vv_mu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_vv_mu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_vv_mu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_vv_tu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_vv_tu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_vv_tu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_vv_tum-1.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_vv_tum-2.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_vv_tum-3.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_vv_tumu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_vv_tumu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_vv_tumu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_vx-1.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_vx-2.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_vx-3.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_vx_m-1.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_vx_m-2.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_vx_m-3.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_vx_mu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_vx_mu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_vx_mu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_vx_tu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_vx_tu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_vx_tu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_vx_tum-1.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_vx_tum-2.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_vx_tum-3.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_vx_tumu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_vx_tumu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_vx_tumu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_wv-1.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_wv-2.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_wv-3.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_wv_m-1.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_wv_m-2.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_wv_m-3.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_wv_mu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_wv_mu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_wv_mu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_wv_tu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_wv_tu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_wv_tu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_wv_tum-1.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_wv_tum-2.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_wv_tum-3.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_wv_tumu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_wv_tumu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_wv_tumu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_wx-1.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_wx-2.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_wx-3.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_wx_m-1.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_wx_m-2.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_wx_m-3.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_wx_mu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_wx_mu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_wx_mu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_wx_tu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_wx_tu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_wx_tu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_wx_tum-1.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_wx_tum-2.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_wx_tum-3.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_wx_tumu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_wx_tumu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwaddu_wx_tumu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwcvt_x-1.c | 111 + .../gcc.target/riscv/rvv/base/vwcvt_x-2.c | 111 + .../gcc.target/riscv/rvv/base/vwcvt_x-3.c | 111 + .../gcc.target/riscv/rvv/base/vwcvt_x_m-1.c | 111 + .../gcc.target/riscv/rvv/base/vwcvt_x_m-2.c | 111 + .../gcc.target/riscv/rvv/base/vwcvt_x_m-3.c | 111 + .../gcc.target/riscv/rvv/base/vwcvt_x_mu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwcvt_x_mu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwcvt_x_mu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwcvt_x_tu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwcvt_x_tu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwcvt_x_tu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwcvt_x_tum-1.c | 111 + .../gcc.target/riscv/rvv/base/vwcvt_x_tum-2.c | 111 + .../gcc.target/riscv/rvv/base/vwcvt_x_tum-3.c | 111 + .../gcc.target/riscv/rvv/base/vwcvt_x_tumu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwcvt_x_tumu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwcvt_x_tumu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwcvtu_x-1.c | 111 + .../gcc.target/riscv/rvv/base/vwcvtu_x-2.c | 111 + .../gcc.target/riscv/rvv/base/vwcvtu_x-3.c | 111 + .../gcc.target/riscv/rvv/base/vwcvtu_x_m-1.c | 111 + .../gcc.target/riscv/rvv/base/vwcvtu_x_m-2.c | 111 + .../gcc.target/riscv/rvv/base/vwcvtu_x_m-3.c | 111 + .../gcc.target/riscv/rvv/base/vwcvtu_x_mu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwcvtu_x_mu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwcvtu_x_mu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwcvtu_x_tu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwcvtu_x_tu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwcvtu_x_tu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwcvtu_x_tum-1.c | 111 + .../gcc.target/riscv/rvv/base/vwcvtu_x_tum-2.c | 111 + .../gcc.target/riscv/rvv/base/vwcvtu_x_tum-3.c | 111 + .../gcc.target/riscv/rvv/base/vwcvtu_x_tumu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwcvtu_x_tumu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwcvtu_x_tumu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmacc_vv-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmacc_vv-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmacc_vv-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmacc_vv_m-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmacc_vv_m-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmacc_vv_m-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmacc_vv_mu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmacc_vv_mu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmacc_vv_mu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmacc_vv_tu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmacc_vv_tu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmacc_vv_tu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmacc_vv_tum-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmacc_vv_tum-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmacc_vv_tum-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmacc_vv_tumu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmacc_vv_tumu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmacc_vv_tumu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmacc_vx-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmacc_vx-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmacc_vx-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmacc_vx_m-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmacc_vx_m-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmacc_vx_m-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmacc_vx_mu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmacc_vx_mu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmacc_vx_mu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmacc_vx_tu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmacc_vx_tu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmacc_vx_tu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmacc_vx_tum-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmacc_vx_tum-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmacc_vx_tum-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmacc_vx_tumu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmacc_vx_tumu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmacc_vx_tumu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccsu_vv-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccsu_vv-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccsu_vv-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccsu_vv_m-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccsu_vv_m-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccsu_vv_m-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccsu_vv_mu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccsu_vv_mu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccsu_vv_mu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccsu_vv_tu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccsu_vv_tu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccsu_vv_tu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccsu_vv_tum-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccsu_vv_tum-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccsu_vv_tum-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccsu_vv_tumu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccsu_vv_tumu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccsu_vv_tumu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccsu_vx-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccsu_vx-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccsu_vx-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccsu_vx_m-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccsu_vx_m-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccsu_vx_m-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccsu_vx_mu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccsu_vx_mu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccsu_vx_mu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccsu_vx_tu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccsu_vx_tu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccsu_vx_tu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccsu_vx_tum-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccsu_vx_tum-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccsu_vx_tum-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccsu_vx_tumu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccsu_vx_tumu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccsu_vx_tumu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccu_vv-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccu_vv-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccu_vv-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccu_vv_m-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccu_vv_m-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccu_vv_m-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccu_vv_mu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccu_vv_mu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccu_vv_mu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccu_vv_tu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccu_vv_tu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccu_vv_tu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccu_vv_tum-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccu_vv_tum-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccu_vv_tum-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccu_vv_tumu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccu_vv_tumu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccu_vv_tumu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccu_vx-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccu_vx-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccu_vx-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccu_vx_m-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccu_vx_m-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccu_vx_m-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccu_vx_mu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccu_vx_mu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccu_vx_mu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccu_vx_tu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccu_vx_tu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccu_vx_tu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccu_vx_tum-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccu_vx_tum-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccu_vx_tum-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccu_vx_tumu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccu_vx_tumu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccu_vx_tumu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccus_vx-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccus_vx-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccus_vx-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccus_vx_m-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccus_vx_m-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccus_vx_m-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccus_vx_mu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccus_vx_mu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccus_vx_mu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccus_vx_tu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccus_vx_tu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccus_vx_tu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccus_vx_tum-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccus_vx_tum-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccus_vx_tum-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccus_vx_tumu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccus_vx_tumu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmaccus_vx_tumu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmul_vv-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmul_vv-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmul_vv-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmul_vv_m-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmul_vv_m-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmul_vv_m-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmul_vv_mu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmul_vv_mu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmul_vv_mu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmul_vv_tu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmul_vv_tu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmul_vv_tu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmul_vv_tum-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmul_vv_tum-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmul_vv_tum-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmul_vv_tumu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmul_vv_tumu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmul_vv_tumu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmul_vx-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmul_vx-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmul_vx-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmul_vx_m-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmul_vx_m-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmul_vx_m-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmul_vx_mu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmul_vx_mu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmul_vx_mu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmul_vx_tu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmul_vx_tu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmul_vx_tu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmul_vx_tum-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmul_vx_tum-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmul_vx_tum-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmul_vx_tumu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmul_vx_tumu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmul_vx_tumu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmulsu_vv-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmulsu_vv-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmulsu_vv-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmulsu_vv_m-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmulsu_vv_m-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmulsu_vv_m-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmulsu_vv_mu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmulsu_vv_mu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmulsu_vv_mu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmulsu_vv_tu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmulsu_vv_tu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmulsu_vv_tu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmulsu_vv_tum-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmulsu_vv_tum-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmulsu_vv_tum-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmulsu_vv_tumu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmulsu_vv_tumu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmulsu_vv_tumu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmulsu_vx-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmulsu_vx-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmulsu_vx-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmulsu_vx_m-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmulsu_vx_m-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmulsu_vx_m-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmulsu_vx_mu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmulsu_vx_mu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmulsu_vx_mu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmulsu_vx_tu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmulsu_vx_tu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmulsu_vx_tu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmulsu_vx_tum-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmulsu_vx_tum-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmulsu_vx_tum-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmulsu_vx_tumu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmulsu_vx_tumu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmulsu_vx_tumu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmulu_vv-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmulu_vv-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmulu_vv-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmulu_vv_m-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmulu_vv_m-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmulu_vv_m-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmulu_vv_mu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmulu_vv_mu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmulu_vv_mu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmulu_vv_tu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmulu_vv_tu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmulu_vv_tu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmulu_vv_tum-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmulu_vv_tum-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmulu_vv_tum-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmulu_vv_tumu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmulu_vv_tumu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmulu_vv_tumu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmulu_vx-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmulu_vx-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmulu_vx-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmulu_vx_m-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmulu_vx_m-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmulu_vx_m-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmulu_vx_mu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmulu_vx_mu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmulu_vx_mu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmulu_vx_tu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmulu_vx_tu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmulu_vx_tu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmulu_vx_tum-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmulu_vx_tum-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmulu_vx_tum-3.c | 111 + .../gcc.target/riscv/rvv/base/vwmulu_vx_tumu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwmulu_vx_tumu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwmulu_vx_tumu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_vv-1.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_vv-2.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_vv-3.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_vv_m-1.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_vv_m-2.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_vv_m-3.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_vv_mu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_vv_mu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_vv_mu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_vv_tu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_vv_tu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_vv_tu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_vv_tum-1.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_vv_tum-2.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_vv_tum-3.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_vv_tumu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_vv_tumu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_vv_tumu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_vx-1.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_vx-2.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_vx-3.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_vx_m-1.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_vx_m-2.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_vx_m-3.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_vx_mu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_vx_mu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_vx_mu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_vx_tu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_vx_tu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_vx_tu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_vx_tum-1.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_vx_tum-2.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_vx_tum-3.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_vx_tumu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_vx_tumu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_vx_tumu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_wv-1.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_wv-2.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_wv-3.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_wv_m-1.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_wv_m-2.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_wv_m-3.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_wv_mu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_wv_mu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_wv_mu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_wv_tu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_wv_tu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_wv_tu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_wv_tum-1.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_wv_tum-2.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_wv_tum-3.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_wv_tumu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_wv_tumu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_wv_tumu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_wx-1.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_wx-2.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_wx-3.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_wx_m-1.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_wx_m-2.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_wx_m-3.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_wx_mu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_wx_mu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_wx_mu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_wx_tu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_wx_tu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_wx_tu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_wx_tum-1.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_wx_tum-2.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_wx_tum-3.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_wx_tumu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_wx_tumu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwsub_wx_tumu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_vv-1.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_vv-2.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_vv-3.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_vv_m-1.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_vv_m-2.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_vv_m-3.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_vv_mu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_vv_mu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_vv_mu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_vv_tu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_vv_tu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_vv_tu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_vv_tum-1.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_vv_tum-2.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_vv_tum-3.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_vv_tumu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_vv_tumu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_vv_tumu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_vx-1.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_vx-2.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_vx-3.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_vx_m-1.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_vx_m-2.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_vx_m-3.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_vx_mu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_vx_mu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_vx_mu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_vx_tu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_vx_tu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_vx_tu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_vx_tum-1.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_vx_tum-2.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_vx_tum-3.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_vx_tumu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_vx_tumu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_vx_tumu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_wv-1.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_wv-2.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_wv-3.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_wv_m-1.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_wv_m-2.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_wv_m-3.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_wv_mu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_wv_mu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_wv_mu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_wv_tu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_wv_tu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_wv_tu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_wv_tum-1.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_wv_tum-2.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_wv_tum-3.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_wv_tumu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_wv_tumu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_wv_tumu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_wx-1.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_wx-2.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_wx-3.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_wx_m-1.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_wx_m-2.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_wx_m-3.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_wx_mu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_wx_mu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_wx_mu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_wx_tu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_wx_tu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_wx_tu-3.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_wx_tum-1.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_wx_tum-2.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_wx_tum-3.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_wx_tumu-1.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_wx_tumu-2.c | 111 + .../gcc.target/riscv/rvv/base/vwsubu_wx_tumu-3.c | 111 + .../gcc.target/riscv/rvv/base/vxor_vv-1.c | 292 + .../gcc.target/riscv/rvv/base/vxor_vv-2.c | 292 + .../gcc.target/riscv/rvv/base/vxor_vv-3.c | 292 + .../gcc.target/riscv/rvv/base/vxor_vv_m-1.c | 292 + .../gcc.target/riscv/rvv/base/vxor_vv_m-2.c | 292 + .../gcc.target/riscv/rvv/base/vxor_vv_m-3.c | 292 + .../gcc.target/riscv/rvv/base/vxor_vv_mu-1.c | 292 + .../gcc.target/riscv/rvv/base/vxor_vv_mu-2.c | 292 + .../gcc.target/riscv/rvv/base/vxor_vv_mu-3.c | 292 + .../gcc.target/riscv/rvv/base/vxor_vv_tu-1.c | 292 + .../gcc.target/riscv/rvv/base/vxor_vv_tu-2.c | 292 + .../gcc.target/riscv/rvv/base/vxor_vv_tu-3.c | 292 + .../gcc.target/riscv/rvv/base/vxor_vv_tum-1.c | 292 + .../gcc.target/riscv/rvv/base/vxor_vv_tum-2.c | 292 + .../gcc.target/riscv/rvv/base/vxor_vv_tum-3.c | 292 + .../gcc.target/riscv/rvv/base/vxor_vv_tumu-1.c | 292 + .../gcc.target/riscv/rvv/base/vxor_vv_tumu-2.c | 292 + .../gcc.target/riscv/rvv/base/vxor_vv_tumu-3.c | 292 + .../gcc.target/riscv/rvv/base/vxor_vx_m_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vxor_vx_m_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vxor_vx_m_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vxor_vx_m_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vxor_vx_m_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vxor_vx_m_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vxor_vx_mu_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vxor_vx_mu_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vxor_vx_mu_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vxor_vx_mu_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vxor_vx_mu_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vxor_vx_mu_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vxor_vx_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vxor_vx_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vxor_vx_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vxor_vx_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vxor_vx_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vxor_vx_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vxor_vx_tu_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vxor_vx_tu_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vxor_vx_tu_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vxor_vx_tu_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vxor_vx_tu_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vxor_vx_tu_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vxor_vx_tum_rv32-1.c | 289 + .../gcc.target/riscv/rvv/base/vxor_vx_tum_rv32-2.c | 289 + .../gcc.target/riscv/rvv/base/vxor_vx_tum_rv32-3.c | 289 + .../gcc.target/riscv/rvv/base/vxor_vx_tum_rv64-1.c | 292 + .../gcc.target/riscv/rvv/base/vxor_vx_tum_rv64-2.c | 292 + .../gcc.target/riscv/rvv/base/vxor_vx_tum_rv64-3.c | 292 + .../riscv/rvv/base/vxor_vx_tumu_rv32-1.c | 289 + .../riscv/rvv/base/vxor_vx_tumu_rv32-2.c | 289 + .../riscv/rvv/base/vxor_vx_tumu_rv32-3.c | 289 + .../riscv/rvv/base/vxor_vx_tumu_rv64-1.c | 292 + .../riscv/rvv/base/vxor_vx_tumu_rv64-2.c | 292 + .../riscv/rvv/base/vxor_vx_tumu_rv64-3.c | 292 + .../gcc.target/riscv/rvv/base/vzext_vf2-1.c | 111 + .../gcc.target/riscv/rvv/base/vzext_vf2-2.c | 111 + .../gcc.target/riscv/rvv/base/vzext_vf2-3.c | 111 + .../gcc.target/riscv/rvv/base/vzext_vf2_m-1.c | 111 + .../gcc.target/riscv/rvv/base/vzext_vf2_m-2.c | 111 + .../gcc.target/riscv/rvv/base/vzext_vf2_m-3.c | 111 + .../gcc.target/riscv/rvv/base/vzext_vf2_mu-1.c | 111 + .../gcc.target/riscv/rvv/base/vzext_vf2_mu-2.c | 111 + .../gcc.target/riscv/rvv/base/vzext_vf2_mu-3.c | 111 + .../gcc.target/riscv/rvv/base/vzext_vf2_tu-1.c | 111 + .../gcc.target/riscv/rvv/base/vzext_vf2_tu-2.c | 111 + .../gcc.target/riscv/rvv/base/vzext_vf2_tu-3.c | 111 + .../gcc.target/riscv/rvv/base/vzext_vf2_tum-1.c | 111 + .../gcc.target/riscv/rvv/base/vzext_vf2_tum-2.c | 111 + .../gcc.target/riscv/rvv/base/vzext_vf2_tum-3.c | 111 + .../gcc.target/riscv/rvv/base/vzext_vf2_tumu-1.c | 111 + .../gcc.target/riscv/rvv/base/vzext_vf2_tumu-2.c | 111 + .../gcc.target/riscv/rvv/base/vzext_vf2_tumu-3.c | 111 + .../gcc.target/riscv/rvv/base/vzext_vf4-1.c | 69 + .../gcc.target/riscv/rvv/base/vzext_vf4-2.c | 69 + .../gcc.target/riscv/rvv/base/vzext_vf4-3.c | 69 + .../gcc.target/riscv/rvv/base/vzext_vf4_m-1.c | 69 + .../gcc.target/riscv/rvv/base/vzext_vf4_m-2.c | 69 + .../gcc.target/riscv/rvv/base/vzext_vf4_m-3.c | 69 + .../gcc.target/riscv/rvv/base/vzext_vf4_mu-1.c | 69 + .../gcc.target/riscv/rvv/base/vzext_vf4_mu-2.c | 69 + .../gcc.target/riscv/rvv/base/vzext_vf4_mu-3.c | 69 + .../gcc.target/riscv/rvv/base/vzext_vf4_tu-1.c | 69 + .../gcc.target/riscv/rvv/base/vzext_vf4_tu-2.c | 69 + .../gcc.target/riscv/rvv/base/vzext_vf4_tu-3.c | 69 + .../gcc.target/riscv/rvv/base/vzext_vf4_tum-1.c | 69 + .../gcc.target/riscv/rvv/base/vzext_vf4_tum-2.c | 69 + .../gcc.target/riscv/rvv/base/vzext_vf4_tum-3.c | 69 + .../gcc.target/riscv/rvv/base/vzext_vf4_tumu-1.c | 69 + .../gcc.target/riscv/rvv/base/vzext_vf4_tumu-2.c | 69 + .../gcc.target/riscv/rvv/base/vzext_vf4_tumu-3.c | 69 + .../gcc.target/riscv/rvv/base/vzext_vf8-1.c | 34 + .../gcc.target/riscv/rvv/base/vzext_vf8-2.c | 34 + .../gcc.target/riscv/rvv/base/vzext_vf8-3.c | 34 + .../gcc.target/riscv/rvv/base/vzext_vf8_m-1.c | 34 + .../gcc.target/riscv/rvv/base/vzext_vf8_m-2.c | 34 + .../gcc.target/riscv/rvv/base/vzext_vf8_m-3.c | 34 + .../gcc.target/riscv/rvv/base/vzext_vf8_mu-1.c | 34 + .../gcc.target/riscv/rvv/base/vzext_vf8_mu-2.c | 34 + .../gcc.target/riscv/rvv/base/vzext_vf8_mu-3.c | 34 + .../gcc.target/riscv/rvv/base/vzext_vf8_tu-1.c | 34 + .../gcc.target/riscv/rvv/base/vzext_vf8_tu-2.c | 34 + .../gcc.target/riscv/rvv/base/vzext_vf8_tu-3.c | 34 + .../gcc.target/riscv/rvv/base/vzext_vf8_tum-1.c | 34 + .../gcc.target/riscv/rvv/base/vzext_vf8_tum-2.c | 34 + .../gcc.target/riscv/rvv/base/vzext_vf8_tum-3.c | 34 + .../gcc.target/riscv/rvv/base/vzext_vf8_tumu-1.c | 34 + .../gcc.target/riscv/rvv/base/vzext_vf8_tumu-2.c | 34 + .../gcc.target/riscv/rvv/base/vzext_vf8_tumu-3.c | 34 + gcc/testsuite/gcc.target/riscv/shorten-memrefs-1.c | 4 +- gcc/testsuite/gcc.target/riscv/shorten-memrefs-2.c | 8 +- gcc/testsuite/gcc.target/riscv/shorten-memrefs-3.c | 2 +- gcc/testsuite/gcc.target/riscv/shorten-memrefs-4.c | 4 +- gcc/testsuite/gcc.target/riscv/shorten-memrefs-5.c | 8 +- gcc/testsuite/gcc.target/riscv/shorten-memrefs-6.c | 2 +- gcc/testsuite/gcc.target/riscv/shorten-memrefs-8.c | 4 +- gcc/testsuite/gcc.target/s390/preserve-args-1.c | 17 + gcc/testsuite/gcc.target/s390/preserve-args-2.c | 19 + gcc/testsuite/gcc.target/s390/preserve-args-3.c | 19 + .../gfortran.dg/ISO_Fortran_binding_14.f90 | 2 +- .../gfortran.dg/bind_c_array_params_2.f90 | 4 +- .../goacc/privatization-1-compute-loop.f90 | 6 +- .../goacc/privatization-1-routine_gang-loop.f90 | 3 +- gcc/testsuite/gfortran.dg/gomp/loop-2.f90 | 5 + gcc/testsuite/gfortran.dg/gomp/loop-5.f90 | 84 + gcc/testsuite/gfortran.dg/gomp/openmp-simd-8.f90 | 25 + gcc/testsuite/gfortran.dg/gomp/taskloop-2.f90 | 2 + gcc/testsuite/gfortran.dg/noinline.f90 | 23 + gcc/testsuite/gfortran.dg/noreturn-1.f90 | 62 + gcc/testsuite/gfortran.dg/noreturn-2.f90 | 53 + gcc/testsuite/gfortran.dg/noreturn-3.f90 | 14 + gcc/testsuite/gfortran.dg/noreturn-4.f90 | 11 + gcc/testsuite/gfortran.dg/noreturn-5.f90 | 9 + gcc/testsuite/gfortran.dg/pr103259.f90 | 11 + gcc/testsuite/gfortran.dg/pr103475.f90 | 11 + gcc/testsuite/gfortran.dg/pr103608.f90 | 14 + gcc/testsuite/gfortran.dg/pr103779.f90 | 18 + gcc/testsuite/gfortran.dg/pr104554.f90 | 11 + gcc/testsuite/gfortran.dg/pr108527.f90 | 2 +- gcc/testsuite/gfortran.dg/pr108592.f90 | 8 + gcc/testsuite/gfortran.dg/pr96486.f90 | 2 +- gcc/testsuite/gfortran.dg/save_7.f90 | 17 + gcc/testsuite/gfortran.dg/weak-1.f90 | 7 + gcc/testsuite/gnat.dg/shift2.adb | 8 + gcc/testsuite/lib/gm2.exp | 3 + gcc/testsuite/lib/target-supports.exp | 2 +- gcc/testsuite/obj-c++.dg/proto-lossage-4.mm | 14 +- gcc/testsuite/objc.dg/proto-lossage-4.m | 6 +- gcc/testsuite/objc/execute/execute.exp | 1 + gcc/testsuite/rust/compile/issue-1361.rs | 8 + gcc/testsuite/rust/compile/issue-1422.rs | 7 + gcc/timevar.h | 4 +- gcc/toplev.cc | 2 +- gcc/tree-cfg.cc | 7 +- gcc/tree-chrec.h | 22 +- gcc/tree-data-ref.h | 24 +- gcc/tree-into-ssa.cc | 4 + gcc/tree-iterator.h | 16 +- gcc/tree-nested.cc | 32 +- gcc/tree-outof-ssa.h | 4 +- gcc/tree-phinodes.h | 4 +- gcc/tree-scalar-evolution.h | 6 +- gcc/tree-sra.h | 2 +- gcc/tree-ssa-alias.cc | 10 +- gcc/tree-ssa-alias.h | 2 +- gcc/tree-ssa-dce.cc | 25 +- gcc/tree-ssa-dse.cc | 2 +- gcc/tree-ssa-forwprop.cc | 3 +- gcc/tree-ssa-live.h | 24 +- gcc/tree-ssa-loop-im.cc | 4 +- gcc/tree-ssa-loop-manip.h | 2 +- gcc/tree-ssa-loop.h | 2 +- gcc/tree-ssa-operands.h | 4 +- gcc/tree-ssa-propagate.h | 4 +- gcc/tree-ssa-reassoc.cc | 9 + gcc/tree-ssa-sccvn.cc | 121 +- gcc/tree-ssa-sccvn.h | 10 +- gcc/tree-ssa.cc | 2 + gcc/tree-ssa.h | 12 +- gcc/tree-ssanames.h | 10 +- gcc/tree-streamer.h | 8 +- gcc/tree-switch-conversion.h | 2 +- gcc/tree-vect-loop-manip.cc | 44 + gcc/tree-vect-loop.cc | 72 +- gcc/tree-vect-patterns.cc | 20 +- gcc/tree-vect-stmts.cc | 63 +- gcc/tree-vectorizer.h | 67 +- gcc/tree-vrp.cc | 4 + gcc/tree.cc | 9 +- gcc/tree.def | 3 +- gcc/tree.h | 88 +- gcc/ubsan.cc | 2 +- gcc/value-query.cc | 10 +- gcc/value-query.h | 4 +- gcc/value-range.cc | 11 +- gcc/value-relation.cc | 34 + gcc/value-relation.h | 1 + gcc/wide-int.h | 2 +- include/ChangeLog | 4 + include/gomp-constants.h | 2 +- libcpp/po/ChangeLog | 4 + libcpp/po/cpplib.pot | 541 +- libgcc/ChangeLog | 10 + libgcc/config.host | 3 + libgcc/config/arm/pr-support.c | 6 + libgcc/config/{aarch64 => riscv}/value-unwind.h | 28 +- libgm2/ChangeLog | 46 + libgm2/libm2cor/Makefile.am | 7 +- libgm2/libm2cor/Makefile.in | 7 +- libgm2/libm2iso/Makefile.am | 7 +- libgm2/libm2iso/Makefile.in | 7 +- libgm2/libm2iso/RTco.cc | 3 +- libgm2/libm2log/Makefile.am | 7 +- libgm2/libm2log/Makefile.in | 7 +- libgm2/libm2min/Makefile.am | 5 - libgm2/libm2min/Makefile.in | 5 - libgm2/libm2pim/Makefile.am | 6 +- libgm2/libm2pim/Makefile.in | 6 +- libgomp/ChangeLog | 103 + libgomp/config/gcn/libgomp-gcn.h | 34 + libgomp/config/gcn/team.c | 8 +- libgomp/libgomp.h | 5 +- libgomp/libgomp.texi | 48 +- libgomp/plugin/plugin-gcn.c | 255 +- libgomp/target.c | 26 +- libgomp/testsuite/libgomp.fortran/allocate-3.f90 | 4 +- libgomp/testsuite/libgomp.fortran/allocate-4.f90 | 42 + .../libgomp.fortran/non-rectangular-loop-1.f90 | 668 + .../libgomp.fortran/non-rectangular-loop-1a.f90 | 374 + .../libgomp.fortran/non-rectangular-loop-2.f90 | 243 + .../libgomp.fortran/non-rectangular-loop-3.f90 | 212 + .../libgomp.fortran/non-rectangular-loop-4.f90 | 215 + .../libgomp.fortran/non-rectangular-loop-5.f90 | 28 + .../libgomp.fortran/reverse-offload-5.f90 | 6 +- .../libgomp.fortran/reverse-offload-6.f90 | 34 + .../libgomp.fortran/target-enter-data-3.f90 | 22 + .../target-nowait-array-section.f90 | 2 +- libiberty/ChangeLog | 5 + libiberty/lrealpath.c | 199 +- libphobos/ChangeLog | 5 + libphobos/libdruntime/core/sys/freebsd/config.d | 5 +- libsanitizer/ChangeLog | 18 + libsanitizer/hwasan/hwasan_setjmp_x86_64.S | 3 +- libstdc++-v3/ChangeLog | 443 + libstdc++-v3/Makefile.am | 4 +- libstdc++-v3/Makefile.in | 4 +- libstdc++-v3/acinclude.m4 | 8 +- libstdc++-v3/config/abi/pre/gnu.ver | 7 + libstdc++-v3/config/os/generic/error_constants.h | 2 + libstdc++-v3/config/os/gnu-linux/os_defines.h | 22 +- libstdc++-v3/configure | 8 +- libstdc++-v3/doc/doxygen/user.cfg.in | 6 +- libstdc++-v3/doc/html/index.html | 4 +- libstdc++-v3/doc/html/manual/abi.html | 2 +- libstdc++-v3/doc/html/manual/associative.html | 2 +- libstdc++-v3/doc/html/manual/configure.html | 5 +- libstdc++-v3/doc/html/manual/debug.html | 2 +- .../doc/html/manual/documentation_hacking.html | 2 +- libstdc++-v3/doc/html/manual/facets.html | 4 +- libstdc++-v3/doc/html/manual/memory.html | 2 +- .../doc/html/manual/policy_data_structures.html | 4 +- libstdc++-v3/doc/html/manual/status.html | 8 +- libstdc++-v3/doc/html/manual/test.html | 12 + libstdc++-v3/doc/html/manual/using.html | 6 + .../doc/html/manual/using_dynamic_or_shared.html | 39 +- libstdc++-v3/doc/html/manual/using_exceptions.html | 2 +- libstdc++-v3/doc/xml/manual/abi.xml | 2 +- libstdc++-v3/doc/xml/manual/configure.xml | 5 +- libstdc++-v3/doc/xml/manual/containers.xml | 2 +- libstdc++-v3/doc/xml/manual/ctype.xml | 2 +- libstdc++-v3/doc/xml/manual/debug.xml | 2 +- .../doc/xml/manual/documentation_hacking.xml | 2 +- .../xml/manual/policy_data_structures_biblio.xml | 4 +- libstdc++-v3/doc/xml/manual/status_cxx2017.xml | 2 +- libstdc++-v3/doc/xml/manual/status_cxx2023.xml | 11 + libstdc++-v3/doc/xml/manual/test.xml | 14 + libstdc++-v3/doc/xml/manual/using.xml | 66 +- libstdc++-v3/doc/xml/manual/using_exceptions.xml | 2 +- libstdc++-v3/include/Makefile.am | 1 + libstdc++-v3/include/Makefile.in | 1 + libstdc++-v3/include/bits/basic_string.h | 11 +- libstdc++-v3/include/bits/c++config | 16 +- libstdc++-v3/include/bits/fs_ops.h | 4 +- libstdc++-v3/include/bits/fs_path.h | 10 +- libstdc++-v3/include/bits/ranges_algo.h | 228 + libstdc++-v3/include/bits/regex_automaton.h | 2 +- libstdc++-v3/include/bits/regex_automaton.tcc | 18 +- libstdc++-v3/include/bits/regex_scanner.tcc | 60 +- libstdc++-v3/include/bits/stl_pair.h | 112 +- libstdc++-v3/include/experimental/bits/fs_ops.h | 4 +- libstdc++-v3/include/experimental/bits/simd.h | 245 +- .../include/experimental/bits/simd_builtin.h | 351 +- .../include/experimental/bits/simd_converter.h | 22 +- .../include/experimental/bits/simd_detail.h | 3 + .../include/experimental/bits/simd_fixed_size.h | 265 +- libstdc++-v3/include/experimental/bits/simd_math.h | 56 +- libstdc++-v3/include/experimental/bits/simd_neon.h | 14 +- libstdc++-v3/include/experimental/bits/simd_x86.h | 143 +- libstdc++-v3/include/experimental/optional | 2 +- .../include/experimental/synchronized_value | 100 + libstdc++-v3/include/ext/throw_allocator.h | 8 +- libstdc++-v3/include/pstl/algorithm_fwd.h | 36 +- libstdc++-v3/include/pstl/algorithm_impl.h | 28 +- libstdc++-v3/include/pstl/execution_impl.h | 8 +- libstdc++-v3/include/pstl/glue_algorithm_impl.h | 2 +- libstdc++-v3/include/pstl/glue_numeric_defs.h | 2 +- libstdc++-v3/include/pstl/numeric_impl.h | 4 +- libstdc++-v3/include/pstl/parallel_backend_tbb.h | 4 +- libstdc++-v3/include/pstl/unseq_backend_simd.h | 12 +- libstdc++-v3/include/std/atomic | 39 + libstdc++-v3/include/std/format | 101 +- libstdc++-v3/include/std/mutex | 8 +- libstdc++-v3/include/std/sstream | 32 +- libstdc++-v3/include/std/tuple | 8 +- libstdc++-v3/include/std/type_traits | 28 +- libstdc++-v3/include/std/variant | 4 +- libstdc++-v3/libsupc++/cxxabi_init_exception.h | 5 +- libstdc++-v3/src/Makefile.am | 16 +- libstdc++-v3/src/Makefile.in | 22 +- libstdc++-v3/src/c++11/Makefile.am | 16 +- libstdc++-v3/src/c++11/Makefile.in | 37 +- libstdc++-v3/src/c++11/random.cc | 2 + libstdc++-v3/src/c++11/system_error.cc | 9 + libstdc++-v3/src/c++17/Makefile.am | 4 + libstdc++-v3/src/c++17/Makefile.in | 6 +- libstdc++-v3/src/c++17/fs_ops.cc | 6 +- libstdc++-v3/src/c++17/fs_path.cc | 13 + libstdc++-v3/src/c++20/Makefile.am | 4 + libstdc++-v3/src/c++20/Makefile.in | 6 +- libstdc++-v3/src/c++98/Makefile.am | 4 + libstdc++-v3/src/c++98/Makefile.in | 6 +- libstdc++-v3/src/filesystem/ops-common.h | 9 +- libstdc++-v3/testsuite/17_intro/names.cc | 21 +- libstdc++-v3/testsuite/17_intro/names_pstl.cc | 18 + .../deprecated-2b.cc} | 9 +- .../aligned_storage/requirements/alias_decl.cc | 3 + .../requirements/explicit_instantiation.cc | 3 + .../testsuite/20_util/aligned_storage/value.cc | 2 + libstdc++-v3/testsuite/20_util/aligned_union/1.cc | 2 + .../deprecated-2b.cc} | 9 +- .../aligned_union/requirements/alias_decl.cc | 3 + .../testsuite/20_util/pair/dangling_ref.cc | 67 + libstdc++-v3/testsuite/20_util/variant/lwg3585.cc | 16 + .../basic_string/allocator/char/move_assign.cc | 52 + libstdc++-v3/testsuite/25_algorithms/contains/1.cc | 33 + .../testsuite/25_algorithms/contains_subrange/1.cc | 37 + .../testsuite/25_algorithms/find_last/1.cc | 90 + .../testsuite/25_algorithms/find_last_if/1.cc | 92 + .../testsuite/25_algorithms/find_last_if_not/1.cc | 92 + libstdc++-v3/testsuite/25_algorithms/iota/1.cc | 29 + .../27_io/basic_istringstream/view/char/1.cc | 1 - .../27_io/basic_istringstream/view/wchar_t/1.cc | 1 - .../27_io/basic_ostringstream/view/char/1.cc | 1 - .../27_io/basic_ostringstream/view/wchar_t/1.cc | 1 - .../testsuite/27_io/basic_stringbuf/view/char/1.cc | 1 - .../27_io/basic_stringbuf/view/wchar_t/1.cc | 1 - .../27_io/basic_stringstream/view/char/1.cc | 1 - .../27_io/basic_stringstream/view/wchar_t/1.cc | 1 - .../testsuite/27_io/filesystem/path/108636.cc | 8 + .../29_atomics/atomic_flag/test/explicit.cc | 26 +- .../29_atomics/atomic_flag/test/implicit.cc | 26 +- .../29_atomics/atomic_flag/wait_notify/1.cc | 26 +- libstdc++-v3/testsuite/experimental/simd/README.md | 10 +- .../experimental/simd/generate_makefile.sh | 24 +- .../testsuite/experimental/simd/tests/abs.cc | 4 +- .../experimental/simd/tests/algorithms.cc | 3 +- .../experimental/simd/tests/bits/conversions.h | 25 +- .../testsuite/experimental/simd/tests/bits/main.h | 87 + .../experimental/simd/tests/bits/make_vec.h | 10 + .../experimental/simd/tests/bits/mathreference.h | 3 + .../experimental/simd/tests/bits/test_values.h | 6 + .../experimental/simd/tests/bits/verify.h | 66 +- .../testsuite/experimental/simd/tests/broadcast.cc | 3 +- .../testsuite/experimental/simd/tests/casts.cc | 4 +- .../experimental/simd/tests/fpclassify.cc | 4 +- .../testsuite/experimental/simd/tests/frexp.cc | 4 +- .../testsuite/experimental/simd/tests/generator.cc | 3 +- .../experimental/simd/tests/hypot3_fma.cc | 4 +- .../experimental/simd/tests/integer_operators.cc | 5 +- .../simd/tests/ldexp_scalbn_scalbln_modf.cc | 4 +- .../testsuite/experimental/simd/tests/loadstore.cc | 4 +- .../testsuite/experimental/simd/tests/logarithm.cc | 5 +- .../experimental/simd/tests/mask_broadcast.cc | 3 +- .../experimental/simd/tests/mask_conversions.cc | 2 +- .../experimental/simd/tests/mask_implicit_cvt.cc | 3 +- .../experimental/simd/tests/mask_loadstore.cc | 29 +- .../experimental/simd/tests/mask_operator_cvt.cc | 3 +- .../experimental/simd/tests/mask_operators.cc | 3 +- .../experimental/simd/tests/mask_reductions.cc | 30 +- .../testsuite/experimental/simd/tests/math_1arg.cc | 3 +- .../testsuite/experimental/simd/tests/math_2arg.cc | 4 +- .../experimental/simd/tests/operator_cvt.cc | 3 +- .../testsuite/experimental/simd/tests/operators.cc | 14 +- .../experimental/simd/tests/reductions.cc | 4 +- .../testsuite/experimental/simd/tests/remqo.cc | 4 +- .../testsuite/experimental/simd/tests/simd.cc | 2 +- .../testsuite/experimental/simd/tests/sincos.cc | 6 +- .../experimental/simd/tests/split_concat.cc | 4 +- .../testsuite/experimental/simd/tests/splits.cc | 2 +- .../experimental/simd/tests/trigonometric.cc | 4 +- .../experimental/simd/tests/trunc_ceil_floor.cc | 3 +- .../testsuite/experimental/simd/tests/where.cc | 4 +- .../testsuite/experimental/synchronized_value.cc | 42 + .../testsuite/std/format/arguments/lwg3810.cc | 25 + libstdc++-v3/testsuite/std/time/hh_mm_ss/1.cc | 2 +- 6813 files changed, 1151495 insertions(+), 18938 deletions(-) copy gcc/m2/mc-boot/{GMemUtils.h => GRTentity.h} (65%) rename gcc/rust/hir/tree/{rust-hir-full-test.cc => rust-hir.cc} (100%) create mode 100644 gcc/testsuite/c-c++-common/Wdangling-pointer-10.c create mode 100644 gcc/testsuite/c-c++-common/Wdangling-pointer-9.c create mode 100644 gcc/testsuite/c-c++-common/cpp/delimited-escape-seq-8.c create mode 100644 gcc/testsuite/c-c++-common/pr108605.c create mode 100644 gcc/testsuite/g++.dg/DRs/dr2475.C create mode 100644 gcc/testsuite/g++.dg/DRs/dr2478.C create mode 100644 gcc/testsuite/g++.dg/DRs/dr2530.C create mode 100644 gcc/testsuite/g++.dg/DRs/dr2673.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/constexpr-nsdmi2.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/overload-conv-5.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/overload5.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/overload5a.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/overload6.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/pr108698.C copy gcc/testsuite/g++.dg/cpp0x/{variadic-alias2.C => variadic-alias8.C} (81%) create mode 100644 gcc/testsuite/g++.dg/cpp0x/variadic184.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/constexpr-108158.C create mode 100644 gcc/testsuite/g++.dg/cpp1z/aggr-base13.C create mode 100644 gcc/testsuite/g++.dg/cpp23/static-operator-call6.C create mode 100644 gcc/testsuite/g++.dg/cpp2a/concepts-dtor1.C create mode 100644 gcc/testsuite/g++.dg/cpp2a/concepts-pr108579.C create mode 100644 gcc/testsuite/g++.dg/gomp/pr108607.C create mode 100644 gcc/testsuite/g++.dg/ipa/pr108509.C create mode 100644 gcc/testsuite/g++.dg/opt/is_constant_evaluated1.C create mode 100644 gcc/testsuite/g++.dg/opt/is_constant_evaluated2.C create mode 100644 gcc/testsuite/g++.dg/pr108520.C create mode 100644 gcc/testsuite/g++.dg/template/call9.C create mode 100644 gcc/testsuite/g++.dg/template/typename24.C create mode 100644 gcc/testsuite/g++.dg/template/typename25.C create mode 100644 gcc/testsuite/g++.dg/template/typename25a.C create mode 100644 gcc/testsuite/g++.dg/template/typename26.C create mode 100644 gcc/testsuite/g++.dg/torture/pr108647.C create mode 100644 gcc/testsuite/g++.dg/warn/Wduplicated-cond3.C create mode 100644 gcc/testsuite/g++.dg/warn/Wduplicated-cond4.C create mode 100644 gcc/testsuite/g++.dg/warn/Wduplicated-cond5.C create mode 100644 gcc/testsuite/g++.dg/warn/Wlogical-op-4.C create mode 100644 gcc/testsuite/g++.dg/warn/changes-meaning2.C create mode 100644 gcc/testsuite/g++.dg/warn/changes-meaning3.C create mode 100644 gcc/testsuite/g++.target/i386/pr108711.C create mode 100644 gcc/testsuite/g++.target/loongarch/bytepick.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/exception-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tum_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tum_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tum_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tum_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tum_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tum_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tumu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tumu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tumu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tumu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tumu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tumu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_tum_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_tum_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_tum_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_tum_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_tum_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_tum_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_tumu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_tumu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_tumu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_tumu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_tumu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaaddu_vx_tumu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tum_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_tumu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tum_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tum_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tum_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tum_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tum_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tum_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tumu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tumu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tumu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tumu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tumu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tumu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tum_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tum_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tum_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tum_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tum_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tum_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tumu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tumu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tumu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tumu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tumu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasub_vx_tumu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tum_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tum_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tum_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tum_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tum_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tum_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tumu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tumu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tumu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tumu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tumu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tumu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vx_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vx_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vx_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vx_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vx_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vx_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vx_tum_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vx_tum_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vx_tum_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vx_tum_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vx_tum_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vx_tum_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vx_tumu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vx_tumu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vx_tumu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vx_tumu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vx_tumu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vx_tumu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tum_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tum_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tum_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tum_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tum_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tum_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tumu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tumu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tumu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tumu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tumu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_tumu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_tum_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_tum_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_tum_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_tum_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_tum_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_tum_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_tumu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_tumu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_tumu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_tumu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_tumu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_tumu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vvm-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vvm-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vvm-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vxm_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vxm_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vxm_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vxm_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vxm_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadc_vxm_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_tum_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_tum_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_tum_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_tumu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_tumu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmadd_vx_tumu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tum_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tum_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tum_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tum_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tum_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tum_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tumu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tumu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tumu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tumu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tumu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tumu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vx_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vx_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vx_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vx_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vx_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vx_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vx_tum_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vx_tum_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vx_tum_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vx_tum_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vx_tum_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vx_tum_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vx_tumu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vx_tumu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vx_tumu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vx_tumu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vx_tumu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vx_tumu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vvm-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vvm-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vvm-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vvm-4.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vvm-5.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vvm-6.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vvm_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vvm_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vvm_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vvm_tu-4.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vvm_tu-5.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vvm_tu-6.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vxm_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vxm_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vxm_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vxm_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vxm_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vxm_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vxm_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vxm_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vxm_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vxm_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vxm_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmerge_vxm_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tum_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tum_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tum_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tum_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tum_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tum_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tumu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tumu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tumu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tumu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tumu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_tumu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vx_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vx_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vx_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vx_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vx_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vx_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vx_tum_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vx_tum_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vx_tum_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vx_tum_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vx_tum_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vx_tum_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vx_tumu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vx_tumu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vx_tumu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vx_tumu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vx_tumu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vx_tumu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vvm-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vvm-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vvm-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vxm_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vxm_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vxm_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vxm_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vxm_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbc_vxm_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv_m-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv_m-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv_m-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vx_m_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vx_m_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vx_m_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vx_m_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vx_m_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vx_m_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv_m-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv_m-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv_m-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vx_m_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vx_m_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vx_m_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vx_m_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vx_m_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vx_m_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsge_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vv_m-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vv_m-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vv_m-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vx_m_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vx_m_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vx_m_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vx_m_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vx_m_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vx_m_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgeu_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vv_m-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vv_m-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vv_m-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_m_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_m_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_m_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_m_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_m_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_m_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgt_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vv_m-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vv_m-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vv_m-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_m_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_m_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_m_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_m_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_m_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_m_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsgtu_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsle_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsle_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsle_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsle_vv_m-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsle_vv_m-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsle_vv_m-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsle_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsle_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsle_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsle_vx_m_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsle_vx_m_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsle_vx_m_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsle_vx_m_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsle_vx_m_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsle_vx_m_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsle_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsle_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsle_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsle_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsle_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsle_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsle_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsle_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsle_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsle_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsle_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsle_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsleu_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsleu_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsleu_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsleu_vv_m-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsleu_vv_m-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsleu_vv_m-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsleu_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsleu_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsleu_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsleu_vx_m_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsleu_vx_m_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsleu_vx_m_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsleu_vx_m_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsleu_vx_m_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsleu_vx_m_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsleu_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsleu_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsleu_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsleu_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsleu_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsleu_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsleu_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsleu_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsleu_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsleu_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsleu_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsleu_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmslt_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmslt_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmslt_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmslt_vv_m-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmslt_vv_m-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmslt_vv_m-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmslt_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmslt_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmslt_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmslt_vx_m_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmslt_vx_m_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmslt_vx_m_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmslt_vx_m_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmslt_vx_m_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmslt_vx_m_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmslt_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmslt_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmslt_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmslt_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmslt_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmslt_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmslt_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmslt_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmslt_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmslt_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmslt_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmslt_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsltu_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsltu_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsltu_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsltu_vv_m-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsltu_vv_m-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsltu_vv_m-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsltu_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsltu_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsltu_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsltu_vx_m_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsltu_vx_m_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsltu_vx_m_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsltu_vx_m_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsltu_vx_m_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsltu_vx_m_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsltu_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsltu_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsltu_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsltu_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsltu_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsltu_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsltu_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsltu_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsltu_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsltu_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsltu_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsltu_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsne_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsne_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsne_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsne_vv_m-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsne_vv_m-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsne_vv_m-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsne_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsne_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsne_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsne_vx_m_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsne_vx_m_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsne_vx_m_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsne_vx_m_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsne_vx_m_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsne_vx_m_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsne_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsne_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsne_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsne_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsne_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsne_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsne_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsne_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsne_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsne_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsne_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsne_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tum_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tum_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tum_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tum_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tum_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tum_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tumu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tumu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tumu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tumu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tumu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tumu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tum_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tum_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tum_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tum_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tum_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tum_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tumu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tumu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tumu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tumu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tumu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulh_vx_tumu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhu_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhu_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhu_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhu_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhu_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhu_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhu_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhu_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhu_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhu_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhu_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhu_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhu_vx_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhu_vx_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhu_vx_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhu_vx_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhu_vx_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhu_vx_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhu_vx_tum_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhu_vx_tum_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhu_vx_tum_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhu_vx_tum_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhu_vx_tum_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhu_vx_tum_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhu_vx_tumu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhu_vx_tumu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhu_vx_tumu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhu_vx_tumu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhu_vx_tumu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhu_vx_tumu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmv_v-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmv_v_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmv_v_x_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmv_v_x_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmv_v_x_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmv_v_x_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmv_v_x_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmv_v_x_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclip_vx_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnclipu_vx_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vncvt_x_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vneg_v_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tum_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tum_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tum_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tum_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tum_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tum_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tumu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tumu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tumu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tumu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tumu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tumu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsub_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsub_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsub_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsub_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsub_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsub_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsub_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsub_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsub_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsub_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsub_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsub_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsub_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsub_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsub_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsub_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsub_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsub_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsub_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsub_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsub_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsub_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsub_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsub_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsub_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsub_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsub_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsub_vx_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsub_vx_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsub_vx_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsub_vx_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsub_vx_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsub_vx_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsub_vx_tum_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsub_vx_tum_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsub_vx_tum_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsub_vx_tum_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsub_vx_tum_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsub_vx_tum_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsub_vx_tumu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsub_vx_tumu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsub_vx_tumu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsub_vx_tumu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsub_vx_tumu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnmsub_vx_tumu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsra_vx_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vx_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tum_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tum_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tum_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tum_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tum_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tum_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tumu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tumu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tumu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tumu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tumu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_tumu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vx_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vx_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vx_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vx_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vx_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vx_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vx_tum_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vx_tum_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vx_tum_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vx_tum_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vx_tum_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vx_tum_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vx_tumu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vx_tumu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vx_tumu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vx_tumu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vx_tumu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vx_tumu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tum_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tum_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tum_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tum_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tum_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tum_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tumu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tumu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tumu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tumu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tumu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tumu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tum_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tum_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tum_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tum_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tum_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tum_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tumu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tumu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tumu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tumu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tumu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tumu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vx_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vx_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vx_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vx_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vx_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vx_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vx_tum_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vx_tum_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vx_tum_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vx_tum_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vx_tum_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vx_tum_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vx_tumu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vx_tumu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vx_tumu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vx_tumu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vx_tumu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsadd_vx_tumu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_tum_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_tum_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_tum_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_tum_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_tum_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_tum_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_tumu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_tumu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_tumu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_tumu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_tumu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsaddu_vx_tumu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vvm-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vvm-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vvm-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vvm_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vvm_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vvm_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf2_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf4_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsext_vf8_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vx_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vx_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vx_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vx_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vx_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vx_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vx_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vx_tum_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vx_tum_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vx_tum_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vx_tum_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vx_tum_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vx_tum_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vx_tumu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vx_tumu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vx_tumu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vx_tumu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vx_tumu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsmul_vx_tumu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsra_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsra_vx-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsra_vx-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsra_vx-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsra_vx_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsra_vx_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsra_vx_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsra_vx_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsra_vx_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsra_vx_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsra_vx_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsra_vx_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsra_vx_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsra_vx_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsra_vx_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsra_vx_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vx-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vx-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vx-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vx_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vx_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vx_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vx_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vx_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vx_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vx_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vx_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vx_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vx_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vx_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vx_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssrl_vx_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_tum_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_tum_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_tum_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_tum_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_tum_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_tum_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_tumu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_tumu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_tumu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_tumu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_tumu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssub_vx_tumu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tum_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tum_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tum_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tum_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tum_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tum_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tumu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tumu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tumu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tumu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tumu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssubu_vx_tumu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_vx_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwaddu_wx_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vx_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vx_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vx_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccus_vx_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmulu_vx_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_vx_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tum_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tum_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tum_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tum_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tum_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tum_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tumu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tumu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tumu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tumu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tumu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_tumu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf8_tumu-3.C create mode 100644 gcc/testsuite/gcc.c-torture/compile/dce-inline-asm-1.c create mode 100644 gcc/testsuite/gcc.c-torture/compile/dce-inline-asm-2.c create mode 100644 gcc/testsuite/gcc.c-torture/compile/pr106433.c create mode 100644 gcc/testsuite/gcc.c-torture/compile/pr108638.c create mode 100644 gcc/testsuite/gcc.c-torture/compile/pr108639.c create mode 100644 gcc/testsuite/gcc.c-torture/compile/pr108688-1.c create mode 100644 gcc/testsuite/gcc.c-torture/compile/pr108783.c create mode 100644 gcc/testsuite/gcc.dg/analyzer/allocation-size-multiline-3.c create mode 100644 gcc/testsuite/gcc.dg/analyzer/coreutils-cksum-pr108664.c create mode 100644 gcc/testsuite/gcc.dg/analyzer/coreutils-sum-pr108666.c create mode 100644 gcc/testsuite/gcc.dg/analyzer/deref-before-check-macro-pr108745.c create mode 100644 gcc/testsuite/gcc.dg/analyzer/deref-before-check-macro.c create mode 100644 gcc/testsuite/gcc.dg/analyzer/deref-before-check-qemu-qtest_rsp_args.c create mode 100644 gcc/testsuite/gcc.dg/analyzer/fd-pr108633.c create mode 100644 gcc/testsuite/gcc.dg/analyzer/fread-pr108661.c create mode 100644 gcc/testsuite/gcc.dg/analyzer/null-deref-pr108806-qemu.c create mode 100644 gcc/testsuite/gcc.dg/analyzer/read-pr108661.c create mode 100644 gcc/testsuite/gcc.dg/analyzer/test-alloca.h create mode 100644 gcc/testsuite/gcc.dg/analyzer/torture/uninit-pr108725.c create mode 100644 gcc/testsuite/gcc.dg/analyzer/torture/uninit-pr108733.c create mode 100644 gcc/testsuite/gcc.dg/analyzer/uninit-7.c create mode 100644 gcc/testsuite/gcc.dg/analyzer/uninit-pr108704.c create mode 100644 gcc/testsuite/gcc.dg/analyzer/uninit-pr108806-qemu.c create mode 100644 gcc/testsuite/gcc.dg/asan/pr108777-1.c create mode 100644 gcc/testsuite/gcc.dg/asan/pr108777-2.c create mode 100644 gcc/testsuite/gcc.dg/asan/pr108777-3.c create mode 100644 gcc/testsuite/gcc.dg/asan/pr108777-4.c create mode 100644 gcc/testsuite/gcc.dg/asan/pr108777-5.c create mode 100644 gcc/testsuite/gcc.dg/asan/pr108777-6.c create mode 100644 gcc/testsuite/gcc.dg/builtin-object-size-common.h create mode 100644 gcc/testsuite/gcc.dg/gomp/pr108435.c create mode 100644 gcc/testsuite/gcc.dg/ipa/pr108384.c create mode 100644 gcc/testsuite/gcc.dg/ipa/pr108679.c create mode 100644 gcc/testsuite/gcc.dg/pr106923.c create mode 100644 gcc/testsuite/gcc.dg/pr107300.c create mode 100644 gcc/testsuite/gcc.dg/pr107570.c create mode 100644 gcc/testsuite/gcc.dg/pr108356.c create mode 100644 gcc/testsuite/gcc.dg/pr108359.c create mode 100644 gcc/testsuite/gcc.dg/pr108385.c create mode 100644 gcc/testsuite/gcc.dg/pr108463.c create mode 100644 gcc/testsuite/gcc.dg/pr108573.c create mode 100644 gcc/testsuite/gcc.dg/pr108625.c create mode 100644 gcc/testsuite/gcc.dg/pr108655.c create mode 100644 gcc/testsuite/gcc.dg/pr108657.c create mode 100644 gcc/testsuite/gcc.dg/pr108688.c create mode 100644 gcc/testsuite/gcc.dg/pr108691.c create mode 100644 gcc/testsuite/gcc.dg/pr108692.c create mode 100644 gcc/testsuite/gcc.dg/pr108787.c create mode 100644 gcc/testsuite/gcc.dg/pr108805.c create mode 100644 gcc/testsuite/gcc.dg/torture/pr108737.c create mode 100644 gcc/testsuite/gcc.dg/torture/pr108782.c create mode 100644 gcc/testsuite/gcc.dg/torture/pr108791.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/bool-minus-1.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/bool-minus-2.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr108354-1.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr108684-1.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/ssa-lim-24.c create mode 100644 gcc/testsuite/gcc.dg/vect/pr108316.c create mode 100644 gcc/testsuite/gcc.dg/vect/pr108608.c create mode 100644 gcc/testsuite/gcc.target/aarch64/cpunative/info_19 create mode 100644 gcc/testsuite/gcc.target/aarch64/cpunative/info_20 create mode 100644 gcc/testsuite/gcc.target/aarch64/cpunative/info_21 create mode 100644 gcc/testsuite/gcc.target/aarch64/cpunative/info_22 create mode 100644 gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_19.c create mode 100644 gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_20.c create mode 100644 gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_21.c create mode 100644 gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_22.c delete mode 100644 gcc/testsuite/gcc.target/aarch64/options_set_10.c create mode 100644 gcc/testsuite/gcc.target/aarch64/pr104921-1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/pr104921-2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/pr104921.x create mode 100644 gcc/testsuite/gcc.target/aarch64/pr108508.c create mode 100644 gcc/testsuite/gcc.target/aarch64/pr108589.c create mode 100644 gcc/testsuite/gcc.target/aarch64/pr108601.c create mode 100644 gcc/testsuite/gcc.target/aarch64/pr108681.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/pr108608-1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/mve_vpt.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/pr108443-run.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/pr108443.c create mode 100644 gcc/testsuite/gcc.target/bpf/ldxdw.c create mode 100644 gcc/testsuite/gcc.target/gcn/cond_shift_3.c copy gcc/testsuite/gcc.target/{aarch64/sve => gcn}/cond_shift_3_run.c (91%) create mode 100644 gcc/testsuite/gcc.target/gcn/cond_shift_4.c copy gcc/testsuite/gcc.target/{aarch64/sve => gcn}/cond_shift_4_run.c (91%) create mode 100644 gcc/testsuite/gcc.target/gcn/cond_shift_8.c copy gcc/testsuite/gcc.target/{aarch64/sve => gcn}/cond_shift_8_run.c (92%) create mode 100644 gcc/testsuite/gcc.target/gcn/cond_shift_9.c copy gcc/testsuite/gcc.target/{aarch64/sve => gcn}/cond_shift_9_run.c (92%) create mode 100644 gcc/testsuite/gcc.target/i386/pr103541.c create mode 100644 gcc/testsuite/gcc.target/i386/pr108516-1.c create mode 100644 gcc/testsuite/gcc.target/i386/pr108516-2.c create mode 100644 gcc/testsuite/gcc.target/i386/pr108724.c create mode 100644 gcc/testsuite/gcc.target/i386/pr108774.c copy gcc/testsuite/gcc.target/i386/{pr91188-1b.c => pr108831-1.c} (64%) copy gcc/testsuite/gcc.target/i386/{pr91188-1b.c => pr108831-2.c} (64%) create mode 100644 gcc/testsuite/gcc.target/powerpc/pr108787.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr96373.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vv_constraint-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vv_constraint-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vv_constraint-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vv_constraint-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vv_constraint-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vv_constraint-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vv_constraint-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-10.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-100.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-101.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-102.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-103.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-104.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-105.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-106.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-107.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-108.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-109.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-11.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-110.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-111.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-112.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-113.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-114.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-115.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-116.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-117.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-118.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-119.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-12.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-120.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-121.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-122.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-123.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-124.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-125.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-126.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-127.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-128.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-129.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-13.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-130.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-131.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-132.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-133.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-134.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-135.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-136.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-137.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-138.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-139.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-14.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-140.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-141.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-142.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-143.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-144.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-145.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-146.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-147.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-148.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-149.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-15.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-150.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-151.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-152.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-153.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-154.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-155.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-156.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-157.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-158.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-159.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-160.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-161.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-162.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-163.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-164.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-165.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-166.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-17.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-18.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-19.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-20.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-21.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-22.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-23.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-24.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-25.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-26.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-27.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-28.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-29.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-30.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-31.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-33.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-34.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-35.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-36.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-37.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-38.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-39.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-40.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-41.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-42.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-43.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-44.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-45.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-46.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-47.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-48.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-49.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-50.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-51.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-52.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-53.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-54.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-55.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-56.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-57.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-58.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-59.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-60.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-61.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-62.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-63.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-64.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-65.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-66.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-67.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-68.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-69.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-70.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-71.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-72.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-73.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-74.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-75.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-76.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-77.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-78.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-79.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-80.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-81.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-82.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-83.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-84.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-85.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-86.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-87.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-88.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-89.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-9.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-90.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-91.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-92.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-93.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-94.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-95.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-96.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-97.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-98.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-99.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vx_constraint-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vx_constraint-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vx_constraint-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vx_constraint-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vx_constraint-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vx_constraint-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vx_constraint-7.c copy gcc/testsuite/gcc.target/riscv/rvv/base/{vle-constraint-1.c => unop_v_constra [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/unop_v_constraint-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vx_m_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vx_m_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vx_m_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vx_m_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vx_m_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vx_m_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vx_mu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vx_mu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vx_mu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vx_mu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vx_mu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vx_mu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vx_tu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vx_tu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vx_tu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vx_tu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vx_tu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vx_tu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vx_tum_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vx_tum_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vx_tum_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vx_tum_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vx_tum_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vx_tum_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vx_tumu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vx_tumu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vx_tumu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vx_tumu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vx_tumu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaadd_vx_tumu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vx_m_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vx_m_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vx_m_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vx_m_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vx_m_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vx_m_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vx_mu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vx_mu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vx_mu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vx_mu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vx_mu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vx_mu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vx_tu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vx_tu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vx_tu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vx_tu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vx_tu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vx_tu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vx_tum_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vx_tum_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vx_tum_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vx_tum_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vx_tum_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vx_tum_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vx_tumu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vx_tumu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vx_tumu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vx_tumu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vx_tumu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vaaddu_vx_tumu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vvm-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vvm-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vvm-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vvm_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vvm_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vvm_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_tu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_tu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_tu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_tu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_tu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_tu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_m_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_m_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_m_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_m_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_m_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_m_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_mu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_mu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_mu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_mu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_mu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_mu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_tu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_tu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_tu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_tu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_tu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_tu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_tum_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_tum_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_tum_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_tum_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_tum_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_tum_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_tumu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_tumu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_tumu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_tumu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_tumu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_tumu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_m_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_m_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_m_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_m_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_m_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_m_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_mu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_mu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_mu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_mu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_mu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_mu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_tu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_tu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_tu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_tu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_tu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_tu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_tum_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_tum_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_tum_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_tum_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_tum_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_tum_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_tumu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_tumu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_tumu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_tumu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_tumu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_tumu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vx_m_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vx_m_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vx_m_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vx_m_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vx_m_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vx_m_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vx_mu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vx_mu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vx_mu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vx_mu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vx_mu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vx_mu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vx_tu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vx_tu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vx_tu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vx_tu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vx_tu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vx_tu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vx_tum_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vx_tum_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vx_tum_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vx_tum_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vx_tum_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vx_tum_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vx_tumu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vx_tumu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vx_tumu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vx_tumu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vx_tumu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasub_vx_tumu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vx_m_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vx_m_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vx_m_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vx_m_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vx_m_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vx_m_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vx_mu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vx_mu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vx_mu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vx_mu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vx_mu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vx_mu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vx_tu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vx_tu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vx_tu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vx_tu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vx_tu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vx_tu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vx_tum_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vx_tum_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vx_tum_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vx_tum_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vx_tum_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vx_tum_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vx_tumu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vx_tumu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vx_tumu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vx_tumu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vx_tumu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vasubu_vx_tumu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vx_m_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vx_m_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vx_m_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vx_m_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vx_m_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vx_m_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vx_mu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vx_mu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vx_mu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vx_mu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vx_mu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vx_mu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vx_tu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vx_tu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vx_tu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vx_tu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vx_tu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vx_tu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vx_tum_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vx_tum_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vx_tum_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vx_tum_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vx_tum_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vx_tum_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vx_tumu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vx_tumu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vx_tumu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vx_tumu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vx_tumu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdiv_vx_tumu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vx_m_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vx_m_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vx_m_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vx_m_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vx_m_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vx_m_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vx_mu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vx_mu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vx_mu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vx_mu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vx_mu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vx_mu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vx_tu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vx_tu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vx_tu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vx_tu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vx_tu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vx_tu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vx_tum_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vx_tum_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vx_tum_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vx_tum_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vx_tum_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vx_tum_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vx_tumu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vx_tumu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vx_tumu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vx_tumu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vx_tumu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vdivu_vx_tumu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vx_m_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vx_m_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vx_m_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vx_m_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vx_m_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vx_m_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vx_mu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vx_mu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vx_mu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vx_mu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vx_mu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vx_mu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vx_tu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vx_tu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vx_tu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vx_tu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vx_tu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vx_tu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vx_tum_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vx_tum_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vx_tum_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vx_tum_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vx_tum_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vx_tum_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vx_tumu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vx_tumu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vx_tumu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vx_tumu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vx_tumu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmacc_vx_tumu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc-8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vvm-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vvm-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vvm-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vxm_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vxm_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vxm_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vxm_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vxm_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadc_vxm_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vx_m_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vx_m_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vx_m_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vx_m_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vx_m_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vx_m_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vx_mu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vx_mu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vx_mu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vx_mu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vx_mu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vx_mu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vx_tu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vx_tu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vx_tu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vx_tu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vx_tu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vx_tu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vx_tum_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vx_tum_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vx_tum_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vx_tum_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vx_tum_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vx_tum_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vx_tumu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vx_tumu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vx_tumu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vx_tumu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vx_tumu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmadd_vx_tumu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_m_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_m_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_m_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_m_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_m_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_m_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_mu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_mu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_mu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_mu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_mu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_mu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tum_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tum_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tum_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tum_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tum_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tum_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tumu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tumu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tumu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tumu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tumu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tumu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vx_m_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vx_m_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vx_m_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vx_m_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vx_m_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vx_m_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vx_mu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vx_mu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vx_mu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vx_mu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vx_mu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vx_mu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vx_tu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vx_tu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vx_tu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vx_tu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vx_tu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vx_tu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vx_tum_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vx_tum_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vx_tum_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vx_tum_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vx_tum_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vx_tum_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vx_tumu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vx_tumu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vx_tumu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vx_tumu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vx_tumu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmaxu_vx_tumu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm_tu-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm_tu-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vvm_tu-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_tu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_tu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_tu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_tu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_tu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmerge_vxm_tu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_m_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_m_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_m_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_m_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_m_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_m_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_mu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_mu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_mu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_mu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_mu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_mu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_tu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_tu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_tu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_tu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_tu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_tu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_tum_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_tum_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_tum_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_tum_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_tum_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_tum_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_tumu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_tumu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_tumu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_tumu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_tumu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_tumu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vx_m_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vx_m_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vx_m_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vx_m_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vx_m_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vx_m_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vx_mu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vx_mu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vx_mu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vx_mu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vx_mu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vx_mu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vx_tu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vx_tu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vx_tu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vx_tu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vx_tu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vx_tu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vx_tum_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vx_tum_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vx_tum_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vx_tum_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vx_tum_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vx_tum_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vx_tumu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vx_tumu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vx_tumu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vx_tumu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vx_tumu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vx_tumu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc-8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vvm-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vvm-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vvm-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vxm_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vxm_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vxm_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vxm_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vxm_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsbc_vxm_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmseq_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmseq_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmseq_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmseq_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmseq_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmseq_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmseq_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmseq_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmseq_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmseq_vx_m_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmseq_vx_m_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmseq_vx_m_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmseq_vx_m_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmseq_vx_m_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmseq_vx_m_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmseq_vx_mu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmseq_vx_mu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmseq_vx_mu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmseq_vx_mu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmseq_vx_mu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmseq_vx_mu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmseq_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmseq_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmseq_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmseq_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmseq_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmseq_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_m_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_m_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_m_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_m_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_m_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_m_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_mu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_mu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_mu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_mu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_mu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_mu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsge_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_mu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_mu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_mu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_mu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_mu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_mu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgeu_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_m_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_m_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_m_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_m_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_m_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_m_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgt_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_mu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_mu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_mu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_mu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_mu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_mu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsgtu_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vx_m_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vx_m_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vx_m_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vx_m_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vx_m_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vx_m_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vx_mu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vx_mu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vx_mu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vx_mu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vx_mu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vx_mu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vx_m_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vx_m_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vx_m_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vx_m_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vx_m_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vx_m_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vx_mu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vx_mu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vx_mu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vx_mu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vx_mu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vx_mu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmslt_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmslt_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmslt_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmslt_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmslt_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmslt_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmslt_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmslt_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmslt_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmslt_vx_m_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmslt_vx_m_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmslt_vx_m_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmslt_vx_m_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmslt_vx_m_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmslt_vx_m_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmslt_vx_mu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmslt_vx_mu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmslt_vx_mu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmslt_vx_mu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmslt_vx_mu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmslt_vx_mu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmslt_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmslt_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmslt_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmslt_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmslt_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmslt_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsltu_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsltu_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsltu_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsltu_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsltu_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsltu_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsltu_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsltu_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsltu_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsltu_vx_m_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsltu_vx_m_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsltu_vx_m_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsltu_vx_m_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsltu_vx_m_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsltu_vx_m_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsltu_vx_mu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsltu_vx_mu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsltu_vx_mu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsltu_vx_mu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsltu_vx_mu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsltu_vx_mu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsltu_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsltu_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsltu_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsltu_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsltu_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsltu_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vx_m_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vx_m_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vx_m_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vx_m_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vx_m_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vx_m_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vx_mu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vx_mu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vx_mu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vx_mu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vx_mu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vx_mu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsne_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vx_m_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vx_m_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vx_m_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vx_m_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vx_m_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vx_m_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vx_mu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vx_mu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vx_mu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vx_mu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vx_mu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vx_mu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vx_tu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vx_tu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vx_tu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vx_tu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vx_tu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vx_tu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vx_tum_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vx_tum_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vx_tum_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vx_tum_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vx_tum_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vx_tum_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vx_tumu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vx_tumu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vx_tumu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vx_tumu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vx_tumu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmul_vx_tumu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vx_m_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vx_m_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vx_m_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vx_m_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vx_m_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vx_m_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vx_mu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vx_mu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vx_mu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vx_mu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vx_mu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vx_mu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vx_tu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vx_tu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vx_tu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vx_tu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vx_tu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vx_tu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vx_tum_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vx_tum_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vx_tum_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vx_tum_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vx_tum_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vx_tum_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vx_tumu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vx_tumu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vx_tumu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vx_tumu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vx_tumu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulh_vx_tumu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_m_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_m_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_m_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_m_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_m_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_m_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vx_m_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vx_m_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vx_m_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vx_m_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vx_m_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vx_m_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vx_mu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vx_mu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vx_mu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vx_mu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vx_mu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vx_mu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vx_tu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vx_tu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vx_tu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vx_tu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vx_tu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vx_tu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vx_tum_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vx_tum_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vx_tum_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vx_tum_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vx_tum_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vx_tum_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vx_tumu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vx_tumu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vx_tumu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vx_tumu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vx_tumu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmulhu_vx_tumu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_v_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_tu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_tu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_tu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_tu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_tu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmv_v_x_tu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclip_wx_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnclipu_wx_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vncvt_x_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_m_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_m_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_m_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_m_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_m_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_m_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_mu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_mu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_mu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_mu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_mu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_mu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tum_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tum_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tum_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tum_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tum_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tum_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tumu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tumu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tumu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tumu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tumu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tumu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vx_m_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vx_m_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vx_m_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vx_m_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vx_m_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vx_m_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vx_mu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vx_mu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vx_mu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vx_mu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vx_mu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vx_mu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vx_tu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vx_tu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vx_tu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vx_tu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vx_tu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vx_tu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vx_tum_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vx_tum_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vx_tum_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vx_tum_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vx_tum_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vx_tum_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vx_tumu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vx_tumu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vx_tumu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vx_tumu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vx_tumu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsub_vx_tumu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsra_wx_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnsrl_wx_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vx_m_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vx_m_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vx_m_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vx_m_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vx_m_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vx_m_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vx_mu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vx_mu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vx_mu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vx_mu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vx_mu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vx_mu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vx_tu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vx_tu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vx_tu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vx_tu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vx_tu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vx_tu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vx_tum_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vx_tum_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vx_tum_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vx_tum_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vx_tum_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vx_tum_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vx_tumu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vx_tumu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vx_tumu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vx_tumu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vx_tumu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vor_vx_tumu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_m_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_m_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_m_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_m_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_m_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_m_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_mu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_mu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_mu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_mu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_mu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_mu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tum_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tum_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tum_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tum_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tum_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tum_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tumu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tumu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tumu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tumu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tumu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrem_vx_tumu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_m_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_m_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_m_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_m_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_m_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_m_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_mu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_mu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_mu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_mu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_mu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_mu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tum_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tum_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tum_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tum_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tum_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tum_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tumu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tumu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tumu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tumu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tumu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tumu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrsub_vx_m_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrsub_vx_m_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrsub_vx_m_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrsub_vx_m_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrsub_vx_m_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrsub_vx_m_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrsub_vx_mu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrsub_vx_mu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrsub_vx_mu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrsub_vx_mu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrsub_vx_mu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrsub_vx_mu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrsub_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrsub_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrsub_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrsub_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrsub_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrsub_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrsub_vx_tu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrsub_vx_tu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrsub_vx_tu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrsub_vx_tu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrsub_vx_tu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrsub_vx_tu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrsub_vx_tum_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrsub_vx_tum_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrsub_vx_tum_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrsub_vx_tum_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrsub_vx_tum_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrsub_vx_tum_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrsub_vx_tumu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrsub_vx_tumu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrsub_vx_tumu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrsub_vx_tumu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrsub_vx_tumu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vrsub_vx_tumu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_m_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_m_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_m_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_m_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_m_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_m_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_mu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_mu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_mu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_mu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_mu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_mu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_tu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_tu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_tu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_tu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_tu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_tu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_tum_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_tum_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_tum_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_tum_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_tum_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_tum_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_tumu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_tumu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_tumu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_tumu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_tumu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsadd_vx_tumu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_m_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_m_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_m_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_m_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_m_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_m_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_mu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_mu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_mu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_mu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_mu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_mu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_tu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_tu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_tu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_tu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_tu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_tu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_tum_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_tum_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_tum_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_tum_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_tum_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_tum_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_tumu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_tumu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_tumu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_tumu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_tumu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsaddu_vx_tumu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vvm-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vvm-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vvm-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vvm_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vvm_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vvm_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf2_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf4_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsext_vf8_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vx-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vx-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vx-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vx_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vx_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vx_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vx_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vx_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vx_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vx_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vx_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vx_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vx_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vx_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vx_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vx_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vx_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsll_vx_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vx_m_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vx_m_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vx_m_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vx_m_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vx_m_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vx_m_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vx_mu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vx_mu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vx_mu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vx_mu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vx_mu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vx_mu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vx_tu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vx_tu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vx_tu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vx_tu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vx_tu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vx_tu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vx_tum_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vx_tum_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vx_tum_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vx_tum_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vx_tum_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vx_tum_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vx_tumu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vx_tumu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vx_tumu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vx_tumu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vx_tumu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsmul_vx_tumu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssrl_vx_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vx_m_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vx_m_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vx_m_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vx_m_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vx_m_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vx_m_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vx_mu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vx_mu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vx_mu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vx_mu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vx_mu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vx_mu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vx_tu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vx_tu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vx_tu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vx_tu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vx_tu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vx_tu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vx_tum_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vx_tum_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vx_tum_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vx_tum_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vx_tum_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vx_tum_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vx_tumu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vx_tumu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vx_tumu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vx_tumu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vx_tumu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssub_vx_tumu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vx_m_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vx_m_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vx_m_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vx_m_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vx_m_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vx_m_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vx_mu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vx_mu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vx_mu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vx_mu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vx_mu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vx_mu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vx_tu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vx_tu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vx_tu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vx_tu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vx_tu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vx_tu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vx_tum_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vx_tum_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vx_tum_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vx_tum_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vx_tum_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vx_tum_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vx_tumu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vx_tumu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vx_tumu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vx_tumu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vx_tumu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu_vx_tumu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_m_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_m_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_m_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_m_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_m_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_m_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_mu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_mu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_mu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_mu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_mu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_mu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tum_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tum_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tum_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tum_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tum_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tum_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tumu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tumu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tumu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tumu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tumu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tumu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_vx-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_vx-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_vx-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_vx_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_vx_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_vx_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_vx_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_vx_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_vx_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_vx_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_vx_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_vx_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_vx_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_vx_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_vx_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_vx_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_vx_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_vx_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_wv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_wv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_wv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_wv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_wv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_wv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_wv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_wv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_wv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_wv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_wv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_wv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_wv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_wv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_wv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_wv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_wv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_wv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_wx-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_wx-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_wx-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_wx_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_wx_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_wx_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_wx_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_wx_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_wx_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_wx_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_wx_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_wx_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_wx_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_wx_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_wx_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_wx_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_wx_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwadd_wx_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvt_x_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwcvtu_x_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmacc_vx_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccsu_vx_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccu_vx_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmul_vx_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulsu_vx_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmulu_vx_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vx-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vx-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vx-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vx_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vx_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vx_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vx_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vx_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vx_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vx_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vx_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vx_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vx_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vx_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vx_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vx_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vx_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_vx_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wx-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wx-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wx-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wx_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wx_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wx_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wx_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wx_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wx_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wx_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wx_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wx_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wx_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wx_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wx_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wx_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wx_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsub_wx_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vx-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vx-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vx-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vx_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vx_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vx_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vx_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vx_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vx_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vx_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vx_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vx_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vx_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vx_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vx_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vx_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vx_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_vx_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwsubu_wx_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_m_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_m_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_m_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_m_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_m_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_m_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_mu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_mu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_mu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_mu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_mu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_mu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tum_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tum_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tum_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tum_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tum_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tum_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tumu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tumu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tumu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tumu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tumu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tumu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf2_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf4_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vzext_vf8_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/s390/preserve-args-1.c create mode 100644 gcc/testsuite/gcc.target/s390/preserve-args-2.c create mode 100644 gcc/testsuite/gcc.target/s390/preserve-args-3.c create mode 100644 gcc/testsuite/gfortran.dg/gomp/loop-5.f90 create mode 100644 gcc/testsuite/gfortran.dg/gomp/openmp-simd-8.f90 create mode 100644 gcc/testsuite/gfortran.dg/noinline.f90 create mode 100644 gcc/testsuite/gfortran.dg/noreturn-1.f90 create mode 100644 gcc/testsuite/gfortran.dg/noreturn-2.f90 create mode 100644 gcc/testsuite/gfortran.dg/noreturn-3.f90 create mode 100644 gcc/testsuite/gfortran.dg/noreturn-4.f90 create mode 100644 gcc/testsuite/gfortran.dg/noreturn-5.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr103259.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr103475.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr103608.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr103779.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr104554.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr108592.f90 create mode 100644 gcc/testsuite/gfortran.dg/save_7.f90 create mode 100644 gcc/testsuite/gfortran.dg/weak-1.f90 create mode 100644 gcc/testsuite/gnat.dg/shift2.adb create mode 100644 gcc/testsuite/rust/compile/issue-1361.rs create mode 100644 gcc/testsuite/rust/compile/issue-1422.rs copy libgcc/config/{aarch64 => riscv}/value-unwind.h (62%) create mode 100644 libgomp/testsuite/libgomp.fortran/allocate-4.f90 create mode 100644 libgomp/testsuite/libgomp.fortran/non-rectangular-loop-1.f90 create mode 100644 libgomp/testsuite/libgomp.fortran/non-rectangular-loop-1a.f90 create mode 100644 libgomp/testsuite/libgomp.fortran/non-rectangular-loop-2.f90 create mode 100644 libgomp/testsuite/libgomp.fortran/non-rectangular-loop-3.f90 create mode 100644 libgomp/testsuite/libgomp.fortran/non-rectangular-loop-4.f90 create mode 100644 libgomp/testsuite/libgomp.fortran/non-rectangular-loop-5.f90 create mode 100644 libgomp/testsuite/libgomp.fortran/reverse-offload-6.f90 create mode 100644 libgomp/testsuite/libgomp.fortran/target-enter-data-3.f90 create mode 100644 libstdc++-v3/include/experimental/synchronized_value create mode 100644 libstdc++-v3/testsuite/17_intro/names_pstl.cc copy libstdc++-v3/testsuite/20_util/{is_literal_type/deprecated-1z.cc => aligned_s [...] copy libstdc++-v3/testsuite/20_util/{is_literal_type/deprecated-1z.cc => aligned_u [...] create mode 100644 libstdc++-v3/testsuite/20_util/pair/dangling_ref.cc create mode 100644 libstdc++-v3/testsuite/20_util/variant/lwg3585.cc create mode 100644 libstdc++-v3/testsuite/25_algorithms/contains/1.cc create mode 100644 libstdc++-v3/testsuite/25_algorithms/contains_subrange/1.cc create mode 100644 libstdc++-v3/testsuite/25_algorithms/find_last/1.cc create mode 100644 libstdc++-v3/testsuite/25_algorithms/find_last_if/1.cc create mode 100644 libstdc++-v3/testsuite/25_algorithms/find_last_if_not/1.cc create mode 100644 libstdc++-v3/testsuite/25_algorithms/iota/1.cc create mode 100644 libstdc++-v3/testsuite/27_io/filesystem/path/108636.cc create mode 100644 libstdc++-v3/testsuite/experimental/simd/tests/bits/main.h create mode 100644 libstdc++-v3/testsuite/experimental/synchronized_value.cc create mode 100644 libstdc++-v3/testsuite/std/format/arguments/lwg3810.cc