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from bb3ceeb6520 libstdc++: Fix incorrect use of abs and log10 in std::forma [...] new 9cba4fce837 RISC-V: Support VLS basic operation auto-vectorization
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Summary of changes: gcc/config/riscv/autovec-vls.md | 23 +++ gcc/config/riscv/vector-iterators.md | 93 ++++++++++++ gcc/config/riscv/vector.md | 166 ++++++++++----------- .../gcc.target/riscv/rvv/autovec/vls/and-1.c | 57 +++++++ .../gcc.target/riscv/rvv/autovec/vls/and-2.c | 57 +++++++ .../gcc.target/riscv/rvv/autovec/vls/and-3.c | 57 +++++++ .../gcc.target/riscv/rvv/autovec/vls/def.h | 48 ++++++ .../gcc.target/riscv/rvv/autovec/vls/div-1.c | 58 +++++++ .../gcc.target/riscv/rvv/autovec/vls/ior-1.c | 57 +++++++ .../gcc.target/riscv/rvv/autovec/vls/ior-2.c | 57 +++++++ .../gcc.target/riscv/rvv/autovec/vls/ior-3.c | 57 +++++++ .../gcc.target/riscv/rvv/autovec/vls/max-1.c | 57 +++++++ .../gcc.target/riscv/rvv/autovec/vls/min-1.c | 57 +++++++ .../gcc.target/riscv/rvv/autovec/vls/minus-1.c | 57 +++++++ .../gcc.target/riscv/rvv/autovec/vls/minus-2.c | 57 +++++++ .../gcc.target/riscv/rvv/autovec/vls/minus-3.c | 57 +++++++ .../gcc.target/riscv/rvv/autovec/vls/mod-1.c | 57 +++++++ .../gcc.target/riscv/rvv/autovec/vls/mult-1.c | 57 +++++++ .../gcc.target/riscv/rvv/autovec/vls/plus-1.c | 57 +++++++ .../gcc.target/riscv/rvv/autovec/vls/plus-2.c | 57 +++++++ .../gcc.target/riscv/rvv/autovec/vls/plus-3.c | 57 +++++++ 21 files changed, 1217 insertions(+), 83 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/and-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/and-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/and-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/div-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ior-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ior-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ior-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/max-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/min-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/minus-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/minus-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/minus-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mod-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mult-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/plus-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/plus-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/plus-3.c