[Tcwg-commits] [toolchain/ci/gcc] branch linaro-local/ci/tcwg_bmk_tk1/llvm-master-arm-spec2k6-O2 updated (e99b18cf710 -> 497498c878d)

This is an automated email from the git hooks/post-receive script.

tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tk1/llvm-master-arm-spec2k6-O2 in repository toolchain/ci/gcc.

from e99b18cf710 Daily bump. adds d6f420d9812 Honor --disable-dependency-tracking in libatomic adds 6cd5024c864 c++: Use %qs in diagnostic message [PR93882] adds 128ff73d7c5 libatomic: Fix last change [PR55930] adds cd6016713aa Daily bump. adds 61c8d9e4e5f Patch for PR57710 adds 7260547dbff Fix error message. adds 92e8508edac Add missing closing parenthises in error message. adds 3133bed5d03 Changing cost propagation and ordering colorable bucket heu [...] adds c7bfe1aaa39 Daily bump. adds 9069e9484ce RISC-V: Adjust floating point code gen for LTGT compare adds f1a681a174c PR47785: Add support for handling Xassembler/Wa options with LTO. adds 2bd8c3ff351 OpenACC tile clause – apply exit/cycle checks (PR 93552) adds 7f5617b0044 sccvn: Handle bitfields in push_partial_def [PR93582] adds 3841739c29a libstdc++: enable_view has false positives (LWG 3326) adds e03069be127 PR78353: Fix testcases adds 120e873484f libstdc++: Add default_sentinel support to stream iterators adds 32b8f5df9f0 c++: Fix C++20 variadic lambda init-capture grammar. adds 8566286eaeb libstdc++: Fix noexcept-specifier for istream_iterator adds fb6a8b230ad c++: P1937R2 - Fixing inconsistencies between const{expr,ev [...] adds c77b6f95e01 fortran: ICE in gfc_conv_constant_to_tree PR93604 adds 027a3f1c387 internal/syscall/unix: add hurd build tag adds c5eab4ed45e libstdc++: P0769R2 Add shift to <algorithm> adds 85c143d002a libstdc++: Add missing bits of P0896R4 pertaining to [back| [...] adds b07c085581e c++: Fix ICE with ill-formed array list-initialization [PR93712] adds 27bf39a8035 ortran: ICE using SHAPE with FINDLOC PR93835 adds cae5ff6036a c++: Fix ICE with -Wmismatched-tags [PR93869] adds 004f2c07b6d analyzer: eliminate irrelevant control-flow edges from paths adds b73547e40e0 PR c++/93804 - exempt extern C headers from -Wredundant-tags adds fb77bf1c86e Remove a hunk duplicated during a merge. adds a4dbb9b25a6 internal/poll: add hurd build tag adds 3a25f345d1f analyzer: fix ICE with OFFSET_TYPE [PR 93899] adds b3d788a2cd3 analyzer: disable the "taint" checker by default adds 0b002688979 Daily bump. adds 04c71707e03 Update gcc de.po. adds f2ca2088bc3 analyzer: fix -fdump-analyzer adds 267cca3d201 doc: properly describe --enable-checking behavior adds 71837f64ab0 Fix typo: paramter -> parameter [PR93864] adds 7b60f3ba766 c: Small diagnostics tweak - add missing ? after did you me [...] adds 103bc4db766 testsuite: Fix recently added ipa testcases [PR93763] adds fe86f537f01 Dead code in fortran/simplify.c adds 2473c81cb2d pass_manager: Fix ICE with -fdump-passes -fdisable-tree-* [ [...] adds 81c833b311b tree-optimization/93868 copy SLP tree before re-arranging stmts adds 8bc6d0a2da6 doc: minor --enable-checking wording fixes adds 81ef67c10a3 testcase for last_vuse in FRE adds 2877ad9ac28 Fix link failure with debug info in LTO mode adds 5b904f175ff libstdc++: Fix regression in std::move algorithm (PR 93872) adds 6de946e65c9 libstdc++: Add test accidentally left out of previous commit adds 73dc4ae4741 combine: Fix find_split_point handling of constant store in [...] adds a71f2193d0d [ARM] Fix -mpure-code for v6m adds dfb93d05246 Fix ChangeLog date adds 490350a11f8 libstdc++: Remove __memmove wrapper for constexpr algorithms adds eb7ba6c36b8 arm: ACLE intrinsics for bfloat16 dot product adds 7f0f108309a libstdc++: LWG 3292 iota_view is under-constrained adds 510bd1c178f libstdc++: LWG 3301 transform_view::iterator has incorrect [...] adds 55c4b3f4862 libstdc++: LWG 3313 join_view::iterator::operator-- is inco [...] adds ec15da7c330 libstdc++: LWG 3325 Constrain return type of transformation [...] adds 76a8c0f65e2 libstdc++: LWG 3397 basic_istream_view::iterator should not [...] adds 8ea6c1b89a2 aarch64: Add bfloat16 vdup and vreinterpret ACLE intrinsics adds e603cd43b14 aarch64: Add bfloat16 vldn/vstn intrinsics adds 68f8763d57a Correct an attribute access example. adds 9c3da8cc5d0 typo fix: Fix probablity, becuse, sucessor and destinarion [...] adds 07a0e380d62 Daily bump. adds 5de338f001e c++: Fix rejects-valid bug in cxx_eval_outermost_constant_e [...] adds 4d213bf6011 store-merging: Fix coalesce_immediate_stores [PR93820] adds ce25177f505 testsuite: Add a -O2 -fgimple testcase next to the -O2 -fno [...] adds 67fa274cd63 analyzer: improvements to logging/dumping adds b6268016bf4 optabs: Don't use scalar conversions for vectors [PR93843] adds 759bd406a2b dump load permutations and refcount per SLP node adds d6ff2207412 c++: Fix ICE with constexpr init and [[no_unique_address]] [...] adds b9934ad88d6 c++: Add test for DR 1423, Convertibility of nullptr to bool. adds 4a305fa2fd4 c++: Fix ICE with static_cast when converting from int[] [PR93862] adds 8017d95c7f5 libstdc++: Add __maybe_const_t and __maybe_empty_t aliases adds 113f0a639db libstdc++ Two simplifications for lexicographical_compare adds fd335985582 libstdc++: P1645R1 constexpr for <numeric> algorithms adds 8ce13842b50 libstdc++: Fix use of inaccessible private member in split_ [...] adds 38e10026578 c++: Fix value-init crash in template [PR93676] adds 44f6b7fb574 c++: Some improvements to concept diagnostics adds 051b9873e78 rs6000: Fix more testsuite fallout from rs6000_legitimate_a [...] adds c5decc83e4e libgo: update to final Go1.14 release adds dc192bbdd04 coroutines: Amend parameter handling to match n4849. adds 15fc2e04a59 PPC64, fix documentation for __builtin_crypto_vpmsum* built [...] adds 89f759ac2eb Daily bump. adds 0ba70d1b5ae analyzer: fix ICE on unreachable calls [PR 93947] adds 71b633aaea3 analyzer: fix ICE with -Wanalyzer-null-dereference [PR 93950] adds 1231f71f96a c++: Fix ICE with invalid array bounds [PR93789] adds cf70bb0fbd7 Document negative form of warning options enabled by defaul [...] adds 494e434c05f maintainer-scripts: Speed up git clone in gcc_release adds 4fd9efc8877 doc: Update description of BullFreeware adds 5f9cd512c42 sccvn: Handle non-byte aligned offset or size for memset (, [...] adds 1956773cc65 gimplify: Don't optimize register const vars to static [PR93949] adds d1215304681 fix -fdebug-prefix-map without gas .file support adds eb8e6a30a44 libstdc++: Make _GLIBCXX_CONCEPT_CHECKS more constexpr-friendly adds 82863a5cc99 amdgcn: fix ICE on subreg of BI reg. adds e840185b31e tree-optimization/93953 - avoid reference into hash-map adds e431546ff9f tree-optimization/93508 - make VN translate through _chk an [...] adds e94f2542305 libstdc++: Support N3644 "Null Forward Iterators" for tests [...] adds da5f369df6d Fix broken type comparison assert adds f32a3662cda libstdc++: Fix std::string error in Debug Mode adds b112e3cb602 libstdc++: Fix std::span test failures with _GLIBCXX_ASSERTIONS adds ae7051590d4 libstdc++: Define <=> for Debug Mode array adds 46788c65f93 work-around system header namespace pollution adds aca124df668 define NO_DOT_IN_LABEL only in vxworks6 adds d9dfec65c5b Use -mno-pcrel for tests requiring TOC. adds aa307bd027d PowerPC Add has_arch_pwr* checks adds dc941ea9258 amdgcn: sub-dword vector min/max/shift/bit operators adds 17a13507d77 [GCC][PATCH][ARM] Add vreinterpret, vdup, vget and vset bf [...] adds 9640ff5a88f middle-end: Fix wrong code caused by disagreemed between FR [...] adds cfeef9acd2c ipa-cp: Avoid an ICE processing self-recursive cloned edges [...] adds 10a32d47986 libstdc++: -D_GLIBCXX_DEBUG fixes in the constrained algos tests adds ba49e9eb187 libstdc++: Add missing friend declarations in some range adaptors adds 9d2d283367a Compare ARGUMENT_PACKS [pr93933] adds 75c299acc47 Fix PR target/93932 adds 449494943e6 libstdc++: Disable diagnostic URLs in testsuite adds 58645f7153d Update gcc fr.po. adds ab466f73bb3 Document that -Wbuiltin-declaration-mismatch is enabled by [...] adds 8f22ba6d69f Daily bump. adds 5c3489a083b testsuite: Fix up g++.dg/torture/pr92152.C test for ilp32 targets adds 4707548ee84 Add myself to MAINTAINERS adds 86e2dc22c91 libstdc++: Fix failing test in debug mode adds a51a546c170 libstdc++: Fix FS-dependent filesystem tests adds a1535015786 libstdc++: Memoize {drop,drop_while,filter,reverse}_view::begin adds 349297b6e69 Fix misleading aarch64 mcpu/march warning string adds f3ce088645e One more patch for PR93564: Prefer smaller hard regno when [...] adds 18396541e47 c++: Further tweak for P1937R2 - const{expr,eval} inconsistencies adds 08bf7bde9f2 Improve detection of ld_date. adds 77e596cf3c1 libstdc++: Also disable caching of reverse_view::begin() fo [...] adds ab2f2e19111 Fix target/93937 adds 7485ace81de Commit for PR92785 adds 4735f92d48c libstdc++: test for failing assertion should use 'run' not [...] adds 586b016cd48 c++: Fix constrained conversion op. adds 799270b4305 libstdc++: Update the <numeric> synopsis test to latest standard adds 3f469f585e0 runtime: handle linux/arm64 signal register adds e82192021dd coroutines: Update func-params-08.C to suspend three times. adds ce33801fe4c libstdc++: Fix bogus use of memcmp in ranges::lexicographic [...] adds 96ad5fb8bc9 Daily bump. adds 117baab8771 c++: implement C++20 Disambiguating Nested-Requirements (P2092R0) adds d48e1175279 Fix regression reported by tester due to recent IRA changes adds d0ad2a22339 Update cpplib ru.po. adds 5b4c2cc6999 Fix trivial regression from recent IRA changes adds d4912dc7666 Fix baseline symbols on hppa-linux-gnu adds 0483af36a21 Add dg-require-visibility to tests that require visibility [...] adds b177b3696c7 Fix typo in last entry. adds 68a1a11fad0 Explicitly link with libatomic when needed. adds 44c85722dc6 libstdc++ Hastable: Move std::is_permutation to limit includes adds bd55ce63657 Explicitly link with libatomic when needed. adds 566f544c3e7 Skip charset.cc tests on *-*-hpux*. adds 38b1722d5d4 XFAIL IPA tests that are not supported on 32-bit hppa*-*-hpux*. adds 9f6dd268194 Fix/skip various tests for hppa*-*-hpux*. adds 819852b98eb Disable gnat.dg/socket1.adb on hppa*-*-hpux*. adds c7dbc549583 Make STATIC_CHAIN_REGNUM a call used register. adds 1cb65b1207c coroutines: Add a test for non-trivial await_resume return type. adds 6fa4bc48bd6 Daily bump. adds fed76afb95a x32: Update baseline_symbols.txt adds 69a9b14b964 [Darwin, libsanitizer] Default to no sanitizer for Darwin <= 10 adds 63cc547f6d8 Darwin, libsanitizer: Adjust minimum supported Darwin versi [...] adds 7067f8c8140 Patch for PR92959 adds 12caab4fb19 ChangeLogs for PR92959 adds 957a1b14e99 Patch and ChangeLogs for PR92976 adds 26e78220c71 coroutines: Test that we correctly use class data members. adds 03a71208880 Fix test for pr88233. adds 151bf47e78f Fix test for pr68805. adds 750d061df09 Daily bump. adds 1e9369c5dcf PR middle-end/93829 - bogus -Wstringop-overflow on memcpy o [...] adds a499c2f8999 PR c/93812 - ICE on redeclaration of an attribute format fu [...] adds 726e292d410 PR middle-end/93926 - ICE on a built-in redeclaration retur [...] adds 649e174102a PR middle-end/92721 - checking ICE on attribute access rede [...] adds 778a77357ca [testsuites] Update several scev/IVOPTs cases adds 917e56a94f9 Fix typo in C++ standard version. adds 577350603a6 lto: Also copy .note.gnu.property section adds 3bb6abbf4bb Fix a libiberty testsuite failure adds 8dd5d8f31a4 Remove duplicate declaration. adds c9d92a575c9 Update comment to reflect optimization. adds 5fad000324d libstdc++: Add 'typename' to fix compilation with Clang adds ac3148a3d7d Fix changelog typo adds 0ce38183001 Fix testsuite regression due to recent IRA changes. adds a5879399fc0 amdgcn: Extend reductions to all types adds 005530eb019 coroutines: Don't make duplicate frame copies of awaitables. adds 4c391563407 libstdc++: Rename __detail::__maybe_empty_t alias template adds d112e173ea0 libstdc++: Fix std::lexicographic_compare for unsigned char [...] adds f3c276aec26 Ensure sufficient size of variables used for module+submodu [...] adds e78e50d57ed c++: Add -std=gnu++20 option [PR93958] adds f26688fbe44 Add new test for PR tree-optimization/92982. adds b80cbe2d8d4 i386: Allow only registers with VALID_INT_MODE_P modes in m [...] adds cd14f288ddf coroutines: Update lambda capture handling to n4849. adds 9f00b22f98e analyzer: detect malloc, free, calloc within "std" [PR93959] adds 6e4444078ae invoke.texi: add missing option to -fanalyzer list adds 13b7691238f analyzer: don't print the duplicate count by default adds 3f33c471bbf Daily bump. adds fd9e021c70e Build coroutine expression with unknown_type in processing_ [...] adds a422f68924d testsuite: Add testcases for already fixed PR [PR93927] adds 93338040bd7 arc: Add length attribute to eh_return pattern. adds adaa539557b arc: Improve code gen for 64bit add/sub operations. adds 9c3044a210d arc: Use accl_operand predicate for fma instructions. adds 02ae0e08a93 arc: Update legitimate small data address. adds 0ab503d34f2 explow: Fix ICE caused by plus_constant [PR94002] adds 01eb1bb0237 s390: Fix --with-arch=... --with-tune=... [PR26877] adds 3d6fd7ce6dc tree-optimization/93946 - fix bogus redundant store removal [...] adds b07e4e7c752 sccvn: Improve handling of load masked with integer constan [...] adds 9b4f00dd3f7 libstdc++: Micro-optimisations for lexicographical_compare_ [...] adds 8e6d0dba166 arm: ACLE BFloat16 convert intrinsics adds 6b9ce2b4eb4 libgcc: arm: convert thumb1 code to unified syntax adds 0e0ffbfc23b c++: Fix non-constant TARGET_EXPR constexpr handing [PR93998] adds 462f6c2041f libstdc++: Workaround is_trivially_copyable<volatile T> (PR 94013) adds c46da87b9d3 Daily bump. adds 7f327e8765c coroutines: Handle component_ref in captures_temporary adds 05779e2c89e libstdc++: Fix use of is_nothrow_assignable_v in <bits/rang [...] adds d6d4b339f5b libstdc++: Add a move-only testsuite iterator type adds 26af9cd8af1 libstdc++: Add a testsuite range type that has a sized sentinel adds 144dfc68d0c libstdc++: Move-only input iterator support in <memory> alg [...] adds 712b182a8bc libstdc++: Fix incorrect use of memset in ranges::fill_n (P [...] adds 6b3302da9ef c++: Fix mismatch in template argument deduction [PR90505] adds 8cc59ac5912 PR target/93995 ICE in patch_jump_insn, at cfgrtl.c:1290 on [...] adds 8e480ec1ddb tailcall: Fix up process_assignment [PR94001] adds 2e032851802 Wrap array in ctor with braces. adds c7ec2f9ff6d Clear --help=language and --help=common interaction. adds dca54007ebb tree-optimization/93964 - adjust ISL code generation for po [...] adds 1cdfb80a4ec sccvn: Avoid overflows in push_partial_def adds 64ba6d17022 inliner: Copy DECL_BY_REFERENCE in copy_decl_to_var [PR93888] adds 20fb4a47421 Add -fcommon to a test-case to re-trigger it. adds 181e2a2fa5e IBM Z: zTPF: Add tpf trace customization options adds 0993851dc13 IBM Z: zTPF: Build libgcc with -mtpf-trace-skip adds 14cb388b743 IBM Z: zTPF: Prevent FPR usage adds 48c16b28679 IBM Z: zTPF: Include glibc-stdint.h to get __UINTPTR_TYPE__ [...] adds 0b0908c1f27 rs6000: Fix -mpower9-vector -mno-altivec ICE (PR87560) adds 94f7d7ec6eb libstdc++: Fix comment on __memcpyable adds 13e3ba14ecc analyzer: remove unused private fields adds 3d66e153b40 analyzer: fix ICE on non-lvalue in prune_for_sm_diagnostic [...] adds e516294a1ac analyzer: handle __builtin_expect [PR93993] adds 322fb704f87 Add dg-require to existing powerpc/pr93122.c test adds 97bd1d6b513 Remove unnecessary XFAILs from existing testcase 20050603-3.c. adds 3ca63e1c76b PR middle-end/81401 - false positive -Wformat-overflow in a loop adds 4ac3eb5c5f1 analyzer: add regression test for fixed ICE [PR94028] adds 3c1645a379e analyzer: validate region subclasses adds 10bbbb591cf PR tree-optimization/93986 - ICE on mixed-precision wide_in [...] adds 6876b269bc7 c++: Fix [[no_unique_address]] and default mem-init [PR90432] adds 20a235a8b44 Fix format warning which showed up on FreeBSD 11.3. adds 547cdf8510a Daily bump. adds cb2409c60ae PR c++/90938 - Initializing array with {1} works but not {0} adds fe19699ae28 sccvn: Fix handling of POINTER_PLUS_EXPR in memset offset [ [...] adds c9f90a25d49 Keep .GCC.command.line sections of LTO objetcs adds febfe87d80c print-rtl: Fix printing of CONST_STRING in DEBUG_INSNs [PR93399] adds 7d6b3a788f7 [PATCH][GCC]: Add myself to MAINTAINERS adds 43031fbdda7 [AArch32] ACLE intrinsics bfloat16 vmmla and vfma<b/t> for [...] adds a2ec7c4aafb Fortran: ICE in gfc_code2string PR93792 adds a258e464580 c++: Add test for PR91607. adds dca58aef2e3 Future proofing this test. adds c0e184b4ad4 testsuite: Add testcase for already fixed PR [PR90311] adds 6a7052832a4 libstdc++: allow string_view insertion to work with <iosfwd [...] adds a5090de45af testsuite: Compile asan_test.C with -Wno-alloc-size-larger-than adds 9412b35affa libstdc++: Fix some warnings in filesystem tests adds 2d22ab64c47 [AArch32] ACLE intrinsics bfloat16 vmmla and vfma<b/t> for [...] adds 3a0e583bf17 i386: Fix some -O0 avx2intrin.h and xopintrin.h intrinsic m [...] adds 55ace4d1463 Fix location maybe_diag_overlap passes to diagnostics so th [...] adds 8c044c65773 Commit correct version of gimple.c file adds c9d70946b3c c: ignore initializers for elements of variable-size types [...] adds 22a75da901b [PATCH][testuite] Fix pr80481.C after epilogue vectorization adds 34ec7d5347e Daily bump. adds 5358e8f5800 i386: Properly encode vector registers in vector move adds 46275300312 re PR tree-optimization/90883 (Generated code is worse if r [...] adds 655e5c29ae4 Fix error format string. adds 1f520d34129 aarch64: ACLE intrinsics for BFCVTN, BFCVTN2 and BFCVT adds 12007097342 RISC-V: Fix testsuite regression due to recent IRA changes. adds ff229375721 ACLE intrinsics: BFloat16 store (vst<n>{q}_bf16) intrinsics [...] adds eb637e76047 ACLE intrinsics: BFloat16 load intrinsics for AArch32 adds 28119fba7f1 libstdc++: Deal with ENOSYS == ENOTSUP adds 180eeeaeb20 libstdc++: Fix failing filesystem::path tests (PR 93244) adds 068fe0a9e99 Add missing ChangeLog entries adds b0815713a32 libstdc++: Fix call to __glibcxx_rwlock_init (PR 93244) adds 4cdcb2c92a1 libstdc++: Fix PR number in ChangeLog (PR 94069) adds 6d082cd9013 libstdc++: Give ranges::empty() a concrete return type (PR 93978) adds 6aa2ca21a44 libstdc++: Add missing friend declaration to join_view::_Sentinel adds 4b62b3960ec arc: Update tumaddsidi4 test. adds e6ce69cae50 Avoid putting a REG_NOTE on anything other than an INSN in [...] adds 3dcf51ad7b0 rs6000: Correct logic to disable NO_SUM_IN_TOC and NO_FP_IN [...] adds 4a5c938bbfd [AArch64][SVE] Add missing movprfx attribute to some ternar [...] adds 3e5c062e96c [AArch64] Fix lane specifier syntax adds 0b839322117 [AArch64] Use intrinsics for widening multiplies (PR91598) adds 191bcd0f30d Fix mangling ICE [PR94027] adds 41f99ba6c57 analyzer: improvements to state dumping adds 90f7c3007d5 analyzer: improvements to region_model::get_representative_tree adds 2a4c59d9aa6 Daily bump. adds 6733ecaf3fe gcc.target/i386/pr89229-3c.c: Include "pr89229-3a.c" adds ff0a62841e2 c++: Fix pretty printing of TYPENAME_TYPEs adds 5e1b4e60c18 c++: Fix missing SFINAE when binding a bit-field to a refer [...] adds 9de42a8e995 Patch and ChangeLogs for PR93581 adds 0b4ee25bdd7 Daily bump. adds d5114529228 [testsuite] Fix PR94023 to guard case under vect_hw_misalign adds cb2c60206f4 [testsuite] Fix PR94019 to check vector char when vect_hw_misalign adds 016d0f9e43c Insert default return_void at the end of coroutine body adds 2e94d3ee47b alias: Punt after walking too many VALUEs during a toplevel [...] adds 314b91220a0 Restore alignment in rs6000 target. adds 157e23d8803 [testsuite][arm] Fix typo in fuse-caller-save.c adds 8475f2902a2 c++: Fix ABI issue with alignas on armv7hl [PR94050] adds 29b1533acd5 configure - build libgomp by default for amdgcn adds 9439378f7a0 rs6000: Fix -mlong-double documentation adds a931bb50fe7 Fix 'A' operand modifier: PR inline-asm/94095 adds 5dc1390b41d Revert: One more patch for PR93564: Prefer smaller hard reg [...] adds 81fa6d7321d c++: Readd [LR]ROTATE_EXPR support to constexpr.c [PR94067] adds ea182fe6363 libstdc++: Handle type-changing path concatenations (PR 94063) adds d417b4f5414 c++: Fix convert_like in template [PR91465, PR93870, PR9203 [...] adds 406d2cecabd Update cpplib da.po. adds 983a6e7a502 Daily bump. adds 8fc37274021 gdbinit.in: Fix typo. adds c1263058ba0 Update gcc sv.po. adds cc5c935937d i386: Fix up *testqi_ext_3 insn&split for the *testdi_1 cha [...] adds 3654d49d0ff libstdc++: Change compile-only test to run adds c222eabcf8b libstdc++: Fix invalid noexcept-specifier (PR 94117) adds aed151bb53b Revert "Fix regression reported by tester due to recent IRA [...] adds cfd90eb9ed0 testsuite: Scan for SSE reg-reg moves only in pr80481.C adds 90b5ebd7693 minor: fix intendation in ddg.c adds b888a051deb loop-iv: make find_simple_exit static adds cf0c3a45731 libstdc++: Fix noexcept guarantees for ranges::split_view adds e00cb200f39 PR90763: PowerPC vec_xl_len should take const argument. adds 14af5d9b19b c++: Partially revert patch for PR66139. adds b269a014771 c++: Add tests for PR93922 and PR94041. adds 0b7f1e24316 libstdc++: Fix uses of _M_current in split_view's outer iterator adds 76743c8a6ab Daily bump. adds 37e0df8a9be rs6000: Check -+0 and NaN for smax/smin generation adds df15a82804e c++: Fix ICE with omitted template args [PR93956]. adds 481fcfe6fec c++: Fix deferred noexcept on constructor [PR93901]. adds e11d05c1ed2 c++: Fix wrong conversion error with non-viable overload [PR94124] adds 5115542a5cc Fix length computation for movsi_insv which resulted in reg [...] adds 8f0d8cd8522 libstdc++: LWG 3286 ranges::size is not required to be vali [...] adds 05ac4d9c7b3 ldist: Further fixes for -ftrapv [PR94114] adds 312992f5a07 dfp: Fix decimal_to_binary [PR94111] adds 60342fdbfb0 value-prof: Fix abs uses in value-prof.c [PR93962] adds 42bc589e87a aarch64: Fix ICE in aarch64_add_offset_1 [PR94121] adds a5aac267e64 Fix internal error on locally-defined subpools adds e835226bab5 Fix GIMPLE verification failure in LTO mode on Ada code adds d564c5e254d [testsuite] Add @ lines to check-function-bodies fluff adds cb99630f254 fold undefined pointer offsetting adds 5fea87cc790 RISC-V: Fix testsuite regression due to recent IRA changes. adds d42ff1d3b62 pdp11: Fix handling of common (local and global) vars [PR94134] adds 1c43ee69f4f Bug fix: cannot convert 'const short int*' to 'const __bf16*' adds 4512b7d8518 libstdc++: Add a test that takes the split_view of a non-fo [...] adds 7eb5be6ab91 c++: Fix wrong modifying const object error for COMPONENT_R [...] adds bde31a76ba4 c++: Fix ICE with concepts and aliases [PR93907]. adds 923e1785276 Daily bump. adds 690de2b706b testsuite: Fix concepts-using2.C failure on 32-bit targets [...] adds 9c1281d9863 Add myself to MAINTAINERS adds f457ae2218c [rs6000] Fix a wrong GC issue adds aedb4c8fc77 Update myself to MAINTAINERS adds 4069adf4bbc c++: Tweak reshape_init_array_1 [PR94124] adds 349ab34dc64 tree-dse: Fix mem* head trimming if call has lhs [PR94130] adds b73f69020f0 doc: Fix up ASM_OUTPUT_ALIGNED_DECL_LOCAL description adds 98aeb1ef510 [Fortran, OpenACC] Reject vars of different scope in $acc d [...] adds 54f46d82f54 i386: Use ix86_output_ssemov for MMX TYPE_SSEMOV adds fcc443b97e1 libstdc++: Fix test failure due to -Wnonnull warnings adds 1dc00a8ec9a tree-optimization/94103 avoid CSE of loads with padding adds a0ae4cbe9d1 maintainer-scripts: Fix jit documentation build with update [...] adds c56871dd15a maintainer-scripts: Fix up gcc_release without -l, where mk [...] adds daf2852b883 Support for the CPEN control register was removed in rev .5 [...] adds 4aded535ea6 Remove no-op register to register copies in CSE just like w [...] adds 54e69cb00da Daily bump. adds 82f620e2ba4 Fix unaligned load with small memcpy on the ARM adds 3e6ab5cefa8 Fix incorrect filling of delay slots in branchy code at -O2 adds dbf3dc75888 aarch64: Add --params to control the number of recip steps [...] adds fd8679974b2 i386: Use ix86_output_ssemov for DFmode TYPE_SSEMOV adds 7aa605c9d46 aarch64: Fix another bug in aarch64_add_offset_1 [PR94121] adds 43d513af3f2 [testsuite] Fix PR93935 to guard case under vect_hw_misalign adds 98ff89d1ac5 Do not strcat to result of getenv. adds 3604480a6fe tree-optimization/94163 constrain alignment set by PRE adds 80a13af724a c++: Redundant -Wdeprecated-declarations warning in build_o [...] adds 5c7e6d4bdf8 df: Don't abuse bb->aux (PR94148, PR94042) adds 9ae8bc02774 testsuite: Assorted x32 testsuite fixes adds f2e9fe5f97d PR c/94040 - ICE on a call to an invalid redeclaration of strftime adds 3b515f74841 Fix wrong year in ChangeLog. adds 45ee7a35f34 PR c/94040 - ICE on a call to an invalid redeclaration of strftime adds a4504f32c05 PR92303: Try to simplify memory subreg. adds db3fa3476e9 testsuite: Fix misquoted string in bfcvt-nosimd.c adds 5b74dd0a227 d/dmd: Merge upstream dmd e9420cfbf adds 5c048755ec9 analyzer: handle NOP_EXPR in get_lvalue [PR94099,PR94105] adds 50c96067c8e Fix UBSAN error, shifting 64 bit value by 64. adds 0034955eb16 Daily bump. adds 53b28abf8e4 Fix doubled indefinite articles, mostly in comments. adds 9a6408bd18f rs6000/test: Fix selector in fold-vec-mule-misc.c adds 6e5084b4401 libphobos: Merge upstream druntime 7915b6a3 adds c393c99d3dc c++: Fix CTAD with multiple-arg ctor template [93248]. adds b3b0c671cc3 c++: Find parameter pack in typedef in lambda [92909]. adds 3a285529ee3 c++: Fix ICE-after-error on partial spec [92068] adds 824722e45f8 i386: Use ix86_output_ssemov for DImode TYPE_SSEMOV adds 89769d70af2 Daily bump. adds 9c3cdb43c2b tree-nested: Fix handling of *reduction clauses with C arra [...] adds b408e010ccf driver: Fix redundant descriptions in options adds ced66da3135 coroutines: Fix indentation (NFC). adds 9d74caf21be i386: Use ix86_output_ssemov for SFmode TYPE_SSEMOV adds 5e5ce5371f6 Daily bump. adds e4e9a59105a Update post order number for merged SCC. adds 5ba25b2ef17 tree-inline: Fix a -fcompare-debug issue in the inliner [PR94167] adds 6d44c881286 tree-inline: Fix a -fcompare-debug issue in the inliner [PR94167] adds f2d3807f580 libphobos: Merge upstream druntime 6c45dd3a, phobos 68cc18adb. adds e41d4a0a567 d/dmd: Merge upstream dmd b061bd744 adds 5a3c42b227b i386: Use ix86_output_ssemov for SImode TYPE_SSEMOV adds 136fec1e27f x32 does not support MS ABI, skip testcases that require it. adds f19b40bd377 Fix ChangeLog formatting from my commit last friday. adds bc093503d74 libphobos: Reset libtool_VERSION to 1:0:0 adds 63c8f7d6a08 [ARM][GCC][1/x]: MVE ACLE intrinsics framework patch. adds c7be0832b54 [ARM][GCC][2/x]: MVE ACLE intrinsics framework patch. adds 5dee500b359 [ARM][GCC][3/x]: MVE ACLE intrinsics framework patch. adds f522810d2b5 [testsuite] Avoid duplicate test names in sizeless tests adds bae7b38cf8a Fix PR94185: Do not reuse insn alternative after changing m [...] adds c015ff8ccaf c: Handle MEM_REF in c_fully_fold* [PR94179] adds 447d196e75d d: Fix multiple definition error when using mixins and interfaces. adds c62f5e6e1f4 libstdc++: Add default constructor to net::service_already_ [...] adds 2691ffe6dba d: Fix assignment to anonymous union member corrupts siblin [...] adds b3f246f12b2 Daily bump. adds 950183c7741 Update gcc sv.po. adds 57e7ad5a8fd c++: Add test for PR 93901. adds ecf2b69a629 Filter a test-case with gas. adds 7afa3b82918 expand: Don't depend on warning flags in code generation of [...] adds 741ff2a263f strlen: Punt on UB reads past end of string literal [PR94187] adds fd857de8070 c: ignore initializers for elements of variable-size types [...] adds 994d4862062 testsuite: Fix pr94185.C testcase on i686-linux with C++98 [...] adds 14782c8123e [ARM][GCC][4/x]: MVE ACLE vector interleaving store intrinsics. adds a50f6abffc3 [ARM][GCC][1/1x]: Patch to support MVE ACLE intrinsics with [...] adds 5db0eb95c34 [ARM][GCC][2/1x]: MVE intrinsics with unary operand. adds a9a437ffc42 tree-ssa-strlen: Fix up count_nonzero_bytes* [PR94015] adds f582ca0fd70 [GCC][PATCH][ARM] Add multilib mapping for Armv8.1-M+MVE wi [...] adds 700d4cb08c8 Fix up duplicated duplicated words mostly in comments adds 6df4618cac9 [ARM][GCC][3/1x]: MVE intrinsics with unary operand. adds a475f153431 [ARM][GCC][4/1x]: MVE intrinsics with unary operand. adds 4be8cf77026 [ARM][GCC][1/2x]: MVE intrinsics with binary operands. adds 887085be635 c++: Fix access checks for __is_assignable and __is_constructible adds f166a8cdf48 [ARM][GCC][2/2x]: MVE intrinsics with binary operands. adds d71dba7b611 [ARM][GCC][3/2x]: MVE intrinsics with binary operands. adds 33203b4c27d [ARM][GCC][4/2x]: MVE intrinsics with binary operands. adds f9355dee93f [ARM][GCC][5/2x]: MVE intrinsics with binary operands. adds 0dad5b33687 [ARM][GCC][1/3x]: MVE intrinsics with ternary operands. adds e4596b66710 coroutines, testsuite: Fix single test execution. adds 1fef0148be4 Fix the ChangeLog after the __is_assignable/__is_constructible fix adds cf9c3bff39c aarch64: Fix bf16_v(ld|st)n.c failures for big-endian adds 58a703f0726 testsuite: Fix gcc.target/aarch64/advsimd-intrinsics/bfcvt- [...] adds cd0b7124273 c++: Fix parsing of invalid enum specifiers [PR90995] adds 046c58907ec c: Handle C_TYPE_INCOMPLETE_VARS even for ENUMERAL_TYPEs [PR94172] adds 2e30d3e3e88 testsuite: Fix g++.dg/debug/dwarf2/const2b.C target selector adds 3b2cc34369a Daily bump. adds 98f29f5638f libstdc++: Fix type-erasure in experimental::net::executor [...] adds 80616e5b7a5 c++: Fix comment typo. adds 52b3aa8be18 dwarf: Generate DIEs for external variables with -g1 [93751] adds af8656be8df c++: Diagnose a deduction guide in a wrong scope [PR91759] adds 4e3d3e40726 middle-end/94188 fix fold of addr expression generation adds 4da9288745d libgomp testsuite - disable long double for AMDGCN adds cb26919c857 aarch64: Treat p12-p15 as call-preserved in SVE PCS functions adds d91480dee93 aarch64: Fix SYMBOL_TINY_GOT handling for ILP32 [PR94201] adds d5029d45940 Fix up duplicated duplicated words in comments adds 1ba9acb11e3 middle-end/94206 fix memset folding to avoid types with padding adds 11cf25c40e3 PR c++/94147 - mangling of lambdas assigned to globals adds 5a80a6c3e5f amdgcn: Add cond_add/sub/and/ior/xor for all vector modes adds dbde9e2d595 amdgcn: Fix vector compare modes adds 07522ae90b5 libstdc++: Fix compilation with released versions of Clang adds e5de406f996 libstdc++ Fix compilation of <stop_token> with Clang adds 0db2cd17702 analyzer: tweaks to exploded_node ctor adds 7d9c107ab1e analyzer: introduce noop_region_model_context adds f665beeba62 analyzer: add test coverage for fixed ICE [PR94047] adds 884d9141112 analyzer: make summarized dumps more comprehensive adds 26cbcfe5fce Fix libgomp.oacc-fortran/atomic_capture-1.f90 adds 8165795c155 [ARM][GCC][2/3x]: MVE intrinsics with ternary operands. adds e3678b4464a [ARM][GCC][3/3x]: MVE intrinsics with ternary operands. adds db5db9d2548 [ARM][GCC][1/4x]: MVE intrinsics with quaternary operands. adds 8eb3b6b9cf2 [ARM][GCC][2/4x]: MVE intrinsics with quaternary operands. adds f2170a379b0 [ARM][GCC][3/4x]: MVE intrinsics with quaternary operands. adds 532e9e2402a [ARM][GCC][4/4x]: MVE intrinsics with quaternary operands. adds 4ff68575991 [ARM][GCC][1/5x]: MVE store intrinsics. adds 535a8645bb8 [ARM][GCC][2/5x]: MVE load intrinsics. adds 405e918c314 [ARM][GCC][3/5x]: MVE store intrinsics with predicated suffix. adds 429d607bc46 [ARM][GCC][4/5x]: MVE load intrinsics with zero(_z) suffix. adds bf1e3d5afa1 [ARM][GCC][5/5x]: MVE ACLE load intrinsics which load a byt [...] adds 4cc23303bad [ARM][GCC][6/5x]: Remaining MVE load intrinsics which loads [...] adds 5cad47e0f85 [ARM][GCC][7/5x]: MVE store intrinsics which stores byte,ha [...] adds 7a5fffa5ed0 [ARM][GCC][8/5x]: Remaining MVE store intrinsics which stor [...] adds 3512dc0108a PR ipa/92799 - ICE on a weakref function definition followe [...] adds 529ea7d9596 Complete change to resolve pr90275. adds 07fe4af4d51 rs6000: Add back some w* constraints (PR91886) adds b3341826531 libstdc++: Fix is_trivially_constructible (PR 94033) adds b5562f1187d Daily bump. adds 73bc09fa8c6 middle-end/94216 fix another build_fold_addr_expr use adds f3280e4c0c9 ipa/94217 simplify offsetted address build adds c7e90196818 phiopt: Avoid -fcompare-debug bug in phiopt [PR94211] adds bb83e069eba libgomp/testsuite: ignore blank-line output for function-no [...] adds 02f7334ac93 c++: Fix up handling of captured vars in lambdas in OpenMP [...] adds f5389e17e4b Update include/plugin-api.h. adds c8429c2aba8 API extension for binutils (type of symbols). adds f22712bd8a2 Fix inliner ICE on alias with flatten attribute [PR92372] adds 37482edc3f7 d/dmd: Merge upstream dmd d1a606599 adds 9def91e9f2a c: Fix up cfun->function_end_locus from the C FE [PR94029] adds f7dceb4e658 Fix cgraph_node::function_symbol availability compuattion [ [...] adds 3373d3e38ea Daily bump. adds 94e2418780f c++: Avoid unnecessary empty class copy [94175]. adds 4a18f168f47 [rs6000] Rewrite the declaration of a variable adds 05009698eeb gcc, Arm: Fix no_cond issue introduced by MVE adds 4119cd693d2 store-merging: Fix up -fnon-call-exceptions handling [PR94224] adds 0efe7d8796e gcc, Arm: Fix MVE move from GPR -> GPR adds 005f6fc59e5 gcc, Arm: Fix testisms for MVE testsuite adds 719c864225e gcc, Arm: Revert changes to {get,set}_fpscr adds 8fefa21fcf6 tree-optimization/94266 - fix object type extraction heuristics adds 7d4549b2cd2 Fix correct offset in ipa_get_jf_ancestor_result. adds 3eff57aacfe [ARM][GCC][6x]:MVE ACLE vaddq intrinsics using arithmetic p [...] adds 85a94e87901 [ARM][GCC][7x]: MVE vreinterpretq and vuninitializedq intrinsics. adds 92f80065d10 [ARM][GCC][1/8x]: MVE ACLE vidup, vddup, viwdup and vdwdup [...] adds 41e1a7ffae9 [ARM][GCC][2/8x]: MVE ACLE gather load and scatter store in [...] adds 3d42842c07f fix CTOR vectorization adds 261014a1be4 [ARM][GCC][9x]: MVE ACLE predicated intrinsics with (dont-c [...] adds 828878c35c8 c++: Include the constraint parameter mapping in diagnostic [...] adds c3562f81042 [ARM][GCC][10x]: MVE ACLE intrinsics "add with carry across [...] adds 1aa22b1916a c-family: Tighten vector handling in type_for_mode [PR94072] adds b5446d0cc09 d: Fix SEGV in hash_table<odr_name_hasher, false, xcallocat [...] adds 1dfcc3b541c [ARM][GCC][11x]: MVE ACLE vector interleaving store and dei [...] adds a23eff1bd04 c++: Add testcases from PR c++/69694 adds a89349e664f adjust SLP tree dumping adds 72b3bc895f0 Fix verifier ICE on wrong comdat local flag [PR93347] adds 68dd57808f7 rs6000: Add command line and builtin compatibility check adds cc3afc9db07 Regenerate gcc.pot. adds 29f23ed79b6 sra: Cap number of sub-access propagations with a param (PR 93435) adds 8416602026d Daily bump. adds 15711e837b2 Fix comma at end of enumerator list seen with -std=c++98. adds 497498c878d lra: Tighten check for reloading paradoxical subregs [PR94052]

No new revisions were added by this update.

Summary of changes: ChangeLog | 13 + MAINTAINERS | 3 + configure | 2 +- configure.ac | 2 +- gcc/ChangeLog | 8660 ++++++ gcc/DATESTAMP | 2 +- gcc/Makefile.in | 1 + gcc/ada/ChangeLog | 5 + gcc/ada/gcc-interface/decl.c | 9 +- gcc/alias.c | 102 +- gcc/alias.h | 2 + gcc/analyzer/ChangeLog | 321 + gcc/analyzer/analyzer.cc | 61 + gcc/analyzer/analyzer.h | 11 +- gcc/analyzer/analyzer.opt | 4 + gcc/analyzer/bar-chart.cc | 102 + gcc/analyzer/bar-chart.h | 60 + gcc/analyzer/checker-path.cc | 2 +- gcc/analyzer/checker-path.h | 4 +- gcc/analyzer/diagnostic-manager.cc | 225 +- gcc/analyzer/diagnostic-manager.h | 15 +- gcc/analyzer/engine.cc | 180 +- gcc/analyzer/exploded-graph.h | 20 +- gcc/analyzer/program-state.cc | 174 +- gcc/analyzer/program-state.h | 3 +- gcc/analyzer/reachability.h | 76 + gcc/analyzer/region-model.cc | 635 +- gcc/analyzer/region-model.h | 154 +- gcc/analyzer/sm-malloc.cc | 5 +- gcc/analyzer/sm.cc | 20 +- gcc/analyzer/sm.h | 2 + gcc/analyzer/supergraph.cc | 23 + gcc/analyzer/supergraph.h | 4 + gcc/asan.c | 7 +- gcc/bb-reorder.c | 6 +- gcc/builtins.c | 22 +- gcc/c-family/ChangeLog | 33 + gcc/c-family/c-attribs.c | 21 +- gcc/c-family/c-common.c | 13 +- gcc/c-family/c-pragma.c | 2 +- gcc/c-family/c.opt | 28 +- gcc/c/ChangeLog | 71 + gcc/c/c-decl.c | 183 +- gcc/c/c-fold.c | 9 + gcc/c/c-parser.c | 51 +- gcc/c/c-tree.h | 14 +- gcc/c/c-typeck.c | 52 +- gcc/c/gimple-parser.c | 7 +- gcc/calls.c | 5 + gcc/cfgexpand.c | 2 +- gcc/cfghooks.c | 4 +- gcc/cfgloop.h | 1 - gcc/cgraph.c | 90 +- gcc/cgraph.h | 17 +- gcc/cgraphunit.c | 21 +- gcc/combine.c | 5 +- gcc/common.opt | 20 +- gcc/common/config/arm/arm-common.c | 3 +- gcc/config.gcc | 4 +- gcc/config/aarch64/aarch64-builtins.c | 14 + gcc/config/aarch64/aarch64-simd-builtins.def | 15 + gcc/config/aarch64/aarch64-simd.md | 89 +- gcc/config/aarch64/aarch64-sve.md | 2 +- gcc/config/aarch64/aarch64-sve2.md | 2 + gcc/config/aarch64/aarch64.c | 69 +- gcc/config/aarch64/aarch64.md | 22 +- gcc/config/aarch64/aarch64.opt | 9 + gcc/config/aarch64/arm_bf16.h | 13 + gcc/config/aarch64/arm_neon.h | 1297 +- .../aarch64/falkor-tag-collision-avoidance.c | 2 +- gcc/config/aarch64/iterators.md | 48 +- gcc/config/arc/arc.c | 40 +- gcc/config/arc/arc.md | 120 +- gcc/config/arc/arc.opt | 4 +- gcc/config/arc/fpu.md | 4 +- gcc/config/arm/aout.h | 6 +- gcc/config/arm/arm-builtins.c | 723 +- gcc/config/arm/arm-c.c | 10 + gcc/config/arm/arm-cpus.in | 14 +- gcc/config/arm/arm-modes.def | 1 + gcc/config/arm/arm-protos.h | 3 +- gcc/config/arm/arm-simd-builtin-types.def | 1 + gcc/config/arm/arm.c | 319 +- gcc/config/arm/arm.h | 69 +- gcc/config/arm/arm.md | 36 +- gcc/config/arm/arm_bf16.h | 14 + gcc/config/arm/arm_mve.h | 27105 +++++++++++++++++++ gcc/config/arm/arm_mve_builtins.def | 878 + gcc/config/arm/arm_neon.h | 872 +- gcc/config/arm/arm_neon_builtins.def | 59 +- gcc/config/arm/constraints.md | 54 +- gcc/config/arm/iterators.md | 75 +- gcc/config/arm/mve.md | 10887 ++++++++ gcc/config/arm/neon.md | 376 +- gcc/config/arm/predicates.md | 46 +- gcc/config/arm/t-arm | 5 +- gcc/config/arm/t-rmprofile | 13 +- gcc/config/arm/thumb1.md | 16 +- gcc/config/arm/thumb2.md | 2 +- gcc/config/arm/types.md | 18 +- gcc/config/arm/unspecs.md | 7 + gcc/config/arm/vec-common.md | 83 +- gcc/config/arm/vfp.md | 128 +- gcc/config/bfin/bfin.md | 3 +- gcc/config/cr16/cr16.opt | 2 +- gcc/config/fr30/fr30.c | 2 +- gcc/config/gcn/gcn-run.c | 2 +- gcc/config/gcn/gcn-valu.md | 198 +- gcc/config/gcn/gcn.c | 111 +- gcc/config/gcn/gcn.h | 4 + gcc/config/gcn/gcn.md | 28 +- gcc/config/i386/avx2intrin.h | 8 +- gcc/config/i386/i386-features.c | 2 +- gcc/config/i386/i386-protos.h | 2 + gcc/config/i386/i386.c | 244 +- gcc/config/i386/i386.md | 231 +- gcc/config/i386/mmx.md | 29 +- gcc/config/i386/predicates.md | 5 - gcc/config/i386/sse.md | 98 +- gcc/config/i386/x86-tune.def | 2 +- gcc/config/i386/xopintrin.h | 8 +- gcc/config/lm32/lm32.c | 8 +- gcc/config/msp430/msp430.c | 2 +- gcc/config/nds32/nds32-md-auxiliary.c | 12 +- gcc/config/nvptx/nvptx.c | 2 +- gcc/config/pdp11/pdp11.c | 3 +- gcc/config/riscv/riscv.c | 18 +- gcc/config/rs6000/aix61.h | 4 +- gcc/config/rs6000/aix71.h | 4 +- gcc/config/rs6000/aix72.h | 4 +- gcc/config/rs6000/constraints.md | 11 + gcc/config/rs6000/rs6000-c.c | 15 +- gcc/config/rs6000/rs6000-cpus.def | 4 + gcc/config/rs6000/rs6000-internal.h | 3 - gcc/config/rs6000/rs6000-logue.c | 2 +- gcc/config/rs6000/rs6000-p8swap.c | 2 +- gcc/config/rs6000/rs6000-string.c | 2 +- gcc/config/rs6000/rs6000.c | 32 +- gcc/config/rs6000/rs6000.h | 4 + gcc/config/rs6000/rs6000.opt | 3 +- gcc/config/rs6000/vsx.md | 104 +- gcc/config/rx/rx.c | 1 - gcc/config/rx/rx.md | 1 - gcc/config/s390/s390.c | 60 +- gcc/config/s390/s390.h | 8 +- gcc/config/s390/s390.md | 4 +- gcc/config/s390/tpf.h | 16 + gcc/config/s390/tpf.md | 12 +- gcc/config/s390/tpf.opt | 20 + gcc/config/sh/sh.c | 2 +- gcc/config/v850/v850.c | 2 +- gcc/config/v850/v850.h | 5 +- gcc/config/vx-common.h | 14 +- gcc/configure | 2 +- gcc/configure.ac | 2 +- gcc/cp/ChangeLog | 411 + gcc/cp/call.c | 74 +- gcc/cp/class.c | 21 +- gcc/cp/constexpr.c | 74 +- gcc/cp/constraint.cc | 47 +- gcc/cp/coroutines.cc | 648 +- gcc/cp/cp-gimplify.c | 50 +- gcc/cp/cp-tree.h | 4 + gcc/cp/cxx-pretty-print.c | 37 +- gcc/cp/cxx-pretty-print.h | 1 + gcc/cp/decl.c | 51 +- gcc/cp/error.c | 35 +- gcc/cp/except.c | 4 +- gcc/cp/init.c | 13 +- gcc/cp/logic.cc | 10 +- gcc/cp/mangle.c | 4 +- gcc/cp/method.c | 10 +- gcc/cp/name-lookup.c | 2 +- gcc/cp/parser.c | 176 +- gcc/cp/pt.c | 121 +- gcc/cp/tree.c | 47 +- gcc/cp/typeck.c | 10 +- gcc/cp/typeck2.c | 6 +- gcc/cse.c | 15 +- gcc/d/ChangeLog | 31 + gcc/d/d-target.cc | 2 +- gcc/d/d-tree.h | 5 + gcc/d/decl.cc | 17 +- gcc/d/dmd/MERGE | 2 +- gcc/d/dmd/attrib.c | 189 +- gcc/d/dmd/attrib.h | 9 +- gcc/d/dmd/cond.c | 333 +- gcc/d/dmd/cond.h | 5 +- gcc/d/dmd/cppmangle.c | 2 +- gcc/d/dmd/dclass.c | 1 - gcc/d/dmd/declaration.c | 9 + gcc/d/dmd/dinterpret.c | 4 + gcc/d/dmd/dmangle.c | 1 + gcc/d/dmd/dsymbol.c | 100 +- gcc/d/dmd/dsymbol.h | 2 + gcc/d/dmd/expression.c | 10 + gcc/d/dmd/expression.h | 2 + gcc/d/dmd/expressionsem.c | 28 +- gcc/d/dmd/func.c | 4 +- gcc/d/dmd/hdrgen.c | 68 +- gcc/d/dmd/iasmgcc.c | 30 +- gcc/d/dmd/init.c | 2 +- gcc/d/dmd/intrange.c | 2 +- gcc/d/dmd/json.c | 4 + gcc/d/dmd/module.h | 1 + gcc/d/dmd/mtype.c | 152 +- gcc/d/dmd/mtype.h | 18 + gcc/d/dmd/parse.c | 304 +- gcc/d/dmd/parse.h | 3 + gcc/d/dmd/scope.h | 3 +- gcc/d/dmd/statement.c | 120 + gcc/d/dmd/statement.h | 9 +- gcc/d/dmd/statementsem.c | 581 +- gcc/d/dmd/traits.c | 34 +- gcc/d/dmd/visitor.h | 4 + gcc/d/expr.cc | 2 +- gcc/d/types.cc | 58 +- gcc/ddg.c | 34 +- gcc/df-core.c | 35 +- gcc/dfp.c | 10 +- gcc/doc/extend.texi | 10 +- gcc/doc/install.texi | 71 +- gcc/doc/invoke.texi | 1659 +- gcc/doc/tm.texi | 10 +- gcc/doc/tm.texi.in | 6 +- gcc/dse.c | 9 +- gcc/dwarf2out.c | 76 +- gcc/explow.c | 3 + gcc/expmed.c | 55 +- gcc/fold-const.c | 9 +- gcc/fortran/ChangeLog | 114 + gcc/fortran/arith.c | 2 +- gcc/fortran/array.c | 2 +- gcc/fortran/class.c | 2 +- gcc/fortran/decl.c | 27 +- gcc/fortran/frontend-passes.c | 2 +- gcc/fortran/interface.c | 6 +- gcc/fortran/intrinsic.texi | 2 +- gcc/fortran/lang.opt | 2 +- gcc/fortran/match.c | 35 +- gcc/fortran/module.c | 12 +- gcc/fortran/openmp.c | 12 +- gcc/fortran/resolve.c | 33 +- gcc/fortran/simplify.c | 17 +- gcc/fortran/trans-array.c | 50 +- gcc/fortran/trans-expr.c | 13 +- gcc/fortran/trans-intrinsic.c | 21 +- gcc/fortran/trans-types.c | 2 +- gcc/gcc.c | 29 + gcc/gdbinit.in | 2 +- gcc/gimple-fold.c | 12 +- gcc/gimple-loop-versioning.cc | 2 +- gcc/gimple-ssa-sprintf.c | 10 +- gcc/gimple-ssa-store-merging.c | 33 +- gcc/gimple-ssa-warn-restrict.c | 25 +- gcc/gimple.c | 13 + gcc/gimple.h | 2 + gcc/gimplify.c | 1 + gcc/go/gofrontend/MERGE | 2 +- gcc/graphite-isl-ast-to-gimple.c | 3 + gcc/graphite-scop-detection.c | 1 - gcc/haifa-sched.c | 9 + gcc/hsa-common.c | 2 +- gcc/hsa-common.h | 2 +- gcc/input.c | 4 +- gcc/ipa-cp.c | 68 +- gcc/ipa-fnsummary.c | 4 - gcc/ipa-inline-transform.c | 9 +- gcc/ipa-inline.c | 3 + gcc/ipa-param-manipulation.h | 2 +- gcc/ipa-predicate.c | 2 +- gcc/ipa-prop.h | 4 +- gcc/ipa-split.c | 2 +- gcc/ira-color.c | 97 +- gcc/ira-costs.c | 2 +- gcc/langhooks.h | 2 +- gcc/loop-iv.c | 2 +- gcc/lra-constraints.c | 24 +- gcc/lra-spills.c | 21 +- gcc/lto-opts.c | 9 + gcc/lto-section-in.c | 1 + gcc/lto-streamer-out.c | 85 +- gcc/lto-streamer.h | 1 + gcc/lto-wrapper.c | 106 +- gcc/match.pd | 9 + gcc/omp-expand.c | 4 +- gcc/omp-grid.c | 2 +- gcc/optabs-tree.c | 5 + gcc/optinfo-emit-json.cc | 2 +- gcc/opts-common.c | 66 + gcc/opts.h | 5 + gcc/params.opt | 8 + gcc/passes.c | 2 + gcc/po/ChangeLog | 20 + gcc/po/de.po | 4161 ++- gcc/po/fr.po | 6101 ++--- gcc/po/gcc.pot | 15239 ++++++----- gcc/po/sv.po | 480 +- gcc/predict.c | 2 +- gcc/print-rtl.c | 4 +- gcc/read-rtl-function.c | 6 +- gcc/reorg.c | 26 +- gcc/resource.c | 21 +- gcc/resource.h | 1 + gcc/rtl.c | 2 +- gcc/selftest.c | 2 +- gcc/shrink-wrap.c | 2 +- gcc/spellcheck.c | 2 +- gcc/symtab.c | 11 + gcc/target.def | 6 +- gcc/testsuite/ChangeLog | 3807 ++- .../c-c++-common/goacc/firstprivate-mappings-1.c | 12 +- gcc/testsuite/g++.dg/DRs/dr1423.C | 7 + gcc/testsuite/g++.dg/abi/align3.C | 12 + gcc/testsuite/g++.dg/abi/empty30.C | 14 + gcc/testsuite/g++.dg/abi/lambda-vis.C | 23 + gcc/testsuite/g++.dg/abi/mangle74.C | 30 + gcc/testsuite/g++.dg/analyzer/cstdlib-2.C | 25 + gcc/testsuite/g++.dg/analyzer/cstdlib.C | 17 + gcc/testsuite/g++.dg/analyzer/pr93899.C | 2 + gcc/testsuite/g++.dg/analyzer/pr93950.C | 28 + gcc/testsuite/g++.dg/analyzer/pr94028.C | 36 + gcc/testsuite/g++.dg/asan/asan_test.C | 2 +- gcc/testsuite/g++.dg/concepts/diagnostic2.C | 30 + gcc/testsuite/g++.dg/concepts/diagnostic3.C | 29 + gcc/testsuite/g++.dg/concepts/diagnostic4.C | 18 + gcc/testsuite/g++.dg/concepts/diagnostic6.C | 14 + gcc/testsuite/g++.dg/concepts/pr93729.C | 15 + gcc/testsuite/g++.dg/concepts/pr93933.C | 31 + .../g++.dg/coroutines/coro1-refs-and-ctors.h | 144 + .../g++.dg/coroutines/coro1-ret-int-yield-int.h | 10 + .../torture/class-05-lambda-capture-copy-local.C | 4 +- .../coroutines/torture/class-07-data-member.C | 61 + .../torture/co-await-14-template-traits.C | 24 + .../torture/co-await-15-capture-comp-ref.C | 99 + .../torture/co-await-15-return-non-triv.C | 51 + .../torture/co-ret-15-default-return_void.C | 55 + .../g++.dg/coroutines/torture/coro-torture.exp | 14 +- .../g++.dg/coroutines/torture/func-params-07.C | 81 + .../g++.dg/coroutines/torture/func-params-08.C | 112 + .../torture/func-params-09-awaitable-parms.C | 105 + .../coroutines/torture/lambda-09-init-captures.C | 55 + .../g++.dg/coroutines/torture/lambda-10-mutable.C | 48 + .../coroutines/torture/local-var-5-awaitable.C | 73 + gcc/testsuite/g++.dg/cpp0x/constexpr-const3.C | 12 + gcc/testsuite/g++.dg/cpp0x/conv-tmpl2.C | 21 + gcc/testsuite/g++.dg/cpp0x/conv-tmpl3.C | 16 + gcc/testsuite/g++.dg/cpp0x/conv-tmpl4.C | 33 + gcc/testsuite/g++.dg/cpp0x/conv-tmpl5.C | 13 + gcc/testsuite/g++.dg/cpp0x/conv-tmpl6.C | 16 + gcc/testsuite/g++.dg/cpp0x/decltype74.C | 30 + gcc/testsuite/g++.dg/cpp0x/decltype75.C | 24 + gcc/testsuite/g++.dg/cpp0x/enum40.C | 26 + gcc/testsuite/g++.dg/cpp0x/initlist-array11.C | 10 + gcc/testsuite/g++.dg/cpp0x/initlist-overload1.C | 15 + gcc/testsuite/g++.dg/cpp0x/initlist116.C | 29 - gcc/testsuite/g++.dg/cpp0x/initlist117.C | 40 - gcc/testsuite/g++.dg/cpp0x/initlist121.C | 31 + gcc/testsuite/g++.dg/cpp0x/initlist122.C | 16 + gcc/testsuite/g++.dg/cpp0x/lambda/lambda-eh.C | 34 - .../g++.dg/cpp0x/lambda/lambda-variadic10.C | 12 + gcc/testsuite/g++.dg/cpp0x/noexcept57.C | 40 + gcc/testsuite/g++.dg/cpp0x/nsdmi-template19.C | 13 + gcc/testsuite/g++.dg/cpp0x/pr93905.C | 18 + gcc/testsuite/g++.dg/cpp0x/rv-cast7.C | 6 + gcc/testsuite/g++.dg/cpp0x/variadic178.C | 6 + .../g++.dg/cpp1y/constexpr-tracking-const17.C | 23 + .../g++.dg/cpp1y/constexpr-tracking-const18.C | 23 + .../g++.dg/cpp1y/constexpr-tracking-const19.C | 23 + .../g++.dg/cpp1y/constexpr-tracking-const20.C | 28 + .../g++.dg/cpp1y/constexpr-tracking-const21.C | 28 + .../g++.dg/cpp1y/constexpr-tracking-const22.C | 17 + gcc/testsuite/g++.dg/cpp1z/class-deduction70.C | 7 + gcc/testsuite/g++.dg/cpp1z/class-deduction71.C | 6 + gcc/testsuite/g++.dg/cpp1z/class-deduction72.C | 11 + gcc/testsuite/g++.dg/cpp1z/conv-tmpl1.C | 10 + gcc/testsuite/g++.dg/cpp2a/concepts-conv1.C | 15 + gcc/testsuite/g++.dg/cpp2a/concepts-p2092.C | 8 + gcc/testsuite/g++.dg/cpp2a/concepts-using2.C | 49 + gcc/testsuite/g++.dg/cpp2a/consteval16.C | 7 + gcc/testsuite/g++.dg/cpp2a/consteval3.C | 10 +- gcc/testsuite/g++.dg/cpp2a/consteval6.C | 6 +- gcc/testsuite/g++.dg/cpp2a/constexpr-init16.C | 15 + gcc/testsuite/g++.dg/cpp2a/constexpr-init17.C | 15 + gcc/testsuite/g++.dg/cpp2a/lambda-pack-init4.C | 10 + gcc/testsuite/g++.dg/cpp2a/no_unique_address3.C | 16 + gcc/testsuite/g++.dg/cpp2a/nontype-class33.C | 36 + gcc/testsuite/g++.dg/debug/dwarf2/const2b.C | 2 +- gcc/testsuite/g++.dg/diagnostic/pr67960-2.C | 13 + gcc/testsuite/g++.dg/diagnostic/pr67960.C | 13 + gcc/testsuite/g++.dg/eh/aggregate1.C | 56 - gcc/testsuite/g++.dg/ext/attr-access.C | 109 + gcc/testsuite/g++.dg/ext/consteval1.C | 4 +- gcc/testsuite/g++.dg/ext/pr93998.C | 14 + gcc/testsuite/g++.dg/ext/pr94197.C | 74 + gcc/testsuite/g++.dg/ext/visibility/ref-temp1.C | 1 + gcc/testsuite/g++.dg/ext/vla22.C | 9 + .../g++.dg/goacc/firstprivate-mappings-1.C | 12 +- gcc/testsuite/g++.dg/guality/pr93888.C | 24 + gcc/testsuite/g++.dg/init/array55.C | 27 + gcc/testsuite/g++.dg/init/array56.C | 107 + gcc/testsuite/g++.dg/ipa/pr93763.C | 2 +- gcc/testsuite/g++.dg/pr80481.C | 6 +- gcc/testsuite/g++.dg/pr90981.C | 1 + gcc/testsuite/g++.dg/pr94027.C | 22 + gcc/testsuite/g++.dg/template/deduce4.C | 17 + gcc/testsuite/g++.dg/template/deduce5.C | 17 + gcc/testsuite/g++.dg/template/deduce6.C | 17 + gcc/testsuite/g++.dg/template/deduce7.C | 10 + gcc/testsuite/g++.dg/torture/pr92152.C | 74 + gcc/testsuite/g++.dg/torture/pr93347.C | 306 + gcc/testsuite/g++.dg/torture/pr94202.C | 22 + gcc/testsuite/g++.dg/torture/pr94216.C | 45 + gcc/testsuite/g++.dg/tree-ssa/pr90883.C | 6 +- gcc/testsuite/g++.dg/tree-ssa/pr94224.C | 34 + gcc/testsuite/g++.dg/warn/Wconversion-pr94067.C | 9 + gcc/testsuite/g++.dg/warn/Wmismatched-tags-2.C | 6 + gcc/testsuite/g++.dg/warn/Wredundant-tags-4.C | 142 + gcc/testsuite/g++.dg/warn/Wredundant-tags-5.C | 109 + gcc/testsuite/g++.dg/warn/Wredundant-tags-5.h | 80 + gcc/testsuite/g++.target/aarch64/pr94052.C | 174 + gcc/testsuite/g++.target/i386/pr94046-1.C | 55 + gcc/testsuite/g++.target/i386/pr94046-2.C | 5 + gcc/testsuite/g++.target/i386/pr94185.C | 33 + gcc/testsuite/gcc.c-torture/compile/20200313-1.c | 14 + gcc/testsuite/gcc.c-torture/compile/pr90275.c | 27 + gcc/testsuite/gcc.c-torture/compile/pr93927-1.c | 9 + gcc/testsuite/gcc.c-torture/compile/pr93927-2.c | 9 + gcc/testsuite/gcc.c-torture/compile/pr93949.c | 7 + gcc/testsuite/gcc.c-torture/compile/pr94179.c | 9 + gcc/testsuite/gcc.c-torture/execute/pr90311.c | 16 + gcc/testsuite/gcc.c-torture/execute/pr93582.c | 22 + gcc/testsuite/gcc.c-torture/execute/pr93908.c | 54 + gcc/testsuite/gcc.c-torture/execute/pr93945.c | 45 + gcc/testsuite/gcc.c-torture/execute/pr94130.c | 16 + gcc/testsuite/gcc.c-torture/execute/pr94134.c | 14 + gcc/testsuite/gcc.c-torture/pr92372.c | 16 + .../gcc.dg/Wbuiltin-declaration-mismatch-12.c | 4 +- .../gcc.dg/Wbuiltin-declaration-mismatch-13.c | 78 + .../gcc.dg/Wbuiltin-declaration-mismatch-14.c | 77 + .../gcc.dg/Wbuiltin-declaration-mismatch-15.c | 56 + gcc/testsuite/gcc.dg/Wstringop-overflow-32.c | 51 + .../gcc.dg/analyzer/CVE-2005-1689-dedupe-issue.c | 2 + .../gcc.dg/analyzer/analyzer-verbosity-2a.c | 20 + .../gcc.dg/analyzer/analyzer-verbosity-3.c | 222 + .../gcc.dg/analyzer/analyzer-verbosity-3a.c | 20 + gcc/testsuite/gcc.dg/analyzer/edges-1.c | 54 + gcc/testsuite/gcc.dg/analyzer/edges-2.c | 20 + gcc/testsuite/gcc.dg/analyzer/expect-1.c | 32 + gcc/testsuite/gcc.dg/analyzer/file-paths-1.c | 2 + gcc/testsuite/gcc.dg/analyzer/malloc-4.c | 20 + gcc/testsuite/gcc.dg/analyzer/pr93382.c | 2 + gcc/testsuite/gcc.dg/analyzer/pr94047.c | 23 + gcc/testsuite/gcc.dg/analyzer/pr94099.c | 27 + gcc/testsuite/gcc.dg/analyzer/pr94105.c | 3 + gcc/testsuite/gcc.dg/analyzer/taint-1.c | 2 + gcc/testsuite/gcc.dg/analyzer/torture/pr93947.c | 40 + gcc/testsuite/gcc.dg/attr-flatten-1.c | 18 + gcc/testsuite/gcc.dg/attr-weakref-5.c | 31 + gcc/testsuite/gcc.dg/debug/dwarf2/pr93751-1.c | 6 + gcc/testsuite/gcc.dg/debug/dwarf2/pr93751-2.c | 6 + gcc/testsuite/gcc.dg/decl-1.c | 2 +- gcc/testsuite/gcc.dg/dfp/pr94111.c | 12 + gcc/testsuite/gcc.dg/format/proto.c | 89 + gcc/testsuite/gcc.dg/gnu2x-attrs-1.c | 1 + gcc/testsuite/gcc.dg/graphite/pr93964.c | 19 + gcc/testsuite/gcc.dg/ipa/ipa-sra-12.c | 4 +- gcc/testsuite/gcc.dg/ipa/ipa-sra-14.c | 6 +- gcc/testsuite/gcc.dg/ipa/ipcp-agg-12.c | 2 +- gcc/testsuite/gcc.dg/ipa/pr93707.c | 31 + gcc/testsuite/gcc.dg/ipa/pr93763.c | 28 +- gcc/testsuite/gcc.dg/lto/pr94157_0.c | 7 + gcc/testsuite/gcc.dg/pr62090.c | 2 + gcc/testsuite/gcc.dg/pr89314.c | 2 +- gcc/testsuite/gcc.dg/pr90756.c | 1 + gcc/testsuite/gcc.dg/pr93399.c | 17 + gcc/testsuite/gcc.dg/pr93577-1.c | 16 + gcc/testsuite/gcc.dg/pr93577-2.c | 16 + gcc/testsuite/gcc.dg/pr93577-3.c | 17 + gcc/testsuite/gcc.dg/pr93577-4.c | 17 + gcc/testsuite/gcc.dg/pr93577-5.c | 11 + gcc/testsuite/gcc.dg/pr93577-6.c | 11 + gcc/testsuite/gcc.dg/pr93582.c | 57 + gcc/testsuite/gcc.dg/pr93820-2.c | 30 + gcc/testsuite/gcc.dg/pr93820.c | 26 + gcc/testsuite/gcc.dg/pr93874.c | 6 + gcc/testsuite/gcc.dg/pr93953.c | 17 + gcc/testsuite/gcc.dg/pr93986.c | 16 + gcc/testsuite/gcc.dg/pr93995.c | 46 + gcc/testsuite/gcc.dg/pr94001.c | 11 + gcc/testsuite/gcc.dg/pr94002.c | 13 + gcc/testsuite/gcc.dg/pr94015.c | 107 + gcc/testsuite/gcc.dg/pr94114.c | 13 + gcc/testsuite/gcc.dg/pr94121.c | 16 + gcc/testsuite/gcc.dg/pr94166.c | 24 + gcc/testsuite/gcc.dg/pr94167.c | 33 + gcc/testsuite/gcc.dg/pr94172-1.c | 12 + gcc/testsuite/gcc.dg/pr94172-2.c | 19 + gcc/testsuite/gcc.dg/pr94188.c | 10 + gcc/testsuite/gcc.dg/pr94189.c | 11 + gcc/testsuite/gcc.dg/pr94211.c | 12 + gcc/testsuite/gcc.dg/pragma-diag-8.c | 20 + gcc/testsuite/gcc.dg/spellcheck-options-21.c | 1 + gcc/testsuite/gcc.dg/strlenopt-68.c | 1 + gcc/testsuite/gcc.dg/strlenopt-94.c | 28 + gcc/testsuite/gcc.dg/torture/20190327-1.c | 1 + gcc/testsuite/gcc.dg/torture/20200311-1.c | 26 + gcc/testsuite/gcc.dg/torture/pr54261-1.c | 14 +- gcc/testsuite/gcc.dg/torture/pr90020.c | 1 + gcc/testsuite/gcc.dg/torture/pr92152.c | 23 + gcc/testsuite/gcc.dg/torture/pr93868.c | 31 + gcc/testsuite/gcc.dg/torture/pr93946-1.c | 27 + gcc/testsuite/gcc.dg/torture/pr93946-2.c | 28 + gcc/testsuite/gcc.dg/torture/pr94206.c | 17 + gcc/testsuite/gcc.dg/tree-ssa/20030807-7.c | 2 +- .../gcc.dg/tree-ssa/alias-access-path-12.c | 20 + .../gcc.dg/tree-ssa/alias-access-path-4.c | 2 +- .../gcc.dg/tree-ssa/alias-access-path-5.c | 2 +- .../gcc.dg/tree-ssa/builtin-sprintf-warn-24.c | 22 + gcc/testsuite/gcc.dg/tree-ssa/pr93435.c | 159 + gcc/testsuite/gcc.dg/tree-ssa/pr93582-10.c | 29 + gcc/testsuite/gcc.dg/tree-ssa/pr93582-11.c | 16 + gcc/testsuite/gcc.dg/tree-ssa/pr93582-4.c | 23 + gcc/testsuite/gcc.dg/tree-ssa/pr93582-5.c | 25 + gcc/testsuite/gcc.dg/tree-ssa/pr93582-6.c | 24 + gcc/testsuite/gcc.dg/tree-ssa/pr93582-7.c | 24 + gcc/testsuite/gcc.dg/tree-ssa/pr93582-8.c | 14 + gcc/testsuite/gcc.dg/tree-ssa/pr93582-9.c | 23 + gcc/testsuite/gcc.dg/tree-ssa/pr94125.c | 41 + gcc/testsuite/gcc.dg/tree-ssa/scev-10.c | 2 +- gcc/testsuite/gcc.dg/tree-ssa/scev-11.c | 2 +- gcc/testsuite/gcc.dg/tree-ssa/scev-12.c | 2 +- gcc/testsuite/gcc.dg/tree-ssa/scev-8.c | 2 +- gcc/testsuite/gcc.dg/tree-ssa/scev-9.c | 2 +- gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-86.c | 20 + gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-87.c | 13 + gcc/testsuite/gcc.dg/ucnid-16-utf8.c | 1 + gcc/testsuite/gcc.dg/vect/bb-slp-19.c | 1 - gcc/testsuite/gcc.dg/vect/bb-slp-over-widen-2.c | 2 +- gcc/testsuite/gcc.dg/vect/pr93843-1.c | 21 + gcc/testsuite/gcc.dg/vect/pr93843-2.c | 11 + gcc/testsuite/gcc.dg/vect/slp-perm-12.c | 2 +- gcc/testsuite/gcc.dg/vect/vect-over-widen-17.c | 5 +- gcc/testsuite/gcc.dg/vla-init-1.c | 2 - gcc/testsuite/gcc.misc-tests/gcov-pr94029.c | 14 + gcc/testsuite/gcc.misc-tests/help.exp | 2 +- .../aarch64/advsimd-intrinsics/bf16_dup.c | 85 + .../aarch64/advsimd-intrinsics/bf16_reinterpret.c | 466 + .../aarch64/advsimd-intrinsics/bf16_vldn.c | 150 + .../aarch64/advsimd-intrinsics/bf16_vstn.c | 107 + .../aarch64/advsimd-intrinsics/bfcvt-compile.c | 48 + .../aarch64/advsimd-intrinsics/bfcvt-nobf16.c | 10 + .../aarch64/advsimd-intrinsics/bfcvt-nosimd.c | 17 + .../aarch64/advsimd-intrinsics/bfcvtn-nobf16.c | 10 + .../aarch64/advsimd-intrinsics/bfcvtnq2-untied.c | 20 + .../gcc.target/aarch64/fmla_intrinsic_1.c | 6 +- .../gcc.target/aarch64/fmls_intrinsic_1.c | 6 +- gcc/testsuite/gcc.target/aarch64/mla_intrinsic_1.c | 4 +- gcc/testsuite/gcc.target/aarch64/mls_intrinsic_1.c | 4 +- gcc/testsuite/gcc.target/aarch64/pr94072.c | 9 + gcc/testsuite/gcc.target/aarch64/pr94201.c | 13 + .../aarch64/sve/acle/general-c/sizeless-1.c | 3 +- .../aarch64/sve/acle/general-c/sizeless-2.c | 3 +- .../gcc.target/aarch64/sve/acle/general/cpy_1.c | 4 + gcc/testsuite/gcc.target/aarch64/sve/pcs/args_1.c | 6 + .../gcc.target/aarch64/sve/pcs/saves_1_be_nowrap.c | 78 +- .../gcc.target/aarch64/sve/pcs/saves_1_be_wrap.c | 78 +- .../gcc.target/aarch64/sve/pcs/saves_1_le_nowrap.c | 78 +- .../gcc.target/aarch64/sve/pcs/saves_1_le_wrap.c | 78 +- .../gcc.target/aarch64/sve/pcs/saves_2_be_nowrap.c | 304 +- .../gcc.target/aarch64/sve/pcs/saves_2_be_wrap.c | 304 +- .../gcc.target/aarch64/sve/pcs/saves_2_le_nowrap.c | 304 +- .../gcc.target/aarch64/sve/pcs/saves_2_le_wrap.c | 304 +- .../gcc.target/aarch64/sve/pcs/saves_4_be.c | 78 +- .../gcc.target/aarch64/sve/pcs/saves_4_le.c | 78 +- .../gcc.target/aarch64/sve/pcs/saves_5_be.c | 76 +- .../gcc.target/aarch64/sve/pcs/saves_5_le.c | 76 +- .../gcc.target/aarch64/sve/pcs/stack_clash_1.c | 81 +- .../aarch64/sve/pcs/stack_clash_1_1024.c | 82 +- .../gcc.target/aarch64/sve/pcs/stack_clash_1_128.c | 78 +- .../aarch64/sve/pcs/stack_clash_1_2048.c | 80 +- .../gcc.target/aarch64/sve/pcs/stack_clash_1_256.c | 82 +- .../gcc.target/aarch64/sve/pcs/stack_clash_1_512.c | 82 +- .../aarch64/sve/pcs/stack_clash_2_1024.c | 66 +- .../aarch64/sve/pcs/stack_clash_2_2048.c | 66 +- .../gcc.target/aarch64/sve/pcs/stack_clash_2_256.c | 66 +- .../gcc.target/aarch64/sve/pcs/stack_clash_2_512.c | 66 +- gcc/testsuite/gcc.target/aarch64/vect-mull.x | 1 + gcc/testsuite/gcc.target/arc/tumaddsidi4.c | 4 +- gcc/testsuite/gcc.target/arm/bf16_dup.c | 96 + gcc/testsuite/gcc.target/arm/bf16_reinterpret.c | 435 + gcc/testsuite/gcc.target/arm/fuse-caller-save.c | 2 +- gcc/testsuite/gcc.target/arm/multilib.exp | 3 + .../gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c | 15 + .../gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c | 14 + .../gcc.target/arm/mve/intrinsics/mve_fpu1.c | 15 + .../gcc.target/arm/mve/intrinsics/mve_fpu2.c | 15 + .../gcc.target/arm/mve/intrinsics/mve_fpu3.c | 13 + .../gcc.target/arm/mve/intrinsics/mve_libcall1.c | 68 + .../gcc.target/arm/mve/intrinsics/mve_libcall2.c | 68 + .../arm/mve/intrinsics/mve_move_gpr_to_gpr.c | 18 + .../arm/mve/intrinsics/mve_vector_float.c | 28 + .../arm/mve/intrinsics/mve_vector_float1.c | 32 + .../arm/mve/intrinsics/mve_vector_float2.c | 28 + .../gcc.target/arm/mve/intrinsics/mve_vector_int.c | 50 + .../arm/mve/intrinsics/mve_vector_int1.c | 55 + .../arm/mve/intrinsics/mve_vector_int2.c | 50 + .../arm/mve/intrinsics/mve_vector_uint.c | 50 + .../arm/mve/intrinsics/mve_vector_uint1.c | 55 + .../arm/mve/intrinsics/mve_vector_uint2.c | 50 + .../gcc.target/arm/mve/intrinsics/vabavq_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_p_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_p_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vabdq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabdq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vabdq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vabdq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vabdq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vabdq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vabdq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vabdq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vabdq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vabdq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vabdq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabdq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vabdq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vabdq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabdq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vabdq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vabdq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vabdq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vabsq_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vabsq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabsq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vabsq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vabsq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vadciq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vadciq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vadciq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vadciq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vadcq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vadcq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vadcq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vadcq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddlvq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddlvq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_x_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddvaq_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvaq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvaq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvaq_p_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvaq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvaq_p_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvaq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvaq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvaq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvaq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvaq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvaq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvq_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvq_p_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvq_p_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vandq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vandq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vandq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vandq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vandq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vandq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vandq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vandq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vandq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vandq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vandq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vandq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vandq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vandq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vandq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vandq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vandq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vandq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vandq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vandq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vandq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vandq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vandq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vandq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vbicq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vbicq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vbicq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vbicq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vbicq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vbicq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vbicq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vbicq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vbicq_n_s16.c | 14 + .../gcc.target/arm/mve/intrinsics/vbicq_n_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vbicq_n_u16.c | 14 + .../gcc.target/arm/mve/intrinsics/vbicq_n_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vbicq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vbicq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vbicq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vbicq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vbicq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vbicq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vbicq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vbrsrq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vbrsrq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vbrsrq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vbrsrq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vbrsrq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vbrsrq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vbrsrq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c | 24 + .../arm/mve/intrinsics/vcaddq_rot270_f16.c | 22 + .../arm/mve/intrinsics/vcaddq_rot270_f32.c | 22 + .../arm/mve/intrinsics/vcaddq_rot270_m_f16.c | 24 + .../arm/mve/intrinsics/vcaddq_rot270_m_f32.c | 24 + .../arm/mve/intrinsics/vcaddq_rot270_m_s16.c | 24 + .../arm/mve/intrinsics/vcaddq_rot270_m_s32.c | 24 + .../arm/mve/intrinsics/vcaddq_rot270_m_s8.c | 24 + .../arm/mve/intrinsics/vcaddq_rot270_m_u16.c | 24 + .../arm/mve/intrinsics/vcaddq_rot270_m_u32.c | 24 + .../arm/mve/intrinsics/vcaddq_rot270_m_u8.c | 24 + .../arm/mve/intrinsics/vcaddq_rot270_s16.c | 22 + .../arm/mve/intrinsics/vcaddq_rot270_s32.c | 22 + .../arm/mve/intrinsics/vcaddq_rot270_s8.c | 22 + .../arm/mve/intrinsics/vcaddq_rot270_u16.c | 22 + .../arm/mve/intrinsics/vcaddq_rot270_u32.c | 22 + .../arm/mve/intrinsics/vcaddq_rot270_u8.c | 22 + .../arm/mve/intrinsics/vcaddq_rot270_x_f16.c | 23 + .../arm/mve/intrinsics/vcaddq_rot270_x_f32.c | 23 + .../arm/mve/intrinsics/vcaddq_rot270_x_s16.c | 23 + .../arm/mve/intrinsics/vcaddq_rot270_x_s32.c | 23 + .../arm/mve/intrinsics/vcaddq_rot270_x_s8.c | 23 + .../arm/mve/intrinsics/vcaddq_rot270_x_u16.c | 23 + .../arm/mve/intrinsics/vcaddq_rot270_x_u32.c | 23 + .../arm/mve/intrinsics/vcaddq_rot270_x_u8.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_f16.c | 22 + .../arm/mve/intrinsics/vcaddq_rot90_f32.c | 22 + .../arm/mve/intrinsics/vcaddq_rot90_m_f16.c | 24 + .../arm/mve/intrinsics/vcaddq_rot90_m_f32.c | 24 + .../arm/mve/intrinsics/vcaddq_rot90_m_s16.c | 24 + .../arm/mve/intrinsics/vcaddq_rot90_m_s32.c | 24 + .../arm/mve/intrinsics/vcaddq_rot90_m_s8.c | 24 + .../arm/mve/intrinsics/vcaddq_rot90_m_u16.c | 24 + .../arm/mve/intrinsics/vcaddq_rot90_m_u32.c | 24 + .../arm/mve/intrinsics/vcaddq_rot90_m_u8.c | 24 + .../arm/mve/intrinsics/vcaddq_rot90_s16.c | 22 + .../arm/mve/intrinsics/vcaddq_rot90_s32.c | 22 + .../arm/mve/intrinsics/vcaddq_rot90_s8.c | 22 + .../arm/mve/intrinsics/vcaddq_rot90_u16.c | 22 + .../arm/mve/intrinsics/vcaddq_rot90_u32.c | 22 + .../arm/mve/intrinsics/vcaddq_rot90_u8.c | 22 + .../arm/mve/intrinsics/vcaddq_rot90_x_f16.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_x_f32.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_x_s16.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_x_s32.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_x_s8.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_x_u16.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_x_u32.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vclsq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vclsq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vclsq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vclsq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vclsq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vclsq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vclsq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vclsq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vclsq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vclzq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vclzq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vclzq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vclzq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vclzq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vclzq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vclzq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vclzq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vclzq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vclzq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vclzq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vclzq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vclzq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vclzq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vclzq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vclzq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vclzq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vclzq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmlaq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmlaq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmlaq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vcmlaq_m_f32.c | 24 + .../arm/mve/intrinsics/vcmlaq_rot180_f16.c | 22 + .../arm/mve/intrinsics/vcmlaq_rot180_f32.c | 22 + .../arm/mve/intrinsics/vcmlaq_rot180_m_f16.c | 24 + .../arm/mve/intrinsics/vcmlaq_rot180_m_f32.c | 24 + .../arm/mve/intrinsics/vcmlaq_rot270_f16.c | 22 + .../arm/mve/intrinsics/vcmlaq_rot270_f32.c | 22 + .../arm/mve/intrinsics/vcmlaq_rot270_m_f16.c | 24 + .../arm/mve/intrinsics/vcmlaq_rot270_m_f32.c | 24 + .../arm/mve/intrinsics/vcmlaq_rot90_f16.c | 22 + .../arm/mve/intrinsics/vcmlaq_rot90_f32.c | 22 + .../arm/mve/intrinsics/vcmlaq_rot90_m_f16.c | 24 + .../arm/mve/intrinsics/vcmlaq_rot90_m_f32.c | 24 + .../arm/mve/intrinsics/vcmpcsq_m_n_u16.c | 23 + .../arm/mve/intrinsics/vcmpcsq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c | 23 + .../arm/mve/intrinsics/vcmpeqq_m_n_f16.c | 23 + .../arm/mve/intrinsics/vcmpeqq_m_n_f32.c | 23 + .../arm/mve/intrinsics/vcmpeqq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vcmpeqq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c | 23 + .../arm/mve/intrinsics/vcmpeqq_m_n_u16.c | 23 + .../arm/mve/intrinsics/vcmpeqq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c | 23 + .../arm/mve/intrinsics/vcmpgeq_m_n_f16.c | 23 + .../arm/mve/intrinsics/vcmpgeq_m_n_f32.c | 23 + .../arm/mve/intrinsics/vcmpgeq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vcmpgeq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c | 23 + .../arm/mve/intrinsics/vcmpgtq_m_n_f16.c | 23 + .../arm/mve/intrinsics/vcmpgtq_m_n_f32.c | 23 + .../arm/mve/intrinsics/vcmpgtq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vcmpgtq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_s8.c | 22 + .../arm/mve/intrinsics/vcmphiq_m_n_u16.c | 23 + .../arm/mve/intrinsics/vcmphiq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmphiq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmphiq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmphiq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpleq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpleq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c | 23 + .../arm/mve/intrinsics/vcmpleq_m_n_f16.c | 23 + .../arm/mve/intrinsics/vcmpleq_m_n_f32.c | 23 + .../arm/mve/intrinsics/vcmpleq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vcmpleq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpleq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpleq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpleq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpleq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpleq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpleq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpltq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpltq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c | 23 + .../arm/mve/intrinsics/vcmpltq_m_n_f16.c | 23 + .../arm/mve/intrinsics/vcmpltq_m_n_f32.c | 23 + .../arm/mve/intrinsics/vcmpltq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vcmpltq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpltq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpltq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpltq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpltq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpltq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpltq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c | 23 + .../arm/mve/intrinsics/vcmpneq_m_n_f16.c | 23 + .../arm/mve/intrinsics/vcmpneq_m_n_f32.c | 23 + .../arm/mve/intrinsics/vcmpneq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vcmpneq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c | 23 + .../arm/mve/intrinsics/vcmpneq_m_n_u16.c | 23 + .../arm/mve/intrinsics/vcmpneq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmulq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmulq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c | 24 + .../arm/mve/intrinsics/vcmulq_rot180_f16.c | 22 + .../arm/mve/intrinsics/vcmulq_rot180_f32.c | 22 + .../arm/mve/intrinsics/vcmulq_rot180_m_f16.c | 24 + .../arm/mve/intrinsics/vcmulq_rot180_m_f32.c | 24 + .../arm/mve/intrinsics/vcmulq_rot180_x_f16.c | 23 + .../arm/mve/intrinsics/vcmulq_rot180_x_f32.c | 23 + .../arm/mve/intrinsics/vcmulq_rot270_f16.c | 22 + .../arm/mve/intrinsics/vcmulq_rot270_f32.c | 22 + .../arm/mve/intrinsics/vcmulq_rot270_m_f16.c | 24 + .../arm/mve/intrinsics/vcmulq_rot270_m_f32.c | 24 + .../arm/mve/intrinsics/vcmulq_rot270_x_f16.c | 23 + .../arm/mve/intrinsics/vcmulq_rot270_x_f32.c | 23 + .../arm/mve/intrinsics/vcmulq_rot90_f16.c | 22 + .../arm/mve/intrinsics/vcmulq_rot90_f32.c | 22 + .../arm/mve/intrinsics/vcmulq_rot90_m_f16.c | 24 + .../arm/mve/intrinsics/vcmulq_rot90_m_f32.c | 24 + .../arm/mve/intrinsics/vcmulq_rot90_x_f16.c | 24 + .../arm/mve/intrinsics/vcmulq_rot90_x_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcreateq_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcreateq_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcreateq_s16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcreateq_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcreateq_s64.c | 14 + .../gcc.target/arm/mve/intrinsics/vcreateq_s8.c | 14 + .../gcc.target/arm/mve/intrinsics/vcreateq_u16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcreateq_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcreateq_u64.c | 14 + .../gcc.target/arm/mve/intrinsics/vcreateq_u8.c | 14 + .../gcc.target/arm/mve/intrinsics/vctp16q.c | 22 + .../gcc.target/arm/mve/intrinsics/vctp16q_m.c | 23 + .../gcc.target/arm/mve/intrinsics/vctp32q.c | 22 + .../gcc.target/arm/mve/intrinsics/vctp32q_m.c | 23 + .../gcc.target/arm/mve/intrinsics/vctp64q.c | 22 + .../gcc.target/arm/mve/intrinsics/vctp64q_m.c | 23 + .../gcc.target/arm/mve/intrinsics/vctp8q.c | 22 + .../gcc.target/arm/mve/intrinsics/vctp8q_m.c | 23 + .../arm/mve/intrinsics/vcvtaq_m_s16_f16.c | 23 + .../arm/mve/intrinsics/vcvtaq_m_s32_f32.c | 23 + .../arm/mve/intrinsics/vcvtaq_m_u16_f16.c | 23 + .../arm/mve/intrinsics/vcvtaq_m_u32_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c | 14 + .../arm/mve/intrinsics/vcvtaq_x_s16_f16.c | 15 + .../arm/mve/intrinsics/vcvtaq_x_s32_f32.c | 15 + .../arm/mve/intrinsics/vcvtaq_x_u16_f16.c | 15 + .../arm/mve/intrinsics/vcvtaq_x_u32_f32.c | 15 + .../gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c | 14 + .../arm/mve/intrinsics/vcvtbq_m_f16_f32.c | 23 + .../arm/mve/intrinsics/vcvtbq_m_f32_f16.c | 23 + .../arm/mve/intrinsics/vcvtbq_x_f32_f16.c | 15 + .../arm/mve/intrinsics/vcvtmq_m_s16_f16.c | 23 + .../arm/mve/intrinsics/vcvtmq_m_s32_f32.c | 23 + .../arm/mve/intrinsics/vcvtmq_m_u16_f16.c | 23 + .../arm/mve/intrinsics/vcvtmq_m_u32_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c | 14 + .../arm/mve/intrinsics/vcvtmq_x_s16_f16.c | 15 + .../arm/mve/intrinsics/vcvtmq_x_s32_f32.c | 15 + .../arm/mve/intrinsics/vcvtmq_x_u16_f16.c | 15 + .../arm/mve/intrinsics/vcvtmq_x_u32_f32.c | 15 + .../arm/mve/intrinsics/vcvtnq_m_s16_f16.c | 23 + .../arm/mve/intrinsics/vcvtnq_m_s32_f32.c | 23 + .../arm/mve/intrinsics/vcvtnq_m_u16_f16.c | 23 + .../arm/mve/intrinsics/vcvtnq_m_u32_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c | 14 + .../arm/mve/intrinsics/vcvtnq_x_s16_f16.c | 15 + .../arm/mve/intrinsics/vcvtnq_x_s32_f32.c | 15 + .../arm/mve/intrinsics/vcvtnq_x_u16_f16.c | 15 + .../arm/mve/intrinsics/vcvtnq_x_u32_f32.c | 15 + .../arm/mve/intrinsics/vcvtpq_m_s16_f16.c | 23 + .../arm/mve/intrinsics/vcvtpq_m_s32_f32.c | 23 + .../arm/mve/intrinsics/vcvtpq_m_u16_f16.c | 23 + .../arm/mve/intrinsics/vcvtpq_m_u32_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c | 14 + .../arm/mve/intrinsics/vcvtpq_x_s16_f16.c | 15 + .../arm/mve/intrinsics/vcvtpq_x_s32_f32.c | 15 + .../arm/mve/intrinsics/vcvtpq_x_u16_f16.c | 15 + .../arm/mve/intrinsics/vcvtpq_x_u32_f32.c | 15 + .../gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c | 14 + .../arm/mve/intrinsics/vcvtq_m_f16_s16.c | 23 + .../arm/mve/intrinsics/vcvtq_m_f16_u16.c | 23 + .../arm/mve/intrinsics/vcvtq_m_f32_s32.c | 23 + .../arm/mve/intrinsics/vcvtq_m_f32_u32.c | 23 + .../arm/mve/intrinsics/vcvtq_m_n_f16_s16.c | 24 + .../arm/mve/intrinsics/vcvtq_m_n_f16_u16.c | 24 + .../arm/mve/intrinsics/vcvtq_m_n_f32_s32.c | 24 + .../arm/mve/intrinsics/vcvtq_m_n_f32_u32.c | 24 + .../arm/mve/intrinsics/vcvtq_m_n_s16_f16.c | 24 + .../arm/mve/intrinsics/vcvtq_m_n_s32_f32.c | 24 + .../arm/mve/intrinsics/vcvtq_m_n_u16_f16.c | 24 + .../arm/mve/intrinsics/vcvtq_m_n_u32_f32.c | 24 + .../arm/mve/intrinsics/vcvtq_m_s16_f16.c | 23 + .../arm/mve/intrinsics/vcvtq_m_s32_f32.c | 23 + .../arm/mve/intrinsics/vcvtq_m_u16_f16.c | 23 + .../arm/mve/intrinsics/vcvtq_m_u32_f32.c | 23 + .../arm/mve/intrinsics/vcvtq_n_f16_s16.c | 22 + .../arm/mve/intrinsics/vcvtq_n_f16_u16.c | 22 + .../arm/mve/intrinsics/vcvtq_n_f32_s32.c | 22 + .../arm/mve/intrinsics/vcvtq_n_f32_u32.c | 22 + .../arm/mve/intrinsics/vcvtq_n_s16_f16.c | 14 + .../arm/mve/intrinsics/vcvtq_n_s32_f32.c | 14 + .../arm/mve/intrinsics/vcvtq_n_u16_f16.c | 14 + .../arm/mve/intrinsics/vcvtq_n_u32_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtq_s16_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtq_s32_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtq_u16_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtq_u32_f32.c | 14 + .../arm/mve/intrinsics/vcvtq_x_f16_s16.c | 24 + .../arm/mve/intrinsics/vcvtq_x_f16_u16.c | 24 + .../arm/mve/intrinsics/vcvtq_x_f32_s32.c | 24 + .../arm/mve/intrinsics/vcvtq_x_f32_u32.c | 24 + .../arm/mve/intrinsics/vcvtq_x_n_f16_s16.c | 24 + .../arm/mve/intrinsics/vcvtq_x_n_f16_u16.c | 24 + .../arm/mve/intrinsics/vcvtq_x_n_f32_s32.c | 24 + .../arm/mve/intrinsics/vcvtq_x_n_f32_u32.c | 24 + .../arm/mve/intrinsics/vcvtq_x_n_s16_f16.c | 15 + .../arm/mve/intrinsics/vcvtq_x_n_s32_f32.c | 15 + .../arm/mve/intrinsics/vcvtq_x_n_u16_f16.c | 15 + .../arm/mve/intrinsics/vcvtq_x_n_u32_f32.c | 15 + .../arm/mve/intrinsics/vcvtq_x_s16_f16.c | 15 + .../arm/mve/intrinsics/vcvtq_x_s32_f32.c | 15 + .../arm/mve/intrinsics/vcvtq_x_u16_f16.c | 15 + .../arm/mve/intrinsics/vcvtq_x_u32_f32.c | 15 + .../gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c | 14 + .../arm/mve/intrinsics/vcvttq_m_f16_f32.c | 23 + .../arm/mve/intrinsics/vcvttq_m_f32_f16.c | 23 + .../arm/mve/intrinsics/vcvttq_x_f32_f16.c | 15 + .../gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c | 24 + .../arm/mve/intrinsics/vddupq_m_wb_u16.c | 24 + .../arm/mve/intrinsics/vddupq_m_wb_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vddupq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vddupq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vddupq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c | 24 + .../arm/mve/intrinsics/vddupq_x_wb_u16.c | 26 + .../arm/mve/intrinsics/vddupq_x_wb_u32.c | 26 + .../gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c | 26 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vdupq_n_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vdupq_n_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vdupq_n_s16.c | 14 + .../gcc.target/arm/mve/intrinsics/vdupq_n_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vdupq_n_s8.c | 14 + .../gcc.target/arm/mve/intrinsics/vdupq_n_u16.c | 14 + .../gcc.target/arm/mve/intrinsics/vdupq_n_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vdupq_n_u8.c | 14 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c | 15 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c | 15 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c | 15 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c | 15 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c | 15 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c | 15 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c | 15 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c | 15 + .../arm/mve/intrinsics/vdwdupq_m_n_u16.c | 24 + .../arm/mve/intrinsics/vdwdupq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c | 24 + .../arm/mve/intrinsics/vdwdupq_m_wb_u16.c | 24 + .../arm/mve/intrinsics/vdwdupq_m_wb_u32.c | 24 + .../arm/mve/intrinsics/vdwdupq_m_wb_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c | 22 + .../arm/mve/intrinsics/vdwdupq_x_n_u16.c | 24 + .../arm/mve/intrinsics/vdwdupq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c | 24 + .../arm/mve/intrinsics/vdwdupq_x_wb_u16.c | 24 + .../arm/mve/intrinsics/vdwdupq_x_wb_u32.c | 24 + .../arm/mve/intrinsics/vdwdupq_x_wb_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/veorq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/veorq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/veorq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/veorq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/veorq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/veorq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/veorq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/veorq_x_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_x_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_x_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_x_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_x_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_x_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_x_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_x_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmaq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmaq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmsq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmsq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot270_m_s16.c | 24 + .../arm/mve/intrinsics/vhcaddq_rot270_m_s32.c | 24 + .../arm/mve/intrinsics/vhcaddq_rot270_m_s8.c | 24 + .../arm/mve/intrinsics/vhcaddq_rot270_s16.c | 22 + .../arm/mve/intrinsics/vhcaddq_rot270_s32.c | 22 + .../arm/mve/intrinsics/vhcaddq_rot270_s8.c | 22 + .../arm/mve/intrinsics/vhcaddq_rot270_x_s16.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot270_x_s32.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot270_x_s8.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot90_m_s16.c | 24 + .../arm/mve/intrinsics/vhcaddq_rot90_m_s32.c | 24 + .../arm/mve/intrinsics/vhcaddq_rot90_m_s8.c | 24 + .../arm/mve/intrinsics/vhcaddq_rot90_s16.c | 22 + .../arm/mve/intrinsics/vhcaddq_rot90_s32.c | 22 + .../arm/mve/intrinsics/vhcaddq_rot90_s8.c | 22 + .../arm/mve/intrinsics/vhcaddq_rot90_x_s16.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot90_x_s32.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot90_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c | 24 + .../arm/mve/intrinsics/vidupq_m_wb_u16.c | 24 + .../arm/mve/intrinsics/vidupq_m_wb_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vidupq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vidupq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vidupq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c | 24 + .../arm/mve/intrinsics/vidupq_x_wb_u16.c | 26 + .../arm/mve/intrinsics/vidupq_x_wb_u32.c | 26 + .../gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c | 26 + .../arm/mve/intrinsics/viwdupq_m_n_u16.c | 24 + .../arm/mve/intrinsics/viwdupq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c | 24 + .../arm/mve/intrinsics/viwdupq_m_wb_u16.c | 24 + .../arm/mve/intrinsics/viwdupq_m_wb_u32.c | 24 + .../arm/mve/intrinsics/viwdupq_m_wb_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c | 22 + .../arm/mve/intrinsics/viwdupq_x_n_u16.c | 24 + .../arm/mve/intrinsics/viwdupq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c | 24 + .../arm/mve/intrinsics/viwdupq_x_wb_u16.c | 24 + .../arm/mve/intrinsics/viwdupq_x_wb_u32.c | 24 + .../arm/mve/intrinsics/viwdupq_x_wb_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vld1q_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_z_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_z_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_z_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_z_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_z_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_z_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_z_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_z_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vld2q_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vld4q_f16.c | 25 + .../gcc.target/arm/mve/intrinsics/vld4q_f32.c | 25 + .../gcc.target/arm/mve/intrinsics/vld4q_s16.c | 25 + .../gcc.target/arm/mve/intrinsics/vld4q_s32.c | 25 + .../gcc.target/arm/mve/intrinsics/vld4q_s8.c | 25 + .../gcc.target/arm/mve/intrinsics/vld4q_u16.c | 25 + .../gcc.target/arm/mve/intrinsics/vld4q_u32.c | 25 + .../gcc.target/arm/mve/intrinsics/vld4q_u8.c | 25 + .../arm/mve/intrinsics/vldrbq_gather_offset_s16.c | 22 + .../arm/mve/intrinsics/vldrbq_gather_offset_s32.c | 22 + .../arm/mve/intrinsics/vldrbq_gather_offset_s8.c | 22 + .../arm/mve/intrinsics/vldrbq_gather_offset_u16.c | 22 + .../arm/mve/intrinsics/vldrbq_gather_offset_u32.c | 22 + .../arm/mve/intrinsics/vldrbq_gather_offset_u8.c | 22 + .../mve/intrinsics/vldrbq_gather_offset_z_s16.c | 22 + .../mve/intrinsics/vldrbq_gather_offset_z_s32.c | 22 + .../arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c | 22 + .../mve/intrinsics/vldrbq_gather_offset_z_u16.c | 22 + .../mve/intrinsics/vldrbq_gather_offset_z_u32.c | 22 + .../arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vldrbq_s16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_s8.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_u16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_u8.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c | 14 + .../arm/mve/intrinsics/vldrdq_gather_base_s64.c | 14 + .../arm/mve/intrinsics/vldrdq_gather_base_u64.c | 14 + .../arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c | 14 + .../arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c | 14 + .../mve/intrinsics/vldrdq_gather_base_wb_z_s64.c | 12 + .../mve/intrinsics/vldrdq_gather_base_wb_z_u64.c | 12 + .../arm/mve/intrinsics/vldrdq_gather_base_z_s64.c | 14 + .../arm/mve/intrinsics/vldrdq_gather_base_z_u64.c | 14 + .../arm/mve/intrinsics/vldrdq_gather_offset_s64.c | 22 + .../arm/mve/intrinsics/vldrdq_gather_offset_u64.c | 22 + .../mve/intrinsics/vldrdq_gather_offset_z_s64.c | 22 + .../mve/intrinsics/vldrdq_gather_offset_z_u64.c | 22 + .../intrinsics/vldrdq_gather_shifted_offset_s64.c | 22 + .../intrinsics/vldrdq_gather_shifted_offset_u64.c | 22 + .../vldrdq_gather_shifted_offset_z_s64.c | 22 + .../vldrdq_gather_shifted_offset_z_u64.c | 22 + .../gcc.target/arm/mve/intrinsics/vldrhq_f16.c | 14 + .../arm/mve/intrinsics/vldrhq_gather_offset_f16.c | 22 + .../arm/mve/intrinsics/vldrhq_gather_offset_s16.c | 22 + .../arm/mve/intrinsics/vldrhq_gather_offset_s32.c | 22 + .../arm/mve/intrinsics/vldrhq_gather_offset_u16.c | 22 + .../arm/mve/intrinsics/vldrhq_gather_offset_u32.c | 22 + .../mve/intrinsics/vldrhq_gather_offset_z_f16.c | 22 + .../mve/intrinsics/vldrhq_gather_offset_z_s16.c | 22 + .../mve/intrinsics/vldrhq_gather_offset_z_s32.c | 22 + .../mve/intrinsics/vldrhq_gather_offset_z_u16.c | 22 + .../mve/intrinsics/vldrhq_gather_offset_z_u32.c | 22 + .../intrinsics/vldrhq_gather_shifted_offset_f16.c | 22 + .../intrinsics/vldrhq_gather_shifted_offset_s16.c | 22 + .../intrinsics/vldrhq_gather_shifted_offset_s32.c | 22 + .../intrinsics/vldrhq_gather_shifted_offset_u16.c | 22 + .../intrinsics/vldrhq_gather_shifted_offset_u32.c | 22 + .../vldrhq_gather_shifted_offset_z_f16.c | 22 + .../vldrhq_gather_shifted_offset_z_s16.c | 22 + .../vldrhq_gather_shifted_offset_z_s32.c | 22 + .../vldrhq_gather_shifted_offset_z_u16.c | 22 + .../vldrhq_gather_shifted_offset_z_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vldrhq_s16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrhq_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrhq_u16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrhq_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrwq_f32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_base_f32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_base_s32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_base_u32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c | 14 + .../mve/intrinsics/vldrwq_gather_base_wb_z_f32.c | 14 + .../mve/intrinsics/vldrwq_gather_base_wb_z_s32.c | 14 + .../mve/intrinsics/vldrwq_gather_base_wb_z_u32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_base_z_f32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_base_z_s32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_base_z_u32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_offset_f32.c | 22 + .../arm/mve/intrinsics/vldrwq_gather_offset_s32.c | 22 + .../arm/mve/intrinsics/vldrwq_gather_offset_u32.c | 22 + .../mve/intrinsics/vldrwq_gather_offset_z_f32.c | 22 + .../mve/intrinsics/vldrwq_gather_offset_z_s32.c | 22 + .../mve/intrinsics/vldrwq_gather_offset_z_u32.c | 22 + .../intrinsics/vldrwq_gather_shifted_offset_f32.c | 22 + .../intrinsics/vldrwq_gather_shifted_offset_s32.c | 22 + .../intrinsics/vldrwq_gather_shifted_offset_u32.c | 22 + .../vldrwq_gather_shifted_offset_z_f32.c | 22 + .../vldrwq_gather_shifted_offset_z_s32.c | 22 + .../vldrwq_gather_shifted_offset_z_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vldrwq_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrwq_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxaq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxaq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxaq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxavq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxavq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxavq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c | 22 + .../arm/mve/intrinsics/vmaxnmavq_p_f16.c | 22 + .../arm/mve/intrinsics/vmaxnmavq_p_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmaxq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vminaq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vminaq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vminaq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vminaq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminaq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminaq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vminavq_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminavq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminavq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vminavq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminavq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminavq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmaq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmaq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vminnmavq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmavq_f32.c | 22 + .../arm/mve/intrinsics/vminnmavq_p_f16.c | 22 + .../arm/mve/intrinsics/vminnmavq_p_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vminnmvq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmvq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vminq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vminq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vminq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vminq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vminq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vminq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vminq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vminq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vminq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vminq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vminq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vminq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vminq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vminvq_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_p_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_p_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_u8.c | 22 + .../arm/mve/intrinsics/vmladavaq_p_s16.c | 23 + .../arm/mve/intrinsics/vmladavaq_p_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c | 23 + .../arm/mve/intrinsics/vmladavaq_p_u16.c | 23 + .../arm/mve/intrinsics/vmladavaq_p_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmladavaq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavaq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavaq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavaq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavaq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavaq_u8.c | 22 + .../arm/mve/intrinsics/vmladavaxq_p_s16.c | 23 + .../arm/mve/intrinsics/vmladavaxq_p_s32.c | 23 + .../arm/mve/intrinsics/vmladavaxq_p_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmladavaxq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavaxq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavaxq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavq_u8.c | 22 + .../arm/mve/intrinsics/vmladavxq_p_s16.c | 22 + .../arm/mve/intrinsics/vmladavxq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavxq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavxq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavxq_s8.c | 22 + .../arm/mve/intrinsics/vmlaldavaq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlaldavaq_p_s32.c | 22 + .../arm/mve/intrinsics/vmlaldavaq_p_u16.c | 22 + .../arm/mve/intrinsics/vmlaldavaq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c | 22 + .../arm/mve/intrinsics/vmlaldavaxq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlaldavaxq_p_s32.c | 22 + .../arm/mve/intrinsics/vmlaldavaxq_p_u16.c | 22 + .../arm/mve/intrinsics/vmlaldavaxq_p_u32.c | 22 + .../arm/mve/intrinsics/vmlaldavaxq_s16.c | 22 + .../arm/mve/intrinsics/vmlaldavaxq_s32.c | 22 + .../arm/mve/intrinsics/vmlaldavq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlaldavq_p_s32.c | 22 + .../arm/mve/intrinsics/vmlaldavq_p_u16.c | 22 + .../arm/mve/intrinsics/vmlaldavq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c | 22 + .../arm/mve/intrinsics/vmlaldavxq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlaldavxq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c | 22 + .../arm/mve/intrinsics/vmlsdavaq_p_s16.c | 23 + .../arm/mve/intrinsics/vmlsdavaq_p_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c | 22 + .../arm/mve/intrinsics/vmlsdavaxq_p_s16.c | 23 + .../arm/mve/intrinsics/vmlsdavaxq_p_s32.c | 23 + .../arm/mve/intrinsics/vmlsdavaxq_p_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavq_s8.c | 22 + .../arm/mve/intrinsics/vmlsdavxq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlsdavxq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavxq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavxq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavxq_s8.c | 22 + .../arm/mve/intrinsics/vmlsldavaq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlsldavaq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c | 22 + .../arm/mve/intrinsics/vmlsldavaxq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlsldavaxq_p_s32.c | 22 + .../arm/mve/intrinsics/vmlsldavaxq_s16.c | 22 + .../arm/mve/intrinsics/vmlsldavaxq_s32.c | 22 + .../arm/mve/intrinsics/vmlsldavq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlsldavq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c | 22 + .../arm/mve/intrinsics/vmlsldavxq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlsldavxq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovlbq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovlbq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovlbq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovlbq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovltq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovltq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovltq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovltq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovltq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovnbq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovnbq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovnbq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovnbq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovntq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovntq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovntq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovntq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulhq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulhq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulhq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulhq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulhq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulhq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulhq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulhq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulhq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulhq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulhq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulhq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulhq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulhq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulhq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulhq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulhq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulhq_x_u8.c | 23 + .../arm/mve/intrinsics/vmullbq_int_m_s16.c | 24 + .../arm/mve/intrinsics/vmullbq_int_m_s32.c | 24 + .../arm/mve/intrinsics/vmullbq_int_m_s8.c | 24 + .../arm/mve/intrinsics/vmullbq_int_m_u16.c | 24 + .../arm/mve/intrinsics/vmullbq_int_m_u32.c | 24 + .../arm/mve/intrinsics/vmullbq_int_m_u8.c | 24 + .../arm/mve/intrinsics/vmullbq_int_s16.c | 22 + .../arm/mve/intrinsics/vmullbq_int_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmullbq_int_s8.c | 22 + .../arm/mve/intrinsics/vmullbq_int_u16.c | 22 + .../arm/mve/intrinsics/vmullbq_int_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmullbq_int_u8.c | 22 + .../arm/mve/intrinsics/vmullbq_int_x_s16.c | 23 + .../arm/mve/intrinsics/vmullbq_int_x_s32.c | 23 + .../arm/mve/intrinsics/vmullbq_int_x_s8.c | 23 + .../arm/mve/intrinsics/vmullbq_int_x_u16.c | 23 + .../arm/mve/intrinsics/vmullbq_int_x_u32.c | 23 + .../arm/mve/intrinsics/vmullbq_int_x_u8.c | 23 + .../arm/mve/intrinsics/vmullbq_poly_m_p16.c | 24 + .../arm/mve/intrinsics/vmullbq_poly_m_p8.c | 24 + .../arm/mve/intrinsics/vmullbq_poly_p16.c | 22 + .../arm/mve/intrinsics/vmullbq_poly_p8.c | 22 + .../arm/mve/intrinsics/vmullbq_poly_x_p16.c | 23 + .../arm/mve/intrinsics/vmullbq_poly_x_p8.c | 23 + .../arm/mve/intrinsics/vmulltq_int_m_s16.c | 24 + .../arm/mve/intrinsics/vmulltq_int_m_s32.c | 24 + .../arm/mve/intrinsics/vmulltq_int_m_s8.c | 24 + .../arm/mve/intrinsics/vmulltq_int_m_u16.c | 24 + .../arm/mve/intrinsics/vmulltq_int_m_u32.c | 24 + .../arm/mve/intrinsics/vmulltq_int_m_u8.c | 24 + .../arm/mve/intrinsics/vmulltq_int_s16.c | 22 + .../arm/mve/intrinsics/vmulltq_int_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulltq_int_s8.c | 22 + .../arm/mve/intrinsics/vmulltq_int_u16.c | 22 + .../arm/mve/intrinsics/vmulltq_int_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulltq_int_u8.c | 22 + .../arm/mve/intrinsics/vmulltq_int_x_s16.c | 23 + .../arm/mve/intrinsics/vmulltq_int_x_s32.c | 23 + .../arm/mve/intrinsics/vmulltq_int_x_s8.c | 23 + .../arm/mve/intrinsics/vmulltq_int_x_u16.c | 23 + .../arm/mve/intrinsics/vmulltq_int_x_u32.c | 23 + .../arm/mve/intrinsics/vmulltq_int_x_u8.c | 23 + .../arm/mve/intrinsics/vmulltq_poly_m_p16.c | 24 + .../arm/mve/intrinsics/vmulltq_poly_m_p8.c | 24 + .../arm/mve/intrinsics/vmulltq_poly_p16.c | 22 + .../arm/mve/intrinsics/vmulltq_poly_p8.c | 22 + .../arm/mve/intrinsics/vmulltq_poly_x_p16.c | 23 + .../arm/mve/intrinsics/vmulltq_poly_x_p8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulq_x_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmvnq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmvnq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmvnq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmvnq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmvnq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmvnq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmvnq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmvnq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmvnq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmvnq_n_s16.c | 14 + .../gcc.target/arm/mve/intrinsics/vmvnq_n_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vmvnq_n_u16.c | 14 + .../gcc.target/arm/mve/intrinsics/vmvnq_n_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vmvnq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmvnq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmvnq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmvnq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmvnq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmvnq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c | 15 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c | 15 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c | 15 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c | 15 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vnegq_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vnegq_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vnegq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vnegq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vnegq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vnegq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vnegq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vnegq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vnegq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vnegq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vnegq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vnegq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vnegq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vnegq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vnegq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vornq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vornq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vornq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vornq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vornq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vornq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vornq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vornq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vornq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vornq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vornq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vornq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vornq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vornq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vornq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vornq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vorrq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vorrq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vorrq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vorrq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vorrq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vorrq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vorrq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vorrq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vorrq_n_s16.c | 14 + .../gcc.target/arm/mve/intrinsics/vorrq_n_s32.c | 14 + .../gcc.target/arm/mve/intrinsics/vorrq_n_u16.c | 14 + .../gcc.target/arm/mve/intrinsics/vorrq_n_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vorrq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vorrq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vorrq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vorrq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vorrq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vorrq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vorrq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vpnot.c | 22 + .../gcc.target/arm/mve/intrinsics/vpselq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vpselq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vpselq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vpselq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vpselq_s64.c | 22 + .../gcc.target/arm/mve/intrinsics/vpselq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vpselq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vpselq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vpselq_u64.c | 22 + .../gcc.target/arm/mve/intrinsics/vpselq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqabsq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vqabsq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqabsq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqabsq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqabsq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqabsq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqaddq_u8.c | 22 + .../arm/mve/intrinsics/vqdmladhq_m_s16.c | 24 + .../arm/mve/intrinsics/vqdmladhq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqdmladhq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqdmladhq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmladhq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmladhq_s8.c | 22 + .../arm/mve/intrinsics/vqdmladhxq_m_s16.c | 24 + .../arm/mve/intrinsics/vqdmladhxq_m_s32.c | 24 + .../arm/mve/intrinsics/vqdmladhxq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqdmladhxq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmladhxq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmladhxq_s8.c | 22 + .../arm/mve/intrinsics/vqdmlahq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqdmlahq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqdmlahq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmlahq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmlahq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmlahq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmlahq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmlahq_n_u8.c | 22 + .../arm/mve/intrinsics/vqdmlsdhq_m_s16.c | 24 + .../arm/mve/intrinsics/vqdmlsdhq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqdmlsdhq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmlsdhq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmlsdhq_s8.c | 22 + .../arm/mve/intrinsics/vqdmlsdhxq_m_s16.c | 24 + .../arm/mve/intrinsics/vqdmlsdhxq_m_s32.c | 24 + .../arm/mve/intrinsics/vqdmlsdhxq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s8.c | 22 + .../arm/mve/intrinsics/vqdmulhq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqdmulhq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqdmulhq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmulhq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmulhq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmulhq_s8.c | 22 + .../arm/mve/intrinsics/vqdmullbq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqdmullbq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqdmullbq_m_s16.c | 24 + .../arm/mve/intrinsics/vqdmullbq_m_s32.c | 24 + .../arm/mve/intrinsics/vqdmullbq_n_s16.c | 22 + .../arm/mve/intrinsics/vqdmullbq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmullbq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmullbq_s32.c | 22 + .../arm/mve/intrinsics/vqdmulltq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqdmulltq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqdmulltq_m_s16.c | 24 + .../arm/mve/intrinsics/vqdmulltq_m_s32.c | 24 + .../arm/mve/intrinsics/vqdmulltq_n_s16.c | 22 + .../arm/mve/intrinsics/vqdmulltq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmulltq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqdmulltq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovnbq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vqmovnbq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqmovnbq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vqmovnbq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovntq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vqmovntq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqmovntq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vqmovntq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqmovntq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovntq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovntq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovntq_u32.c | 22 + .../arm/mve/intrinsics/vqmovunbq_m_s16.c | 23 + .../arm/mve/intrinsics/vqmovunbq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c | 22 + .../arm/mve/intrinsics/vqmovuntq_m_s16.c | 23 + .../arm/mve/intrinsics/vqmovuntq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqnegq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vqnegq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqnegq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqnegq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqnegq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqnegq_s8.c | 22 + .../arm/mve/intrinsics/vqrdmladhq_m_s16.c | 24 + .../arm/mve/intrinsics/vqrdmladhq_m_s32.c | 24 + .../arm/mve/intrinsics/vqrdmladhq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c | 22 + .../arm/mve/intrinsics/vqrdmladhxq_m_s16.c | 24 + .../arm/mve/intrinsics/vqrdmladhxq_m_s32.c | 24 + .../arm/mve/intrinsics/vqrdmladhxq_m_s8.c | 24 + .../arm/mve/intrinsics/vqrdmladhxq_s16.c | 22 + .../arm/mve/intrinsics/vqrdmladhxq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c | 22 + .../arm/mve/intrinsics/vqrdmlahq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqrdmlahq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqrdmlahq_m_n_s8.c | 24 + .../arm/mve/intrinsics/vqrdmlahq_n_s16.c | 22 + .../arm/mve/intrinsics/vqrdmlahq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c | 22 + .../arm/mve/intrinsics/vqrdmlahq_n_u16.c | 22 + .../arm/mve/intrinsics/vqrdmlahq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u8.c | 22 + .../arm/mve/intrinsics/vqrdmlashq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqrdmlashq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqrdmlashq_m_n_s8.c | 24 + .../arm/mve/intrinsics/vqrdmlashq_n_s16.c | 22 + .../arm/mve/intrinsics/vqrdmlashq_n_s32.c | 22 + .../arm/mve/intrinsics/vqrdmlashq_n_s8.c | 22 + .../arm/mve/intrinsics/vqrdmlashq_n_u16.c | 22 + .../arm/mve/intrinsics/vqrdmlashq_n_u32.c | 22 + .../arm/mve/intrinsics/vqrdmlashq_n_u8.c | 22 + .../arm/mve/intrinsics/vqrdmlsdhq_m_s16.c | 24 + .../arm/mve/intrinsics/vqrdmlsdhq_m_s32.c | 24 + .../arm/mve/intrinsics/vqrdmlsdhq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c | 22 + .../arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c | 24 + .../arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c | 24 + .../arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c | 24 + .../arm/mve/intrinsics/vqrdmlsdhxq_s16.c | 22 + .../arm/mve/intrinsics/vqrdmlsdhxq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c | 22 + .../arm/mve/intrinsics/vqrdmulhq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqrdmulhq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqrdmulhq_m_n_s8.c | 24 + .../arm/mve/intrinsics/vqrdmulhq_m_s16.c | 24 + .../arm/mve/intrinsics/vqrdmulhq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c | 24 + .../arm/mve/intrinsics/vqrdmulhq_n_s16.c | 22 + .../arm/mve/intrinsics/vqrdmulhq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c | 22 + .../arm/mve/intrinsics/vqrshlq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vqrshlq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s8.c | 23 + .../arm/mve/intrinsics/vqrshlq_m_n_u16.c | 23 + .../arm/mve/intrinsics/vqrshlq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrshlq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrshlq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrshlq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrshlq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrshlq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqrshlq_u8.c | 22 + .../arm/mve/intrinsics/vqrshrnbq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqrshrnbq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqrshrnbq_m_n_u16.c | 24 + .../arm/mve/intrinsics/vqrshrnbq_m_n_u32.c | 24 + .../arm/mve/intrinsics/vqrshrnbq_n_s16.c | 22 + .../arm/mve/intrinsics/vqrshrnbq_n_s32.c | 22 + .../arm/mve/intrinsics/vqrshrnbq_n_u16.c | 22 + .../arm/mve/intrinsics/vqrshrnbq_n_u32.c | 22 + .../arm/mve/intrinsics/vqrshrntq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqrshrntq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqrshrntq_m_n_u16.c | 24 + .../arm/mve/intrinsics/vqrshrntq_m_n_u32.c | 24 + .../arm/mve/intrinsics/vqrshrntq_n_s16.c | 22 + .../arm/mve/intrinsics/vqrshrntq_n_s32.c | 22 + .../arm/mve/intrinsics/vqrshrntq_n_u16.c | 22 + .../arm/mve/intrinsics/vqrshrntq_n_u32.c | 22 + .../arm/mve/intrinsics/vqrshrunbq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqrshrunbq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqrshrunbq_n_s16.c | 22 + .../arm/mve/intrinsics/vqrshrunbq_n_s32.c | 22 + .../arm/mve/intrinsics/vqrshruntq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqrshruntq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqrshruntq_n_s16.c | 22 + .../arm/mve/intrinsics/vqrshruntq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_r_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_r_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_r_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_r_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_r_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_r_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqshlq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshlq_u8.c | 22 + .../arm/mve/intrinsics/vqshluq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vqshluq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c | 22 + .../arm/mve/intrinsics/vqshrnbq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqshrnbq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqshrnbq_m_n_u16.c | 24 + .../arm/mve/intrinsics/vqshrnbq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqshrnbq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshrnbq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshrnbq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshrnbq_n_u32.c | 22 + .../arm/mve/intrinsics/vqshrntq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqshrntq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqshrntq_m_n_u16.c | 24 + .../arm/mve/intrinsics/vqshrntq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqshrntq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshrntq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshrntq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqshrntq_n_u32.c | 22 + .../arm/mve/intrinsics/vqshrunbq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqshrunbq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqshrunbq_n_s16.c | 22 + .../arm/mve/intrinsics/vqshrunbq_n_s32.c | 22 + .../arm/mve/intrinsics/vqshruntq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vqshruntq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vqshruntq_n_s16.c | 22 + .../arm/mve/intrinsics/vqshruntq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqsubq_u8.c | 22 + .../arm/mve/intrinsics/vreinterpretq_f16.c | 45 + .../arm/mve/intrinsics/vreinterpretq_f32.c | 45 + .../arm/mve/intrinsics/vreinterpretq_s16.c | 45 + .../arm/mve/intrinsics/vreinterpretq_s32.c | 45 + .../arm/mve/intrinsics/vreinterpretq_s64.c | 46 + .../arm/mve/intrinsics/vreinterpretq_s8.c | 45 + .../arm/mve/intrinsics/vreinterpretq_u16.c | 45 + .../arm/mve/intrinsics/vreinterpretq_u32.c | 45 + .../arm/mve/intrinsics/vreinterpretq_u64.c | 46 + .../arm/mve/intrinsics/vreinterpretq_u8.c | 45 + .../gcc.target/arm/mve/intrinsics/vrev16q_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev16q_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev16q_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev16q_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev32q_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vrev32q_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev32q_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev32q_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev32q_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev32q_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev32q_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev32q_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev32q_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev32q_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vrev64q_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vrev64q_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vrhaddq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrhaddq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrhaddq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrhaddq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrhaddq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrhaddq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c | 23 + .../arm/mve/intrinsics/vrmlaldavhaq_p_s32.c | 22 + .../arm/mve/intrinsics/vrmlaldavhaq_p_u32.c | 22 + .../arm/mve/intrinsics/vrmlaldavhaq_s32.c | 22 + .../arm/mve/intrinsics/vrmlaldavhaq_u32.c | 22 + .../arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c | 22 + .../arm/mve/intrinsics/vrmlaldavhaxq_s32.c | 22 + .../arm/mve/intrinsics/vrmlaldavhq_p_s32.c | 22 + .../arm/mve/intrinsics/vrmlaldavhq_p_u32.c | 22 + .../arm/mve/intrinsics/vrmlaldavhq_s32.c | 22 + .../arm/mve/intrinsics/vrmlaldavhq_u32.c | 22 + .../arm/mve/intrinsics/vrmlaldavhxq_p_s32.c | 22 + .../arm/mve/intrinsics/vrmlaldavhxq_s32.c | 22 + .../arm/mve/intrinsics/vrmlsldavhaq_p_s32.c | 22 + .../arm/mve/intrinsics/vrmlsldavhaq_s32.c | 22 + .../arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c | 22 + .../arm/mve/intrinsics/vrmlsldavhaxq_s32.c | 22 + .../arm/mve/intrinsics/vrmlsldavhq_p_s32.c | 22 + .../arm/mve/intrinsics/vrmlsldavhq_s32.c | 22 + .../arm/mve/intrinsics/vrmlsldavhxq_p_s32.c | 22 + .../arm/mve/intrinsics/vrmlsldavhxq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vrmulhq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrmulhq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrmulhq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrmulhq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrmulhq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrmulhq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndaq_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndaq_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndmq_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndmq_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndnq_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndnq_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndpq_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndpq_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndq_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndq_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndxq_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndxq_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c | 23 + .../arm/mve/intrinsics/vrshrnbq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vrshrnbq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vrshrnbq_m_n_u16.c | 24 + .../arm/mve/intrinsics/vrshrnbq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c | 22 + .../arm/mve/intrinsics/vrshrntq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vrshrntq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vrshrntq_m_n_u16.c | 24 + .../arm/mve/intrinsics/vrshrntq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vsbciq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vsbciq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vsbcq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vsbcq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlcq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlcq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlcq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlcq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlcq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlcq_u8.c | 22 + .../arm/mve/intrinsics/vshllbq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c | 24 + .../arm/mve/intrinsics/vshllbq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c | 22 + .../arm/mve/intrinsics/vshllbq_x_n_s16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c | 16 + .../arm/mve/intrinsics/vshllbq_x_n_u16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c | 16 + .../arm/mve/intrinsics/vshlltq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c | 24 + .../arm/mve/intrinsics/vshlltq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c | 22 + .../arm/mve/intrinsics/vshlltq_x_n_s16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c | 16 + .../arm/mve/intrinsics/vshlltq_x_n_u16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vshlq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_r_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_r_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_r_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_r_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_r_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_r_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_s16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_s32.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_s8.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_u16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_u32.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_u8.c | 16 + .../arm/mve/intrinsics/vshrnbq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vshrnbq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vshrnbq_m_n_u16.c | 24 + .../arm/mve/intrinsics/vshrnbq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c | 22 + .../arm/mve/intrinsics/vshrntq_m_n_s16.c | 24 + .../arm/mve/intrinsics/vshrntq_m_n_s32.c | 24 + .../arm/mve/intrinsics/vshrntq_m_n_u16.c | 24 + .../arm/mve/intrinsics/vshrntq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vshrq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshrq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vshrq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vshrq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vshrq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vshrq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c | 16 + .../gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c | 16 + .../gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c | 16 + .../gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vsliq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vsliq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vsliq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vsliq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vsliq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vsliq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vsriq_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vsriq_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vsriq_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vsriq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vsriq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vsriq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_p_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_p_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_p_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_p_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vst2q_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vst2q_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vst2q_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vst2q_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vst2q_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vst2q_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vst2q_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vst2q_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vst4q_f16.c | 38 + .../gcc.target/arm/mve/intrinsics/vst4q_f32.c | 38 + .../gcc.target/arm/mve/intrinsics/vst4q_s16.c | 38 + .../gcc.target/arm/mve/intrinsics/vst4q_s32.c | 38 + .../gcc.target/arm/mve/intrinsics/vst4q_s8.c | 38 + .../gcc.target/arm/mve/intrinsics/vst4q_u16.c | 38 + .../gcc.target/arm/mve/intrinsics/vst4q_u32.c | 38 + .../gcc.target/arm/mve/intrinsics/vst4q_u8.c | 38 + .../gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrbq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrbq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrbq_s8.c | 22 + .../mve/intrinsics/vstrbq_scatter_offset_p_s16.c | 22 + .../mve/intrinsics/vstrbq_scatter_offset_p_s32.c | 22 + .../mve/intrinsics/vstrbq_scatter_offset_p_s8.c | 22 + .../mve/intrinsics/vstrbq_scatter_offset_p_u16.c | 22 + .../mve/intrinsics/vstrbq_scatter_offset_p_u32.c | 22 + .../mve/intrinsics/vstrbq_scatter_offset_p_u8.c | 22 + .../arm/mve/intrinsics/vstrbq_scatter_offset_s16.c | 22 + .../arm/mve/intrinsics/vstrbq_scatter_offset_s32.c | 22 + .../arm/mve/intrinsics/vstrbq_scatter_offset_s8.c | 22 + .../arm/mve/intrinsics/vstrbq_scatter_offset_u16.c | 22 + .../arm/mve/intrinsics/vstrbq_scatter_offset_u32.c | 22 + .../arm/mve/intrinsics/vstrbq_scatter_offset_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrbq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrbq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrbq_u8.c | 22 + .../arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c | 22 + .../arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c | 22 + .../arm/mve/intrinsics/vstrdq_scatter_base_s64.c | 22 + .../arm/mve/intrinsics/vstrdq_scatter_base_u64.c | 22 + .../mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c | 22 + .../mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c | 22 + .../mve/intrinsics/vstrdq_scatter_base_wb_s64.c | 22 + .../mve/intrinsics/vstrdq_scatter_base_wb_u64.c | 22 + .../mve/intrinsics/vstrdq_scatter_offset_p_s64.c | 22 + .../mve/intrinsics/vstrdq_scatter_offset_p_u64.c | 22 + .../arm/mve/intrinsics/vstrdq_scatter_offset_s64.c | 22 + .../arm/mve/intrinsics/vstrdq_scatter_offset_u64.c | 22 + .../vstrdq_scatter_shifted_offset_p_s64.c | 22 + .../vstrdq_scatter_shifted_offset_p_u64.c | 22 + .../intrinsics/vstrdq_scatter_shifted_offset_s64.c | 22 + .../intrinsics/vstrdq_scatter_shifted_offset_u64.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_s32.c | 22 + .../arm/mve/intrinsics/vstrhq_scatter_offset_f16.c | 22 + .../mve/intrinsics/vstrhq_scatter_offset_p_f16.c | 22 + .../mve/intrinsics/vstrhq_scatter_offset_p_s16.c | 22 + .../mve/intrinsics/vstrhq_scatter_offset_p_s32.c | 22 + .../mve/intrinsics/vstrhq_scatter_offset_p_u16.c | 22 + .../mve/intrinsics/vstrhq_scatter_offset_p_u32.c | 22 + .../arm/mve/intrinsics/vstrhq_scatter_offset_s16.c | 22 + .../arm/mve/intrinsics/vstrhq_scatter_offset_s32.c | 22 + .../arm/mve/intrinsics/vstrhq_scatter_offset_u16.c | 22 + .../arm/mve/intrinsics/vstrhq_scatter_offset_u32.c | 22 + .../intrinsics/vstrhq_scatter_shifted_offset_f16.c | 22 + .../vstrhq_scatter_shifted_offset_p_f16.c | 22 + .../vstrhq_scatter_shifted_offset_p_s16.c | 22 + .../vstrhq_scatter_shifted_offset_p_s32.c | 22 + .../vstrhq_scatter_shifted_offset_p_u16.c | 22 + .../vstrhq_scatter_shifted_offset_p_u32.c | 22 + .../intrinsics/vstrhq_scatter_shifted_offset_s16.c | 22 + .../intrinsics/vstrhq_scatter_shifted_offset_s32.c | 22 + .../intrinsics/vstrhq_scatter_shifted_offset_u16.c | 22 + .../intrinsics/vstrhq_scatter_shifted_offset_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrhq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrwq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrwq_s32.c | 22 + .../arm/mve/intrinsics/vstrwq_scatter_base_f32.c | 22 + .../arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c | 22 + .../arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c | 22 + .../arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c | 22 + .../arm/mve/intrinsics/vstrwq_scatter_base_s32.c | 22 + .../arm/mve/intrinsics/vstrwq_scatter_base_u32.c | 22 + .../mve/intrinsics/vstrwq_scatter_base_wb_f32.c | 22 + .../mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c | 22 + .../mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c | 22 + .../mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c | 22 + .../mve/intrinsics/vstrwq_scatter_base_wb_s32.c | 22 + .../mve/intrinsics/vstrwq_scatter_base_wb_u32.c | 22 + .../arm/mve/intrinsics/vstrwq_scatter_offset_f32.c | 22 + .../mve/intrinsics/vstrwq_scatter_offset_p_f32.c | 22 + .../mve/intrinsics/vstrwq_scatter_offset_p_s32.c | 22 + .../mve/intrinsics/vstrwq_scatter_offset_p_u32.c | 22 + .../arm/mve/intrinsics/vstrwq_scatter_offset_s32.c | 22 + .../arm/mve/intrinsics/vstrwq_scatter_offset_u32.c | 22 + .../intrinsics/vstrwq_scatter_shifted_offset_f32.c | 22 + .../vstrwq_scatter_shifted_offset_p_f32.c | 22 + .../vstrwq_scatter_shifted_offset_p_s32.c | 22 + .../vstrwq_scatter_shifted_offset_p_u32.c | 22 + .../intrinsics/vstrwq_scatter_shifted_offset_s32.c | 22 + .../intrinsics/vstrwq_scatter_shifted_offset_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vstrwq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vsubq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vsubq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vsubq_m_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vsubq_m_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vsubq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vsubq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vsubq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vsubq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vsubq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vsubq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vsubq_n_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vsubq_n_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vsubq_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vsubq_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vsubq_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vsubq_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vsubq_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vsubq_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vsubq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vsubq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vsubq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vsubq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vsubq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vsubq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vsubq_x_f16.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_f32.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_s16.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_s32.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_s8.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_u16.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_u32.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_u8.c | 16 + .../arm/mve/intrinsics/vuninitializedq_float.c | 17 + .../arm/mve/intrinsics/vuninitializedq_float1.c | 17 + .../arm/mve/intrinsics/vuninitializedq_int.c | 29 + .../arm/mve/intrinsics/vuninitializedq_int1.c | 29 + gcc/testsuite/gcc.target/arm/mve/mve.exp | 47 + gcc/testsuite/gcc.target/arm/pr78353-1.c | 9 + gcc/testsuite/gcc.target/arm/pr78353-2.c | 10 + gcc/testsuite/gcc.target/arm/simd/bf16_cvt_1.c | 51 + gcc/testsuite/gcc.target/arm/simd/bf16_dot_1.c | 100 + gcc/testsuite/gcc.target/arm/simd/bf16_dot_2.c | 33 + gcc/testsuite/gcc.target/arm/simd/bf16_dot_3.c | 33 + gcc/testsuite/gcc.target/arm/simd/bf16_ma_1.c | 79 + gcc/testsuite/gcc.target/arm/simd/bf16_ma_2.c | 35 + gcc/testsuite/gcc.target/arm/simd/bf16_mmla_1.c | 19 + gcc/testsuite/gcc.target/arm/simd/bf16_vldn_1.c | 152 + gcc/testsuite/gcc.target/arm/simd/bf16_vstn_1.c | 84 + .../gcc.target/i386/avx512vl-vmovdqa64-1.c | 7 +- gcc/testsuite/gcc.target/i386/pr64409.c | 4 +- gcc/testsuite/gcc.target/i386/pr71958.c | 7 +- gcc/testsuite/gcc.target/i386/pr89229-2a.c | 15 + gcc/testsuite/gcc.target/i386/pr89229-2b.c | 13 + gcc/testsuite/gcc.target/i386/pr89229-2c.c | 6 + gcc/testsuite/gcc.target/i386/pr89229-3a.c | 16 + gcc/testsuite/gcc.target/i386/pr89229-3b.c | 12 + gcc/testsuite/gcc.target/i386/pr89229-3c.c | 6 + gcc/testsuite/gcc.target/i386/pr89229-4a.c | 16 + gcc/testsuite/gcc.target/i386/pr89229-4b.c | 7 + gcc/testsuite/gcc.target/i386/pr89229-4c.c | 6 + gcc/testsuite/gcc.target/i386/pr89229-5a.c | 17 + gcc/testsuite/gcc.target/i386/pr89229-5b.c | 6 + gcc/testsuite/gcc.target/i386/pr89229-5c.c | 7 + gcc/testsuite/gcc.target/i386/pr89229-6a.c | 16 + gcc/testsuite/gcc.target/i386/pr89229-6b.c | 6 + gcc/testsuite/gcc.target/i386/pr89229-6c.c | 6 + gcc/testsuite/gcc.target/i386/pr89229-7a.c | 17 + gcc/testsuite/gcc.target/i386/pr89229-7b.c | 6 + gcc/testsuite/gcc.target/i386/pr89229-7c.c | 7 + gcc/testsuite/gcc.target/i386/pr89346.c | 15 + gcc/testsuite/gcc.target/i386/pr90096.c | 2 +- gcc/testsuite/gcc.target/i386/pr91623.c | 2 +- gcc/testsuite/gcc.target/i386/pr93997.c | 4 + gcc/testsuite/gcc.target/i386/pr94088.c | 9 + gcc/testsuite/gcc.target/i386/pr94103.c | 17 + gcc/testsuite/gcc.target/or1k/return-2.c | 2 +- gcc/testsuite/gcc.target/powerpc/20050603-3.c | 5 +- .../powerpc/fold-vec-extract-longlong.p8.c | 25 +- .../gcc.target/powerpc/fold-vec-mule-misc.c | 2 +- .../gcc.target/powerpc/fold-vec-st-char.c | 2 +- .../gcc.target/powerpc/fold-vec-st-float.c | 2 +- gcc/testsuite/gcc.target/powerpc/fold-vec-st-int.c | 2 +- .../gcc.target/powerpc/fold-vec-st-short.c | 2 +- gcc/testsuite/gcc.target/powerpc/p9-minmax-3.c | 17 + gcc/testsuite/gcc.target/powerpc/ppc64-abi-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/ppc64-abi-2.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr68805.c | 5 +- gcc/testsuite/gcc.target/powerpc/pr88233.c | 7 +- gcc/testsuite/gcc.target/powerpc/pr90763.c | 88 + gcc/testsuite/gcc.target/powerpc/pr92132-fp-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr93122.c | 1 + gcc/testsuite/gcc.target/powerpc/pr93800.c | 14 + gcc/testsuite/gcc.target/riscv/interrupt-2.c | 4 - gcc/testsuite/gcc.target/riscv/pr93304.c | 7 +- gcc/testsuite/gcc.target/s390/pr93908.c | 5 + gcc/testsuite/gdc.dg/asm1.d | 9 + gcc/testsuite/gdc.dg/asm5.d | 12 + gcc/testsuite/gdc.dg/imports/pr92216.d | 22 + gcc/testsuite/gdc.dg/pr92216.d | 13 + gcc/testsuite/gdc.dg/pr92309.d | 25 + gcc/testsuite/gdc.test/compilable/b12001.d | 9 + .../gdc.test/compilable/imports/pr9471a.d | 2 + .../gdc.test/compilable/imports/pr9471b.d | 5 + .../gdc.test/compilable/imports/pr9471c.d | 18 + .../gdc.test/compilable/imports/pr9471d.d | 1 + gcc/testsuite/gdc.test/compilable/json.d | 21 + gcc/testsuite/gdc.test/compilable/pr9471.d | 6 + gcc/testsuite/gdc.test/compilable/staticforeach.d | 842 + gcc/testsuite/gdc.test/compilable/test11169.d | 15 + gcc/testsuite/gdc.test/compilable/test17819.d | 17 + gcc/testsuite/gdc.test/compilable/test18871.d | 15 + gcc/testsuite/gdc.test/compilable/test7815.d | 65 + gcc/testsuite/gdc.test/compilable/test7886.d | 5 + gcc/testsuite/gdc.test/fail_compilation/e7804_1.d | 11 + gcc/testsuite/gdc.test/fail_compilation/e7804_2.d | 19 + .../gdc.test/fail_compilation/fail11169.d | 28 - .../gdc.test/fail_compilation/fail19182.d | 18 + .../gdc.test/fail_compilation/fail19336.d | 17 + .../gdc.test/fail_compilation/fail19520.d | 21 + gcc/testsuite/gdc.test/fail_compilation/fail2195.d | 18 + gcc/testsuite/gdc.test/fail_compilation/fail7815.d | 65 - gcc/testsuite/gdc.test/fail_compilation/fail7886.d | 5 - .../gdc.test/fail_compilation/staticforeach1.d | 13 + .../gdc.test/fail_compilation/staticforeach2.d | 13 + .../gdc.test/fail_compilation/staticforeach3.d | 7 + .../gdc.test/fail_compilation/test17307.d | 12 + .../gdc.test/fail_compilation/traits_alone.d | 10 + gcc/testsuite/gdc.test/runnable/arrayop.d | 3 +- gcc/testsuite/gdc.test/runnable/constfold.d | 18 +- gcc/testsuite/gdc.test/runnable/e7804.d | 179 + .../gdc.test/runnable/imports/template13478a.d | 5 +- gcc/testsuite/gdc.test/runnable/staticforeach.d | 45 + gcc/testsuite/gdc.test/runnable/test42.d | 60 +- gcc/testsuite/gdc.test/runnable/traits.d | 38 +- gcc/testsuite/gfortran.dg/analyzer/pr93993.f90 | 33 + gcc/testsuite/gfortran.dg/argument_checking_24.f90 | 8 +- gcc/testsuite/gfortran.dg/associated_8.f90 | 37 + gcc/testsuite/gfortran.dg/data_array_5.f90 | 2 +- gcc/testsuite/gfortran.dg/goacc/declare-2.f95 | 21 +- gcc/testsuite/gfortran.dg/goacc/declare-3.f95 | 10 +- gcc/testsuite/gfortran.dg/goacc/pr78260-2.f90 | 13 +- gcc/testsuite/gfortran.dg/goacc/pr94120-1.f90 | 11 + gcc/testsuite/gfortran.dg/goacc/pr94120-2.f90 | 12 + gcc/testsuite/gfortran.dg/goacc/pr94120-3.f90 | 13 + gcc/testsuite/gfortran.dg/goacc/tile-4.f90 | 27 + gcc/testsuite/gfortran.dg/inquiry_type_ref_6.f90 | 24 + gcc/testsuite/gfortran.dg/pr77351.f90 | 6 +- gcc/testsuite/gfortran.dg/pr90988_4.f | 1 + gcc/testsuite/gfortran.dg/pr91372.f90 | 1 + gcc/testsuite/gfortran.dg/pr93486.f90 | 30 + gcc/testsuite/gfortran.dg/pr93604.f90 | 10 + gcc/testsuite/gfortran.dg/pr93792.f90 | 17 + gcc/testsuite/gfortran.dg/pr93835.f08 | 8 + gcc/testsuite/gfortran.dg/same_type_as_3.f03 | 27 + gcc/testsuite/gfortran.dg/select_type_48.f90 | 31 + .../gfortran.dg/unlimited_polymorphic_31.f03 | 55 + gcc/testsuite/gnat.dg/lto24.adb | 10 + gcc/testsuite/gnat.dg/lto24_pkg1.ads | 17 + gcc/testsuite/gnat.dg/lto24_pkg2.adb | 8 + gcc/testsuite/gnat.dg/lto24_pkg2.ads | 5 + gcc/testsuite/gnat.dg/socket1.adb | 2 +- gcc/testsuite/gnat.dg/subpools1.adb | 82 + gcc/testsuite/lib/scanasm.exp | 2 +- gcc/testsuite/lib/target-supports.exp | 97 +- gcc/testsuite/obj-c++.dg/encode-4.mm | 4 +- gcc/testsuite/objc.dg/encode-2.m | 4 +- gcc/tree-call-cdce.c | 2 +- gcc/tree-data-ref.c | 2 +- gcc/tree-inline.c | 5 +- gcc/tree-loop-distribution.c | 19 +- gcc/tree-nested.c | 37 +- gcc/tree-pretty-print.c | 5 +- gcc/tree-pretty-print.h | 1 + gcc/tree-sra.c | 39 +- gcc/tree-ssa-alias.c | 180 +- gcc/tree-ssa-dom.c | 21 +- gcc/tree-ssa-dse.c | 60 +- gcc/tree-ssa-forwprop.c | 11 +- gcc/tree-ssa-loop-ch.c | 2 +- gcc/tree-ssa-loop-im.c | 3 +- gcc/tree-ssa-loop-split.c | 2 +- gcc/tree-ssa-math-opts.c | 2 +- gcc/tree-ssa-phiopt.c | 10 +- gcc/tree-ssa-pre.c | 27 +- gcc/tree-ssa-reassoc.c | 9 +- gcc/tree-ssa-sccvn.c | 734 +- gcc/tree-ssa-sccvn.h | 13 +- gcc/tree-ssa-scopedtables.c | 5 +- gcc/tree-ssa-scopedtables.h | 2 +- gcc/tree-ssa-strlen.c | 389 +- gcc/tree-ssa-strlen.h | 2 +- gcc/tree-tailcall.c | 3 +- gcc/tree-vect-loop.c | 2 +- gcc/tree-vect-slp.c | 68 +- gcc/tree.c | 12 +- gcc/tree.def | 2 +- gcc/value-prof.c | 4 +- include/ChangeLog | 19 + include/lto-symtab.h | 13 + include/plugin-api.h | 32 +- libatomic/ChangeLog | 13 + libatomic/Makefile.am | 4 +- libatomic/Makefile.in | 3 +- libcpp/po/ChangeLog | 8 + libcpp/po/da.po | 51 +- libcpp/po/ru.po | 47 +- libgcc/ChangeLog | 30 + libgcc/config.host | 2 +- libgcc/config/arm/bpabi-v6m.S | 120 +- libgcc/config/arm/lib1funcs.S | 365 +- libgcc/config/arm/libunwind.S | 88 +- libgcc/config/arm/t-arm | 3 + libgcc/config/s390/t-tpf | 7 + libgcc/libgcov-interface.c | 1 - libgo/MERGE | 2 +- libgo/VERSION | 2 +- libgo/go/cmd/go/internal/modcmd/mod.go | 5 - libgo/go/cmd/go/internal/modload/import.go | 3 +- libgo/go/cmd/go/internal/vet/vet.go | 4 +- libgo/go/cmd/go/internal/web/api.go | 2 +- .../cmd/go/testdata/script/mod_gobuild_import.txt | 59 +- libgo/go/cmd/go/testdata/script/mod_readonly.txt | 1 + libgo/go/cmd/go/testdata/script/vet_flags.txt | 11 + libgo/go/crypto/cipher/gcm.go | 7 +- libgo/go/crypto/cipher/gcm_test.go | 19 +- libgo/go/crypto/elliptic/elliptic.go | 19 +- libgo/go/crypto/x509/pkcs8.go | 2 +- libgo/go/go/build/build.go | 14 +- libgo/go/go/doc/doc.go | 9 +- libgo/go/hash/maphash/maphash.go | 14 +- libgo/go/hash/maphash/maphash_test.go | 23 + libgo/go/internal/poll/fcntl_syscall.go | 2 +- libgo/go/internal/syscall/unix/nonblocking.go | 2 +- libgo/go/math/big/int.go | 4 +- libgo/go/runtime/malloc.go | 7 +- libgo/go/runtime/mkpreempt.go | 9 + libgo/go/runtime/netpoll_stub.go | 17 +- libgo/go/testing/benchmark.go | 1 + libgo/go/testing/sub_test.go | 40 + libgo/go/testing/testing.go | 1 - libgo/runtime/go-signal.c | 63 +- libgomp/ChangeLog | 27 + libgomp/testsuite/libgomp.c++/pr93931.C | 120 + .../libgomp.c-c++-common/function-not-offloaded.c | 1 + libgomp/testsuite/libgomp.c/pr93566.c | 113 + .../libgomp.oacc-c++/firstprivate-mappings-1.C | 9 + .../firstprivate-mappings-1.c | 9 + .../libgomp.oacc-fortran/atomic_capture-1.f90 | 30 +- libiberty/ChangeLog | 17 + libiberty/simple-object.c | 6 + libiberty/testsuite/demangle-expected | 2 +- libphobos/ChangeLog | 8 + libphobos/Makefile.in | 2 +- libphobos/configure | 2 +- libphobos/configure.ac | 2 +- libphobos/libdruntime/MERGE | 2 +- libphobos/libdruntime/Makefile.in | 2 +- libphobos/libdruntime/core/cpuid.d | 36 +- libphobos/libdruntime/core/stdc/errno.d | 328 + libphobos/libdruntime/core/stdc/fenv.d | 2 + libphobos/libdruntime/core/sys/posix/config.d | 8 +- libphobos/libdruntime/core/sys/posix/fcntl.d | 112 +- libphobos/libdruntime/core/sys/posix/semaphore.d | 4 +- libphobos/libdruntime/core/sys/posix/sys/socket.d | 62 +- libphobos/libdruntime/core/sys/posix/sys/stat.d | 236 +- libphobos/libdruntime/core/sys/posix/sys/types.d | 22 +- libphobos/src/MERGE | 2 +- libphobos/src/std/algorithm/iteration.d | 2 +- libphobos/src/std/math.d | 20 +- libsanitizer/ChangeLog | 6 + libsanitizer/configure.tgt | 2 +- libstdc++-v3/ChangeLog | 589 + .../abi/post/hppa-linux-gnu/baseline_symbols.txt | 21 + .../post/x86_64-linux-gnu/x32/baseline_symbols.txt | 7 + libstdc++-v3/include/bits/boost_concept_check.h | 2 +- libstdc++-v3/include/bits/cpp_type_traits.h | 62 + libstdc++-v3/include/bits/hashtable_policy.h | 3 +- libstdc++-v3/include/bits/range_access.h | 5 +- libstdc++-v3/include/bits/ranges_algo.h | 119 +- libstdc++-v3/include/bits/ranges_algobase.h | 118 +- libstdc++-v3/include/bits/ranges_uninitialized.h | 54 +- libstdc++-v3/include/bits/regex.h | 10 - libstdc++-v3/include/bits/stl_algo.h | 150 - libstdc++-v3/include/bits/stl_algobase.h | 265 +- libstdc++-v3/include/bits/stl_iterator.h | 22 + libstdc++-v3/include/bits/stl_multiset.h | 11 - libstdc++-v3/include/bits/stl_numeric.h | 9 + libstdc++-v3/include/bits/stl_set.h | 9 - libstdc++-v3/include/bits/stream_iterator.h | 16 + libstdc++-v3/include/bits/streambuf_iterator.h | 11 + libstdc++-v3/include/bits/unordered_set.h | 15 - libstdc++-v3/include/debug/array | 20 + libstdc++-v3/include/debug/multiset.h | 13 - libstdc++-v3/include/debug/set.h | 12 - libstdc++-v3/include/debug/string | 2 +- libstdc++-v3/include/debug/unordered_set | 16 - libstdc++-v3/include/experimental/executor | 235 +- libstdc++-v3/include/experimental/socket | 18 +- libstdc++-v3/include/experimental/string_view | 6 +- libstdc++-v3/include/std/numeric | 18 + libstdc++-v3/include/std/ranges | 358 +- libstdc++-v3/include/std/shared_mutex | 2 +- libstdc++-v3/include/std/span | 7 +- libstdc++-v3/include/std/stop_token | 12 + libstdc++-v3/include/std/string_view | 7 +- libstdc++-v3/include/std/type_traits | 70 +- libstdc++-v3/include/std/version | 1 + libstdc++-v3/src/c++11/system_error.cc | 3 +- libstdc++-v3/src/c++17/fs_path.cc | 40 + .../testsuite/17_intro/headers/c++1998/charset.cc | 2 +- .../testsuite/17_intro/headers/c++2011/charset.cc | 2 +- .../testsuite/17_intro/headers/c++2014/charset.cc | 2 +- .../testsuite/17_intro/headers/c++2017/charset.cc | 2 +- .../testsuite/17_intro/headers/c++2020/charset.cc | 2 +- libstdc++-v3/testsuite/20_util/bind/91371.cc | 2 +- .../testsuite/20_util/is_function/91371.cc | 2 +- .../20_util/is_member_function_pointer/91371.cc | 2 +- .../20_util/is_nothrow_constructible/94003.cc | 46 + libstdc++-v3/testsuite/20_util/is_object/91371.cc | 2 +- .../specialized_algorithms/destroy/constrained.cc | 15 + .../uninitialized_copy/constrained.cc | 25 + .../uninitialized_fill/94017.cc | 77 + .../uninitialized_fill_n/94017.cc | 77 + .../uninitialized_move/constrained.cc | 25 + .../21_strings/basic_string/cons/char/1.cc | 2 + .../basic_string_view/inserters/94051.cc | 28 + .../array/tuple_interface/get_debug_neg.cc | 6 +- .../tuple_interface/tuple_element_debug_neg.cc | 2 +- .../23_containers/span/back_assert_neg.cc | 1 + .../23_containers/span/first_2_assert_neg.cc | 1 + .../23_containers/span/first_assert_neg.cc | 1 + .../23_containers/span/front_assert_neg.cc | 1 + .../23_containers/span/index_op_assert_neg.cc | 1 + .../23_containers/span/last_2_assert_neg.cc | 1 + .../23_containers/span/last_assert_neg.cc | 1 + .../23_containers/span/subspan_2_assert_neg.cc | 1 + .../23_containers/span/subspan_3_assert_neg.cc | 1 + .../23_containers/span/subspan_4_assert_neg.cc | 1 + .../23_containers/span/subspan_5_assert_neg.cc | 1 + .../23_containers/span/subspan_6_assert_neg.cc | 1 + .../23_containers/span/subspan_assert_neg.cc | 1 + .../unordered_set/allocator/ext_ptr.cc | 2 + .../24_iterators/back_insert_iterator/pr93884.cc | 44 + .../24_iterators/counted_iterator/lwg3389.cc | 35 +- .../24_iterators/front_insert_iterator/pr93884.cc | 44 + .../24_iterators/istream_iterator/cons/sentinel.cc | 36 + .../24_iterators/istream_iterator/sentinel.cc | 57 + .../istreambuf_iterator/cons/sentinel.cc | 26 + .../24_iterators/move_iterator/lwg3390.cc | 35 +- .../testsuite/24_iterators/ostream_iterator/1.cc | 2 +- .../range_operations/advance_debug_neg.cc | 10 +- libstdc++-v3/testsuite/25_algorithms/copy/94013.cc | 78 + .../testsuite/25_algorithms/copy/constrained.cc | 16 +- .../testsuite/25_algorithms/copy_backward/94013.cc | 78 + .../25_algorithms/copy_backward/constexpr.cc | 18 + .../25_algorithms/copy_backward/constrained.cc | 16 +- .../testsuite/25_algorithms/equal/94013.cc | 69 + libstdc++-v3/testsuite/25_algorithms/fill/94013.cc | 45 + libstdc++-v3/testsuite/25_algorithms/fill/94017.cc | 76 + .../testsuite/25_algorithms/fill_n/94017.cc | 76 + .../25_algorithms/inplace_merge/constrained.cc | 2 +- .../25_algorithms/lexicographical_compare/93972.cc | 169 + .../25_algorithms/lexicographical_compare/94013.cc | 71 + .../25_algorithms/lexicographical_compare/uchar.cc | 61 + .../testsuite/25_algorithms/min/concept_checks.cc | 23 + libstdc++-v3/testsuite/25_algorithms/move/93872.cc | 39 + libstdc++-v3/testsuite/25_algorithms/move/94013.cc | 78 + .../testsuite/25_algorithms/move/constrained.cc | 16 +- .../testsuite/25_algorithms/move_backward/93872.cc | 39 + .../testsuite/25_algorithms/move_backward/94013.cc | 78 + .../25_algorithms/move_backward/constrained.cc | 16 +- .../25_algorithms/partial_sort/constrained.cc | 4 +- .../25_algorithms/partial_sort_copy/constrained.cc | 8 +- .../testsuite/25_algorithms/shift_left/1.cc | 104 + .../testsuite/25_algorithms/shift_right/1.cc | 103 + .../testsuite/25_algorithms/shuffle/constrained.cc | 4 +- .../testsuite/25_algorithms/sort/constrained.cc | 4 +- .../25_algorithms/stable_sort/constrained.cc | 4 +- .../testsuite/26_numerics/accumulate/constexpr.cc | 42 + .../26_numerics/adjacent_difference/constexpr.cc | 44 + .../26_numerics/exclusive_scan/constexpr.cc | 44 + .../26_numerics/headers/numeric/synopsis.cc | 111 + .../26_numerics/inclusive_scan/constexpr.cc | 55 + .../26_numerics/inner_product/constexpr.cc | 45 + .../testsuite/26_numerics/iota/constexpr.cc | 31 + .../testsuite/26_numerics/partial_sum/constexpr.cc | 44 + .../testsuite/26_numerics/reduce/constexpr.cc | 52 + .../transform_exclusive_scan/constexpr.cc | 33 + .../transform_inclusive_scan/constexpr.cc | 44 + .../26_numerics/transform_reduce/constexpr.cc | 55 + .../testsuite/27_io/filesystem/operations/all.cc | 2 +- .../testsuite/27_io/filesystem/operations/copy.cc | 2 +- .../27_io/filesystem/operations/file_size.cc | 12 +- .../27_io/filesystem/operations/last_write_time.cc | 77 +- .../27_io/filesystem/path/concat/94063.cc | 111 + .../filesystem/path/generic/generic_string.cc | 11 +- .../testsuite/27_io/filesystem/path/generic/utf.cc | 11 +- .../27_io/filesystem/path/generic/wchar_t.cc | 11 +- .../condition_variable_any/stop_token/wait_on.cc | 1 + .../testsuite/30_threads/jthread/jthread.cc | 1 + .../30_threads/shared_timed_mutex/94069.cc | 28 + .../30_threads/stop_token/stop_callback.cc | 1 + .../stop_token/stop_callback/deadlock-mt.cc | 1 + .../stop_token/stop_callback/deadlock.cc | 1 + .../30_threads/stop_token/stop_callback/destroy.cc | 1 + .../30_threads/stop_token/stop_callback/invoke.cc | 1 + .../testsuite/30_threads/stop_token/stop_source.cc | 1 + .../30_threads/stop_token/stop_source/assign.cc | 1 + .../testsuite/30_threads/stop_token/stop_token.cc | 1 + .../stop_token/stop_token/stop_possible.cc | 1 + .../experimental/filesystem/operations/copy.cc | 2 +- .../filesystem/operations/file_size.cc | 12 +- .../filesystem/operations/last_write_time.cc | 58 +- .../net/execution_context/make_service.cc | 36 + .../testsuite/experimental/net/executor/1.cc | 93 + libstdc++-v3/testsuite/lib/libstdc++.exp | 2 +- .../testsuite/std/ranges/adaptors/93978.cc | 35 + libstdc++-v3/testsuite/std/ranges/adaptors/drop.cc | 57 + .../testsuite/std/ranges/adaptors/drop_while.cc | 38 +- .../testsuite/std/ranges/adaptors/filter.cc | 36 + libstdc++-v3/testsuite/std/ranges/adaptors/join.cc | 23 + .../testsuite/std/ranges/adaptors/lwg3286.cc | 72 + .../testsuite/std/ranges/adaptors/lwg3313_neg.cc | 40 + .../testsuite/std/ranges/adaptors/lwg3325_neg.cc | 35 + .../testsuite/std/ranges/adaptors/reverse.cc | 56 + .../testsuite/std/ranges/adaptors/split.cc | 65 + libstdc++-v3/testsuite/std/ranges/adaptors/take.cc | 16 + .../testsuite/std/ranges/adaptors/take_while.cc | 17 + .../testsuite/std/ranges/adaptors/transform.cc | 47 + .../testsuite/std/ranges/iota/lwg3292_neg.cc | 40 + libstdc++-v3/testsuite/std/ranges/istream_view.cc | 16 + .../testsuite/std/ranges/subrange/lwg3286.cc | 71 + libstdc++-v3/testsuite/std/ranges/view.cc | 12 +- .../tr1/8_c_compatibility/cstdlib/functions.cc | 2 +- libstdc++-v3/testsuite/util/testsuite_iterators.h | 94 +- lto-plugin/ChangeLog | 20 + lto-plugin/lto-plugin.c | 141 +- maintainer-scripts/ChangeLog | 11 + maintainer-scripts/gcc_release | 21 +- maintainer-scripts/update_web_docs_git | 5 +- 3360 files changed, 150452 insertions(+), 19959 deletions(-) create mode 100644 gcc/analyzer/bar-chart.cc create mode 100644 gcc/analyzer/bar-chart.h create mode 100644 gcc/analyzer/reachability.h create mode 100644 gcc/config/arm/arm_mve.h create mode 100644 gcc/config/arm/arm_mve_builtins.def create mode 100644 gcc/config/arm/mve.md create mode 100644 gcc/testsuite/g++.dg/DRs/dr1423.C create mode 100644 gcc/testsuite/g++.dg/abi/align3.C create mode 100644 gcc/testsuite/g++.dg/abi/empty30.C create mode 100644 gcc/testsuite/g++.dg/abi/lambda-vis.C create mode 100644 gcc/testsuite/g++.dg/abi/mangle74.C create mode 100644 gcc/testsuite/g++.dg/analyzer/cstdlib-2.C create mode 100644 gcc/testsuite/g++.dg/analyzer/cstdlib.C create mode 100644 gcc/testsuite/g++.dg/analyzer/pr93899.C create mode 100644 gcc/testsuite/g++.dg/analyzer/pr93950.C create mode 100644 gcc/testsuite/g++.dg/analyzer/pr94028.C create mode 100644 gcc/testsuite/g++.dg/concepts/diagnostic2.C create mode 100644 gcc/testsuite/g++.dg/concepts/diagnostic3.C create mode 100644 gcc/testsuite/g++.dg/concepts/diagnostic4.C create mode 100644 gcc/testsuite/g++.dg/concepts/diagnostic6.C create mode 100644 gcc/testsuite/g++.dg/concepts/pr93729.C create mode 100644 gcc/testsuite/g++.dg/concepts/pr93933.C create mode 100644 gcc/testsuite/g++.dg/coroutines/coro1-refs-and-ctors.h create mode 100644 gcc/testsuite/g++.dg/coroutines/torture/class-07-data-member.C create mode 100644 gcc/testsuite/g++.dg/coroutines/torture/co-await-14-template-traits.C create mode 100644 gcc/testsuite/g++.dg/coroutines/torture/co-await-15-capture-comp-ref.C create mode 100644 gcc/testsuite/g++.dg/coroutines/torture/co-await-15-return-non-triv.C create mode 100644 gcc/testsuite/g++.dg/coroutines/torture/co-ret-15-default-retur [...] create mode 100644 gcc/testsuite/g++.dg/coroutines/torture/func-params-07.C create mode 100644 gcc/testsuite/g++.dg/coroutines/torture/func-params-08.C create mode 100644 gcc/testsuite/g++.dg/coroutines/torture/func-params-09-awaitabl [...] create mode 100644 gcc/testsuite/g++.dg/coroutines/torture/lambda-09-init-captures.C create mode 100644 gcc/testsuite/g++.dg/coroutines/torture/lambda-10-mutable.C create mode 100644 gcc/testsuite/g++.dg/coroutines/torture/local-var-5-awaitable.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/constexpr-const3.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/conv-tmpl2.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/conv-tmpl3.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/conv-tmpl4.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/conv-tmpl5.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/conv-tmpl6.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/decltype74.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/decltype75.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/enum40.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/initlist-array11.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/initlist-overload1.C delete mode 100644 gcc/testsuite/g++.dg/cpp0x/initlist116.C delete mode 100644 gcc/testsuite/g++.dg/cpp0x/initlist117.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/initlist121.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/initlist122.C delete mode 100644 gcc/testsuite/g++.dg/cpp0x/lambda/lambda-eh.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/lambda/lambda-variadic10.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/noexcept57.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/nsdmi-template19.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/pr93905.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/rv-cast7.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/variadic178.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/constexpr-tracking-const17.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/constexpr-tracking-const18.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/constexpr-tracking-const19.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/constexpr-tracking-const20.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/constexpr-tracking-const21.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/constexpr-tracking-const22.C create mode 100644 gcc/testsuite/g++.dg/cpp1z/class-deduction70.C create mode 100644 gcc/testsuite/g++.dg/cpp1z/class-deduction71.C create mode 100644 gcc/testsuite/g++.dg/cpp1z/class-deduction72.C create mode 100644 gcc/testsuite/g++.dg/cpp1z/conv-tmpl1.C create mode 100644 gcc/testsuite/g++.dg/cpp2a/concepts-conv1.C create mode 100644 gcc/testsuite/g++.dg/cpp2a/concepts-p2092.C create mode 100644 gcc/testsuite/g++.dg/cpp2a/concepts-using2.C create mode 100644 gcc/testsuite/g++.dg/cpp2a/consteval16.C create mode 100644 gcc/testsuite/g++.dg/cpp2a/constexpr-init16.C create mode 100644 gcc/testsuite/g++.dg/cpp2a/constexpr-init17.C create mode 100644 gcc/testsuite/g++.dg/cpp2a/lambda-pack-init4.C create mode 100644 gcc/testsuite/g++.dg/cpp2a/no_unique_address3.C create mode 100644 gcc/testsuite/g++.dg/cpp2a/nontype-class33.C create mode 100644 gcc/testsuite/g++.dg/diagnostic/pr67960-2.C create mode 100644 gcc/testsuite/g++.dg/diagnostic/pr67960.C delete mode 100644 gcc/testsuite/g++.dg/eh/aggregate1.C create mode 100644 gcc/testsuite/g++.dg/ext/attr-access.C create mode 100644 gcc/testsuite/g++.dg/ext/pr93998.C create mode 100644 gcc/testsuite/g++.dg/ext/pr94197.C create mode 100644 gcc/testsuite/g++.dg/ext/vla22.C create mode 100644 gcc/testsuite/g++.dg/guality/pr93888.C create mode 100644 gcc/testsuite/g++.dg/init/array55.C create mode 100644 gcc/testsuite/g++.dg/init/array56.C create mode 100644 gcc/testsuite/g++.dg/pr94027.C create mode 100644 gcc/testsuite/g++.dg/template/deduce4.C create mode 100644 gcc/testsuite/g++.dg/template/deduce5.C create mode 100644 gcc/testsuite/g++.dg/template/deduce6.C create mode 100644 gcc/testsuite/g++.dg/template/deduce7.C create mode 100644 gcc/testsuite/g++.dg/torture/pr92152.C create mode 100644 gcc/testsuite/g++.dg/torture/pr93347.C create mode 100644 gcc/testsuite/g++.dg/torture/pr94202.C create mode 100644 gcc/testsuite/g++.dg/torture/pr94216.C create mode 100644 gcc/testsuite/g++.dg/tree-ssa/pr94224.C create mode 100644 gcc/testsuite/g++.dg/warn/Wconversion-pr94067.C create mode 100644 gcc/testsuite/g++.dg/warn/Wmismatched-tags-2.C create mode 100644 gcc/testsuite/g++.dg/warn/Wredundant-tags-4.C create mode 100644 gcc/testsuite/g++.dg/warn/Wredundant-tags-5.C create mode 100644 gcc/testsuite/g++.dg/warn/Wredundant-tags-5.h create mode 100644 gcc/testsuite/g++.target/aarch64/pr94052.C create mode 100644 gcc/testsuite/g++.target/i386/pr94046-1.C create mode 100644 gcc/testsuite/g++.target/i386/pr94046-2.C create mode 100644 gcc/testsuite/g++.target/i386/pr94185.C create mode 100644 gcc/testsuite/gcc.c-torture/compile/20200313-1.c create mode 100644 gcc/testsuite/gcc.c-torture/compile/pr90275.c create mode 100644 gcc/testsuite/gcc.c-torture/compile/pr93927-1.c create mode 100644 gcc/testsuite/gcc.c-torture/compile/pr93927-2.c create mode 100644 gcc/testsuite/gcc.c-torture/compile/pr93949.c create mode 100644 gcc/testsuite/gcc.c-torture/compile/pr94179.c create mode 100644 gcc/testsuite/gcc.c-torture/execute/pr90311.c create mode 100644 gcc/testsuite/gcc.c-torture/execute/pr93582.c create mode 100644 gcc/testsuite/gcc.c-torture/execute/pr93908.c create mode 100644 gcc/testsuite/gcc.c-torture/execute/pr93945.c create mode 100644 gcc/testsuite/gcc.c-torture/execute/pr94130.c create mode 100644 gcc/testsuite/gcc.c-torture/execute/pr94134.c create mode 100644 gcc/testsuite/gcc.c-torture/pr92372.c create mode 100644 gcc/testsuite/gcc.dg/Wbuiltin-declaration-mismatch-13.c create mode 100644 gcc/testsuite/gcc.dg/Wbuiltin-declaration-mismatch-14.c create mode 100644 gcc/testsuite/gcc.dg/Wbuiltin-declaration-mismatch-15.c create mode 100644 gcc/testsuite/gcc.dg/Wstringop-overflow-32.c create mode 100644 gcc/testsuite/gcc.dg/analyzer/analyzer-verbosity-2a.c create mode 100644 gcc/testsuite/gcc.dg/analyzer/analyzer-verbosity-3.c create mode 100644 gcc/testsuite/gcc.dg/analyzer/analyzer-verbosity-3a.c create mode 100644 gcc/testsuite/gcc.dg/analyzer/edges-1.c create mode 100644 gcc/testsuite/gcc.dg/analyzer/edges-2.c create mode 100644 gcc/testsuite/gcc.dg/analyzer/expect-1.c create mode 100644 gcc/testsuite/gcc.dg/analyzer/malloc-4.c create mode 100644 gcc/testsuite/gcc.dg/analyzer/pr94047.c create mode 100644 gcc/testsuite/gcc.dg/analyzer/pr94099.c create mode 100644 gcc/testsuite/gcc.dg/analyzer/pr94105.c create mode 100644 gcc/testsuite/gcc.dg/analyzer/torture/pr93947.c create mode 100644 gcc/testsuite/gcc.dg/attr-flatten-1.c create mode 100644 gcc/testsuite/gcc.dg/attr-weakref-5.c create mode 100644 gcc/testsuite/gcc.dg/debug/dwarf2/pr93751-1.c create mode 100644 gcc/testsuite/gcc.dg/debug/dwarf2/pr93751-2.c create mode 100644 gcc/testsuite/gcc.dg/dfp/pr94111.c create mode 100644 gcc/testsuite/gcc.dg/format/proto.c create mode 100644 gcc/testsuite/gcc.dg/graphite/pr93964.c create mode 100644 gcc/testsuite/gcc.dg/ipa/pr93707.c create mode 100644 gcc/testsuite/gcc.dg/lto/pr94157_0.c create mode 100644 gcc/testsuite/gcc.dg/pr93399.c create mode 100644 gcc/testsuite/gcc.dg/pr93577-1.c create mode 100644 gcc/testsuite/gcc.dg/pr93577-2.c create mode 100644 gcc/testsuite/gcc.dg/pr93577-3.c create mode 100644 gcc/testsuite/gcc.dg/pr93577-4.c create mode 100644 gcc/testsuite/gcc.dg/pr93577-5.c create mode 100644 gcc/testsuite/gcc.dg/pr93577-6.c create mode 100644 gcc/testsuite/gcc.dg/pr93582.c create mode 100644 gcc/testsuite/gcc.dg/pr93820-2.c create mode 100644 gcc/testsuite/gcc.dg/pr93820.c create mode 100644 gcc/testsuite/gcc.dg/pr93874.c create mode 100644 gcc/testsuite/gcc.dg/pr93953.c create mode 100644 gcc/testsuite/gcc.dg/pr93986.c create mode 100644 gcc/testsuite/gcc.dg/pr93995.c create mode 100644 gcc/testsuite/gcc.dg/pr94001.c create mode 100644 gcc/testsuite/gcc.dg/pr94002.c create mode 100644 gcc/testsuite/gcc.dg/pr94015.c create mode 100644 gcc/testsuite/gcc.dg/pr94114.c create mode 100644 gcc/testsuite/gcc.dg/pr94121.c create mode 100644 gcc/testsuite/gcc.dg/pr94166.c create mode 100644 gcc/testsuite/gcc.dg/pr94167.c create mode 100644 gcc/testsuite/gcc.dg/pr94172-1.c create mode 100644 gcc/testsuite/gcc.dg/pr94172-2.c create mode 100644 gcc/testsuite/gcc.dg/pr94188.c create mode 100644 gcc/testsuite/gcc.dg/pr94189.c create mode 100644 gcc/testsuite/gcc.dg/pr94211.c create mode 100644 gcc/testsuite/gcc.dg/pragma-diag-8.c create mode 100644 gcc/testsuite/gcc.dg/strlenopt-94.c create mode 100644 gcc/testsuite/gcc.dg/torture/20200311-1.c create mode 100644 gcc/testsuite/gcc.dg/torture/pr92152.c create mode 100644 gcc/testsuite/gcc.dg/torture/pr93868.c create mode 100644 gcc/testsuite/gcc.dg/torture/pr93946-1.c create mode 100644 gcc/testsuite/gcc.dg/torture/pr93946-2.c create mode 100644 gcc/testsuite/gcc.dg/torture/pr94206.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/alias-access-path-12.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/builtin-sprintf-warn-24.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr93435.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr93582-10.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr93582-11.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr93582-4.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr93582-5.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr93582-6.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr93582-7.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr93582-8.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr93582-9.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr94125.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-86.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-87.c create mode 100644 gcc/testsuite/gcc.dg/vect/pr93843-1.c create mode 100644 gcc/testsuite/gcc.dg/vect/pr93843-2.c create mode 100644 gcc/testsuite/gcc.misc-tests/gcov-pr94029.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bf16_dup.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bf16_reinterpret.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bf16_vldn.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bf16_vstn.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bfcvt-compile.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bfcvt-nobf16.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bfcvt-nosimd.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bfcvtn-nobf16.c create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bfcvtnq2-untied.c create mode 100644 gcc/testsuite/gcc.target/aarch64/pr94072.c create mode 100644 gcc/testsuite/gcc.target/aarch64/pr94201.c create mode 100644 gcc/testsuite/gcc.target/arm/bf16_dup.c create mode 100644 gcc/testsuite/gcc.target/arm/bf16_reinterpret.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu2.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_fpu3.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_libcall1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_libcall2.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_move_gpr_to_gpr.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float2.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int2.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_uint2.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot180_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot270_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q_m.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q_m.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q_m.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q_m.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f16_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_m_f32_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_x_f32_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_m_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_m_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_m_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f16_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_m_f32_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_x_f32_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offset_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_z_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offset_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offset_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_z_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offset_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_offse [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_shift [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavaxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmladavxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpnot.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vpselq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmullbq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmulltq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovntq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshruntq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_r_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrntq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrunbq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshruntq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsliq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst4q_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_scatter_offset_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrbq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrhq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offs [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shif [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_float.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_float1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_int.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_int1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/mve.exp create mode 100644 gcc/testsuite/gcc.target/arm/pr78353-1.c create mode 100644 gcc/testsuite/gcc.target/arm/pr78353-2.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/bf16_cvt_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/bf16_dot_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/bf16_dot_2.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/bf16_dot_3.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/bf16_ma_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/bf16_ma_2.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/bf16_mmla_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/bf16_vldn_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/bf16_vstn_1.c create mode 100644 gcc/testsuite/gcc.target/i386/pr89229-2a.c create mode 100644 gcc/testsuite/gcc.target/i386/pr89229-2b.c create mode 100644 gcc/testsuite/gcc.target/i386/pr89229-2c.c create mode 100644 gcc/testsuite/gcc.target/i386/pr89229-3a.c create mode 100644 gcc/testsuite/gcc.target/i386/pr89229-3b.c create mode 100644 gcc/testsuite/gcc.target/i386/pr89229-3c.c create mode 100644 gcc/testsuite/gcc.target/i386/pr89229-4a.c create mode 100644 gcc/testsuite/gcc.target/i386/pr89229-4b.c create mode 100644 gcc/testsuite/gcc.target/i386/pr89229-4c.c create mode 100644 gcc/testsuite/gcc.target/i386/pr89229-5a.c create mode 100644 gcc/testsuite/gcc.target/i386/pr89229-5b.c create mode 100644 gcc/testsuite/gcc.target/i386/pr89229-5c.c create mode 100644 gcc/testsuite/gcc.target/i386/pr89229-6a.c create mode 100644 gcc/testsuite/gcc.target/i386/pr89229-6b.c create mode 100644 gcc/testsuite/gcc.target/i386/pr89229-6c.c create mode 100644 gcc/testsuite/gcc.target/i386/pr89229-7a.c create mode 100644 gcc/testsuite/gcc.target/i386/pr89229-7b.c create mode 100644 gcc/testsuite/gcc.target/i386/pr89229-7c.c create mode 100644 gcc/testsuite/gcc.target/i386/pr89346.c create mode 100644 gcc/testsuite/gcc.target/i386/pr93997.c create mode 100644 gcc/testsuite/gcc.target/i386/pr94088.c create mode 100644 gcc/testsuite/gcc.target/i386/pr94103.c create mode 100644 gcc/testsuite/gcc.target/powerpc/p9-minmax-3.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr90763.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr93800.c create mode 100644 gcc/testsuite/gcc.target/s390/pr93908.c create mode 100644 gcc/testsuite/gdc.dg/asm5.d create mode 100644 gcc/testsuite/gdc.dg/imports/pr92216.d create mode 100644 gcc/testsuite/gdc.dg/pr92216.d create mode 100644 gcc/testsuite/gdc.dg/pr92309.d create mode 100644 gcc/testsuite/gdc.test/compilable/b12001.d create mode 100644 gcc/testsuite/gdc.test/compilable/imports/pr9471a.d create mode 100644 gcc/testsuite/gdc.test/compilable/imports/pr9471b.d create mode 100644 gcc/testsuite/gdc.test/compilable/imports/pr9471c.d create mode 100644 gcc/testsuite/gdc.test/compilable/imports/pr9471d.d create mode 100644 gcc/testsuite/gdc.test/compilable/pr9471.d create mode 100644 gcc/testsuite/gdc.test/compilable/staticforeach.d create mode 100644 gcc/testsuite/gdc.test/compilable/test17819.d create mode 100644 gcc/testsuite/gdc.test/compilable/test18871.d create mode 100644 gcc/testsuite/gdc.test/compilable/test7815.d create mode 100644 gcc/testsuite/gdc.test/compilable/test7886.d create mode 100644 gcc/testsuite/gdc.test/fail_compilation/e7804_1.d create mode 100644 gcc/testsuite/gdc.test/fail_compilation/e7804_2.d delete mode 100644 gcc/testsuite/gdc.test/fail_compilation/fail11169.d create mode 100644 gcc/testsuite/gdc.test/fail_compilation/fail19182.d create mode 100644 gcc/testsuite/gdc.test/fail_compilation/fail19336.d create mode 100644 gcc/testsuite/gdc.test/fail_compilation/fail19520.d create mode 100644 gcc/testsuite/gdc.test/fail_compilation/fail2195.d delete mode 100644 gcc/testsuite/gdc.test/fail_compilation/fail7815.d delete mode 100644 gcc/testsuite/gdc.test/fail_compilation/fail7886.d create mode 100644 gcc/testsuite/gdc.test/fail_compilation/staticforeach1.d create mode 100644 gcc/testsuite/gdc.test/fail_compilation/staticforeach2.d create mode 100644 gcc/testsuite/gdc.test/fail_compilation/staticforeach3.d create mode 100644 gcc/testsuite/gdc.test/fail_compilation/test17307.d create mode 100644 gcc/testsuite/gdc.test/fail_compilation/traits_alone.d create mode 100644 gcc/testsuite/gdc.test/runnable/e7804.d create mode 100644 gcc/testsuite/gdc.test/runnable/staticforeach.d create mode 100644 gcc/testsuite/gfortran.dg/analyzer/pr93993.f90 create mode 100644 gcc/testsuite/gfortran.dg/associated_8.f90 create mode 100644 gcc/testsuite/gfortran.dg/goacc/pr94120-1.f90 create mode 100644 gcc/testsuite/gfortran.dg/goacc/pr94120-2.f90 create mode 100644 gcc/testsuite/gfortran.dg/goacc/pr94120-3.f90 create mode 100644 gcc/testsuite/gfortran.dg/goacc/tile-4.f90 create mode 100644 gcc/testsuite/gfortran.dg/inquiry_type_ref_6.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr93486.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr93604.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr93792.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr93835.f08 create mode 100644 gcc/testsuite/gfortran.dg/same_type_as_3.f03 create mode 100644 gcc/testsuite/gfortran.dg/select_type_48.f90 create mode 100644 gcc/testsuite/gfortran.dg/unlimited_polymorphic_31.f03 create mode 100644 gcc/testsuite/gnat.dg/lto24.adb create mode 100644 gcc/testsuite/gnat.dg/lto24_pkg1.ads create mode 100644 gcc/testsuite/gnat.dg/lto24_pkg2.adb create mode 100644 gcc/testsuite/gnat.dg/lto24_pkg2.ads create mode 100644 gcc/testsuite/gnat.dg/subpools1.adb create mode 100644 libgcc/config/s390/t-tpf create mode 100644 libgomp/testsuite/libgomp.c++/pr93931.C create mode 100644 libgomp/testsuite/libgomp.c/pr93566.c create mode 100644 libstdc++-v3/testsuite/20_util/is_nothrow_constructible/94003.cc create mode 100644 libstdc++-v3/testsuite/20_util/specialized_algorithms/uninitial [...] create mode 100644 libstdc++-v3/testsuite/20_util/specialized_algorithms/uninitial [...] create mode 100644 libstdc++-v3/testsuite/21_strings/basic_string_view/inserters/94051.cc create mode 100644 libstdc++-v3/testsuite/24_iterators/back_insert_iterator/pr93884.cc create mode 100644 libstdc++-v3/testsuite/24_iterators/front_insert_iterator/pr93884.cc create mode 100644 libstdc++-v3/testsuite/24_iterators/istream_iterator/cons/sentinel.cc create mode 100644 libstdc++-v3/testsuite/24_iterators/istream_iterator/sentinel.cc create mode 100644 libstdc++-v3/testsuite/24_iterators/istreambuf_iterator/cons/se [...] create mode 100644 libstdc++-v3/testsuite/25_algorithms/copy/94013.cc create mode 100644 libstdc++-v3/testsuite/25_algorithms/copy_backward/94013.cc create mode 100644 libstdc++-v3/testsuite/25_algorithms/equal/94013.cc create mode 100644 libstdc++-v3/testsuite/25_algorithms/fill/94013.cc create mode 100644 libstdc++-v3/testsuite/25_algorithms/fill/94017.cc create mode 100644 libstdc++-v3/testsuite/25_algorithms/fill_n/94017.cc create mode 100644 libstdc++-v3/testsuite/25_algorithms/lexicographical_compare/93972.cc create mode 100644 libstdc++-v3/testsuite/25_algorithms/lexicographical_compare/94013.cc create mode 100644 libstdc++-v3/testsuite/25_algorithms/lexicographical_compare/uchar.cc create mode 100644 libstdc++-v3/testsuite/25_algorithms/min/concept_checks.cc create mode 100644 libstdc++-v3/testsuite/25_algorithms/move/93872.cc create mode 100644 libstdc++-v3/testsuite/25_algorithms/move/94013.cc create mode 100644 libstdc++-v3/testsuite/25_algorithms/move_backward/93872.cc create mode 100644 libstdc++-v3/testsuite/25_algorithms/move_backward/94013.cc create mode 100644 libstdc++-v3/testsuite/25_algorithms/shift_left/1.cc create mode 100644 libstdc++-v3/testsuite/25_algorithms/shift_right/1.cc create mode 100644 libstdc++-v3/testsuite/26_numerics/accumulate/constexpr.cc create mode 100644 libstdc++-v3/testsuite/26_numerics/adjacent_difference/constexpr.cc create mode 100644 libstdc++-v3/testsuite/26_numerics/exclusive_scan/constexpr.cc create mode 100644 libstdc++-v3/testsuite/26_numerics/inclusive_scan/constexpr.cc create mode 100644 libstdc++-v3/testsuite/26_numerics/inner_product/constexpr.cc create mode 100644 libstdc++-v3/testsuite/26_numerics/iota/constexpr.cc create mode 100644 libstdc++-v3/testsuite/26_numerics/partial_sum/constexpr.cc create mode 100644 libstdc++-v3/testsuite/26_numerics/reduce/constexpr.cc create mode 100644 libstdc++-v3/testsuite/26_numerics/transform_exclusive_scan/con [...] create mode 100644 libstdc++-v3/testsuite/26_numerics/transform_inclusive_scan/con [...] create mode 100644 libstdc++-v3/testsuite/26_numerics/transform_reduce/constexpr.cc create mode 100644 libstdc++-v3/testsuite/27_io/filesystem/path/concat/94063.cc create mode 100644 libstdc++-v3/testsuite/30_threads/shared_timed_mutex/94069.cc create mode 100644 libstdc++-v3/testsuite/experimental/net/execution_context/make_ [...] create mode 100644 libstdc++-v3/testsuite/experimental/net/executor/1.cc create mode 100644 libstdc++-v3/testsuite/std/ranges/adaptors/93978.cc create mode 100644 libstdc++-v3/testsuite/std/ranges/adaptors/lwg3286.cc create mode 100644 libstdc++-v3/testsuite/std/ranges/adaptors/lwg3313_neg.cc create mode 100644 libstdc++-v3/testsuite/std/ranges/adaptors/lwg3325_neg.cc create mode 100644 libstdc++-v3/testsuite/std/ranges/iota/lwg3292_neg.cc create mode 100644 libstdc++-v3/testsuite/std/ranges/subrange/lwg3286.cc