[Tcwg-commits] [gcc] branch master updated (316c83b158d -> b7e4f61c3e7)

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from 316c83b158d RISC-V: Add vwadd v C++ api test new 5e620b36cd3 RISC-V: allow vx instruction use "zero" as scalar register. new cb44a16d212 RISC-V: Add vadc/vsbc C/C++ API support new b5e7450a173 RISC-V: Add vadc.vvm/vadc.vxm C API tests new c2f4dc58105 RISC-V: Add vsbc.vvm/vsbc.vxm C API tests new 6483b831033 RISC-V: Add vsbc C++ API tests new b7e4f61c3e7 RISC-V: Add vadc C++ API tests

The 6 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.

Summary of changes: gcc/config/riscv/riscv-protos.h | 1 + gcc/config/riscv/riscv-v.cc | 2 +- gcc/config/riscv/riscv-vector-builtins-bases.cc | 46 +++ gcc/config/riscv/riscv-vector-builtins-bases.h | 2 + .../riscv/riscv-vector-builtins-functions.def | 4 + gcc/config/riscv/riscv-vector-builtins-shapes.cc | 22 ++ gcc/config/riscv/riscv-vector-builtins-shapes.h | 1 + gcc/config/riscv/riscv-vector-builtins.cc | 50 ++- gcc/config/riscv/riscv-vector-builtins.h | 12 + gcc/config/riscv/vector-iterators.md | 3 + gcc/config/riscv/vector.md | 350 +++++++++++++++++++-- .../g++.target/riscv/rvv/base/vadc_vvm-1.C | 292 +++++++++++++++++ .../g++.target/riscv/rvv/base/vadc_vvm-2.C | 292 +++++++++++++++++ .../g++.target/riscv/rvv/base/vadc_vvm-3.C | 292 +++++++++++++++++ .../g++.target/riscv/rvv/base/vadc_vvm_tu-1.C | 292 +++++++++++++++++ .../g++.target/riscv/rvv/base/vadc_vvm_tu-2.C | 292 +++++++++++++++++ .../g++.target/riscv/rvv/base/vadc_vvm_tu-3.C | 292 +++++++++++++++++ .../g++.target/riscv/rvv/base/vadc_vxm_rv32-1.C | 289 +++++++++++++++++ .../g++.target/riscv/rvv/base/vadc_vxm_rv32-2.C | 289 +++++++++++++++++ .../g++.target/riscv/rvv/base/vadc_vxm_rv32-3.C | 289 +++++++++++++++++ .../g++.target/riscv/rvv/base/vadc_vxm_rv64-1.C | 292 +++++++++++++++++ .../g++.target/riscv/rvv/base/vadc_vxm_rv64-2.C | 292 +++++++++++++++++ .../g++.target/riscv/rvv/base/vadc_vxm_rv64-3.C | 292 +++++++++++++++++ .../g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-1.C | 289 +++++++++++++++++ .../g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-2.C | 289 +++++++++++++++++ .../g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-3.C | 289 +++++++++++++++++ .../g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-1.C | 292 +++++++++++++++++ .../g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-2.C | 292 +++++++++++++++++ .../g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-3.C | 292 +++++++++++++++++ .../g++.target/riscv/rvv/base/vsbc_vvm-1.C | 292 +++++++++++++++++ .../g++.target/riscv/rvv/base/vsbc_vvm-2.C | 292 +++++++++++++++++ .../g++.target/riscv/rvv/base/vsbc_vvm-3.C | 292 +++++++++++++++++ .../g++.target/riscv/rvv/base/vsbc_vvm_tu-1.C | 292 +++++++++++++++++ .../g++.target/riscv/rvv/base/vsbc_vvm_tu-2.C | 292 +++++++++++++++++ .../g++.target/riscv/rvv/base/vsbc_vvm_tu-3.C | 292 +++++++++++++++++ .../g++.target/riscv/rvv/base/vsbc_vxm_rv32-1.C | 289 +++++++++++++++++ .../g++.target/riscv/rvv/base/vsbc_vxm_rv32-2.C | 289 +++++++++++++++++ .../g++.target/riscv/rvv/base/vsbc_vxm_rv32-3.C | 289 +++++++++++++++++ .../g++.target/riscv/rvv/base/vsbc_vxm_rv64-1.C | 292 +++++++++++++++++ .../g++.target/riscv/rvv/base/vsbc_vxm_rv64-2.C | 292 +++++++++++++++++ .../g++.target/riscv/rvv/base/vsbc_vxm_rv64-3.C | 292 +++++++++++++++++ .../g++.target/riscv/rvv/base/vsbc_vxm_tu_rv32-1.C | 289 +++++++++++++++++ .../g++.target/riscv/rvv/base/vsbc_vxm_tu_rv32-2.C | 289 +++++++++++++++++ .../g++.target/riscv/rvv/base/vsbc_vxm_tu_rv32-3.C | 289 +++++++++++++++++ .../g++.target/riscv/rvv/base/vsbc_vxm_tu_rv64-1.C | 292 +++++++++++++++++ .../g++.target/riscv/rvv/base/vsbc_vxm_tu_rv64-2.C | 292 +++++++++++++++++ .../g++.target/riscv/rvv/base/vsbc_vxm_tu_rv64-3.C | 292 +++++++++++++++++ .../riscv/rvv/base/binop_vx_constraint-121.c | 55 ++++ gcc/testsuite/gcc.target/riscv/rvv/base/vadc-1.c | 27 ++ gcc/testsuite/gcc.target/riscv/rvv/base/vadc-2.c | 48 +++ gcc/testsuite/gcc.target/riscv/rvv/base/vadc-3.c | 78 +++++ gcc/testsuite/gcc.target/riscv/rvv/base/vadc-4.c | 79 +++++ .../gcc.target/riscv/rvv/base/vadc_vvm-1.c | 292 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vadc_vvm-2.c | 292 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vadc_vvm-3.c | 292 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vadc_vvm_tu-1.c | 292 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vadc_vvm_tu-2.c | 292 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vadc_vvm_tu-3.c | 292 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vadc_vxm_rv32-1.c | 289 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vadc_vxm_rv32-2.c | 289 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vadc_vxm_rv32-3.c | 289 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vadc_vxm_rv64-1.c | 292 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vadc_vxm_rv64-2.c | 292 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vadc_vxm_rv64-3.c | 292 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vadc_vxm_tu_rv32-1.c | 289 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vadc_vxm_tu_rv32-2.c | 289 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vadc_vxm_tu_rv32-3.c | 289 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vadc_vxm_tu_rv64-1.c | 292 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vadc_vxm_tu_rv64-2.c | 292 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vadc_vxm_tu_rv64-3.c | 292 +++++++++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/vsbc-1.c | 27 ++ gcc/testsuite/gcc.target/riscv/rvv/base/vsbc-2.c | 56 ++++ gcc/testsuite/gcc.target/riscv/rvv/base/vsbc-3.c | 77 +++++ gcc/testsuite/gcc.target/riscv/rvv/base/vsbc-4.c | 78 +++++ .../gcc.target/riscv/rvv/base/vsbc_vvm-1.c | 292 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vsbc_vvm-2.c | 292 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vsbc_vvm-3.c | 292 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vsbc_vvm_tu-1.c | 292 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vsbc_vvm_tu-2.c | 292 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vsbc_vvm_tu-3.c | 292 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vsbc_vxm_rv32-1.c | 289 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vsbc_vxm_rv32-2.c | 289 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vsbc_vxm_rv32-3.c | 289 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vsbc_vxm_rv64-1.c | 292 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vsbc_vxm_rv64-2.c | 292 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vsbc_vxm_rv64-3.c | 292 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv32-1.c | 289 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv32-2.c | 289 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv32-3.c | 289 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv64-1.c | 292 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv64-2.c | 292 +++++++++++++++++ .../gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv64-3.c | 292 +++++++++++++++++ 92 files changed, 21939 insertions(+), 31 deletions(-) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vvm-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vvm-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vvm-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vvm_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vvm_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vvm_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsbc_vxm_tu_rv64-3.C create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-121.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vvm-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vvm-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vvm-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vvm_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vvm_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vvm_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_tu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_tu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_tu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_tu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_tu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_tu_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vvm-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vvm-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vvm-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vvm_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vvm_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vvm_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_rv64-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv64-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv64-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsbc_vxm_tu_rv64-3.c