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from 1b5e053f7e8 [X86] Regenerate fsgsbase intrinsic tests. NFCI. new dcfcbe7bdc3 [RISCV] Implement prolog and epilog insertion new d001eea1650 [RISCV] Allow lowering of dynamic_stackalloc, stacksave, st [...]
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Summary of changes: lib/Target/RISCV/RISCVFrameLowering.cpp | 147 ++++++++++++++++++- lib/Target/RISCV/RISCVFrameLowering.h | 15 +- lib/Target/RISCV/RISCVISelLowering.cpp | 5 + test/CodeGen/RISCV/addc-adde-sube-subc.ll | 14 ++ test/CodeGen/RISCV/alloca.ll | 65 +++++++++ test/CodeGen/RISCV/alu32.ll | 133 ++++++++++++++++++ test/CodeGen/RISCV/bare-select.ll | 7 + test/CodeGen/RISCV/blockaddress.ll | 9 +- test/CodeGen/RISCV/branch.ll | 7 + test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll | 135 +++++++++++++----- test/CodeGen/RISCV/calls.ll | 38 ++++- test/CodeGen/RISCV/div.ll | 54 +++++++ test/CodeGen/RISCV/frame.ll | 14 +- test/CodeGen/RISCV/i32-icmp.ll | 70 ++++++++++ test/CodeGen/RISCV/imm.ll | 35 +++++ test/CodeGen/RISCV/indirectbr.ll | 18 ++- test/CodeGen/RISCV/jumptable.ll | 7 + test/CodeGen/RISCV/mem.ll | 84 +++++++++++ test/CodeGen/RISCV/mul.ll | 32 +++++ test/CodeGen/RISCV/rem.ll | 10 ++ test/CodeGen/RISCV/rotl-rotr.ll | 14 ++ test/CodeGen/RISCV/select-cc.ll | 7 + test/CodeGen/RISCV/sext-zext-trunc.ll | 210 ++++++++++++++++++++++++++++ test/CodeGen/RISCV/shifts.ll | 15 ++ test/CodeGen/RISCV/wide-mem.ll | 14 ++ 25 files changed, 1110 insertions(+), 49 deletions(-) create mode 100644 test/CodeGen/RISCV/alloca.ll