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from aa0ab207ffa [InstCombine] Handle (X & C2) < C1 --> (X & C2) == 0 new 34fb94caca2 [NVPTX] Implemented shfl.sync instruction and supporting in [...] new 8e50186c89b [SimplifyCFG] auto-generate full checks; NFC
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Summary of changes: include/llvm/IR/IntrinsicsNVVM.td | 44 +++++ lib/Target/NVPTX/NVPTXIntrinsics.td | 74 +++++++- test/CodeGen/NVPTX/shfl-sync.ll | 94 ++++++++++ test/Transforms/SimplifyCFG/rangereduce.ll | 282 +++++++++++++++++++++-------- 4 files changed, 415 insertions(+), 79 deletions(-) create mode 100644 test/CodeGen/NVPTX/shfl-sync.ll