[Tcwg-commits] [gcc] branch master updated (f56d48b2471 -> 36ba985145f)

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from f56d48b2471 RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests. new 36ba985145f Don't build readline/libreadline.a, when --with-system-read [...]

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Summary of changes: configure | 6 ++++++ configure.ac | 6 ++++++ 2 files changed, 12 insertions(+)