[Tcwg-commits] [llvm] branch master updated (b77f18e -> 7ff284e)

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from b77f18e [Hexagon] Handle spills of partially defined double vector registers new 7ff284e [x86] add tests for potential negation folds

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Summary of changes: test/CodeGen/X86/negate.ll | 80 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) create mode 100644 test/CodeGen/X86/negate.ll