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from 29fec22 [LoopVectorize] Added address space check when analysing inte [...] new 3f55d74 MIRTests: Remove unnecessary 2>&1 redirection
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Summary of changes: test/CodeGen/AArch64/GlobalISel/legalize-add.mir | 2 +- test/CodeGen/AArch64/GlobalISel/legalize-and.mir | 2 +- test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir | 2 +- test/CodeGen/AArch64/GlobalISel/legalize-combines.mir | 2 +- test/CodeGen/AArch64/GlobalISel/legalize-constant.mir | 2 +- test/CodeGen/AArch64/GlobalISel/legalize-div.mir | 2 +- test/CodeGen/AArch64/GlobalISel/legalize-ext.mir | 2 +- test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir | 2 +- test/CodeGen/AArch64/GlobalISel/legalize-fptoi.mir | 2 +- test/CodeGen/AArch64/GlobalISel/legalize-gep.mir | 2 +- test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir | 2 +- test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir | 2 +- test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir | 2 +- test/CodeGen/AArch64/GlobalISel/legalize-mul.mir | 2 +- test/CodeGen/AArch64/GlobalISel/legalize-or.mir | 2 +- test/CodeGen/AArch64/GlobalISel/legalize-pow.mir | 2 +- test/CodeGen/AArch64/GlobalISel/legalize-rem.mir | 2 +- test/CodeGen/AArch64/GlobalISel/legalize-shift.mir | 2 +- test/CodeGen/AArch64/GlobalISel/legalize-simple.mir | 2 +- test/CodeGen/AArch64/GlobalISel/legalize-sub.mir | 2 +- test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir | 2 +- test/CodeGen/AArch64/GlobalISel/legalize-xor.mir | 2 +- test/CodeGen/AArch64/arm64-regress-opt-cmp.mir | 2 +- test/CodeGen/AArch64/ldst-opt.mir | 2 +- test/CodeGen/AArch64/movimm-wzr.mir | 2 +- test/CodeGen/AVR/pseudo/ADCWRdRr.mir | 2 +- test/CodeGen/AVR/pseudo/ADDWRdRr.mir | 2 +- test/CodeGen/AVR/pseudo/ANDIWRdK.mir | 2 +- test/CodeGen/AVR/pseudo/ANDWRdRr.mir | 2 +- test/CodeGen/AVR/pseudo/ASRWRd.mir | 2 +- test/CodeGen/AVR/pseudo/COMWRd.mir | 2 +- test/CodeGen/AVR/pseudo/CPCWRdRr.mir | 2 +- test/CodeGen/AVR/pseudo/CPWRdRr.mir | 2 +- test/CodeGen/AVR/pseudo/EORWRdRr.mir | 2 +- test/CodeGen/AVR/pseudo/FRMIDX.mir | 2 +- test/CodeGen/AVR/pseudo/INWRdA.mir | 2 +- test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir | 2 +- test/CodeGen/AVR/pseudo/LDDWRdYQ.mir | 2 +- test/CodeGen/AVR/pseudo/LDIWRdK.mir | 2 +- test/CodeGen/AVR/pseudo/LDSWRdK.mir | 2 +- test/CodeGen/AVR/pseudo/LDWRdPtr.mir | 2 +- test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir | 2 +- test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir | 2 +- test/CodeGen/AVR/pseudo/LSLWRd.mir | 2 +- test/CodeGen/AVR/pseudo/LSRWRd.mir | 2 +- test/CodeGen/AVR/pseudo/ORIWRdK.mir | 2 +- test/CodeGen/AVR/pseudo/ORWRdRr.mir | 2 +- test/CodeGen/AVR/pseudo/OUTWARr.mir | 2 +- test/CodeGen/AVR/pseudo/POPWRd.mir | 2 +- test/CodeGen/AVR/pseudo/PUSHWRr.mir | 2 +- test/CodeGen/AVR/pseudo/SBCIWRdK.mir | 2 +- test/CodeGen/AVR/pseudo/SBCWRdRr.mir | 2 +- test/CodeGen/AVR/pseudo/SEXT.mir | 2 +- test/CodeGen/AVR/pseudo/STDWPtrQRr.mir | 2 +- test/CodeGen/AVR/pseudo/STSWKRr.mir | 2 +- test/CodeGen/AVR/pseudo/STWPtrPdRr.mir | 2 +- test/CodeGen/AVR/pseudo/STWPtrPiRr.mir | 2 +- test/CodeGen/AVR/pseudo/STWPtrRr.mir | 2 +- test/CodeGen/AVR/pseudo/SUBIWRdK.mir | 2 +- test/CodeGen/AVR/pseudo/SUBWRdRr.mir | 2 +- test/CodeGen/AVR/pseudo/ZEXT.mir | 2 +- test/CodeGen/AVR/pseudo/expand-lddw-dst-src-same.mir | 2 +- test/CodeGen/AVR/relax-mem/STDWPtrQRr.mir | 2 +- test/CodeGen/Hexagon/expand-condsets-rm-reg.mir | 2 +- test/CodeGen/MIR/Generic/llvmIRMissing.mir | 2 +- test/CodeGen/MIR/Generic/machine-basic-block-ir-block-reference.mir | 2 +- test/CodeGen/MIR/Generic/runPass.mir | 2 +- test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir | 2 +- test/CodeGen/X86/implicit-use-spill.mir | 2 +- 69 files changed, 69 insertions(+), 69 deletions(-)