[Tcwg-commits] [toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-allnoconfig updated (3285ee143b7 -> 8ab5770a17f)

21 Dec 2020


      This is an automated email from the git hooks/post-receive script.
tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-allnoconfig
in repository toolchain/ci/llvm-project.
from  3285ee143b7 [Analysis, IR, CodeGen] Use llvm::erase_if (NFC)
      adds  5d24935f220 [PGO] Remove dead member variable InstrumentFuncEntry (NFC)
      adds  43327ba98da [Object] Fix LFFile<ELFT>::getEntry on sizeof(size_t)==4 platforms
      adds  e2863357de7 [lld-macho][nfc] Use split-file in order file test
      adds  5f9896d3b23 [lld-macho] Support Obj-C symbols in order files
      adds  64e47572002 [lld-macho] Have order files support filtering by archive m [...]
      adds  bfa95b4ac79 [BasicAA] Add test for byval argument (NFC)
      adds  f47bac5dd20 [ARM] Extra vecreduce tests with smaller than legal types. NFC
      adds  47dbee6790c Make NPM OptBisectInstrumentation use global singleton OptBisect
      adds  01d1de81963 [MC] Reject byte alignment if larger than or equal to 2**32
      adds  36b0dd8f678 [OpenMP] Fixed the issue that CMake variables for OpenMP we [...]
      adds  1a883484afe [test] Fix reg-usage.ll under NPM
      adds  4dce7c2e209 [MachineLICM] delete dead flag if the duplicated def outsid [...]
      adds  564066524ad [PowerPC] add has side effect for SAT bit clobber intrinsic [...]
      adds  db1616c7684 [test] Fix new-pass-manager-opt-bisect.c
      adds  966f1431de0 [Target] Use llvm::erase_if (NFC)
      adds  9e4b682baf2 [RISCV][NFC] Add tests for multiplication with constant
      adds  72e75ca343c [MC][ELF] Allow STT_SECTION referencing SHF_MERGE on REL targets
      adds  791fe7ac57a [lld-macho] Fix memcpy ub after D93267
      adds  f314bcffa3c [llvm-reduce][test] Make remove-alias.ll CHECK patterns mor [...]
      adds  553d4d08d2b [MC] Report locations for .symver errors
      adds  e4c360a897f [MC][ELF] Drop MCSymbol::isExternal call sites
      adds  29eb3dcfe62 [PowerPC] Materialize i64 constants by enumerated patterns.
      adds  7b9890e17e9 [MC][ELF] Remove unneeded MCSymbol::setExternal calls
      adds  26d378b801f [PowerPC][NFC] Added assertion of shift exponent is too lar [...]
      adds  e0963ae274b [AsmParser] make .ascii support spaces as separators
      adds  3183add5343 [RISCV] Define the remaining vector fixed-point arithmetic  [...]
      adds  e2303a448e2 [FastRA] Fix handling of bundled MIs
      adds  8ffda237a66 MCContext::reportError: don't call report_fatal_error
      adds  1635dea266c [AsmPrinter] Replace a reachable report_fatal_error with MC [...]
      adds  f6c7ebe76ac [MLIR][SPIRVToLLVM] Updated documentation on entry points a [...]
      adds  3bf7d47a977 [NFC][InstructionCost] Remove isValid() asserts in SLPVecto [...]
      adds  27b7d646886 [clang][cli] Streamline MarshallingInfoFlag description
      adds  70410a26494 [clang][cli] Let denormalizer decide how to render the opti [...]
      adds  5a85526728c [clang] Use enum for LangOptions::SYCLVersion instead of unsigned
      adds  93da221eaf7 [VP][NFC] ISD::VP_Sub -> ISD::VP_SUB
      adds  cd608dc8d3e [VPlan] Use VPDef for VPInterleaveRecipe.
      adds  d99e4a4840d [VE] Support RETURNADDR
      adds  5e273b845bc [VE] Support STACKSAVE and STACKRESTORE
      adds  d6abd7317a2 [flang][driver] Make the names of files created in unit tes [...]
      adds  06b83fd6c75 [TableGen] NFC: Switch to range-based for loops in OptParse [...]
      adds  164bcbd40e6 [TableGen] NFC: Rename variables in OptParserEmitter
      adds  a3a896d1cdc [VE] Optimize LEA combinations
      adds  b2ba6867eac Refactoring the attribute plugin example to fit the new API
      adds  6f45049fb6e [Statepoints] Disable VReg lowering for values used on exce [...]
      adds  f2508923737 [VPlan] Make VPRecipeBase inherit from VPDef.
      adds  8c2ad9e85f6 [VE] Correct VMP allocation in calling conv
      adds  d6118759f30 [InstSimplify] add tests for inverted logic operands; NFC
      adds  38ca7face67 [InstSimplify] reduce logic with inverted add/sub ops
      adds  3a675c777dd [TableGen] Add the !substr() bang operator
      adds  88c5b500606 [AggressiveInstCombine] Generalize foldGuardedRotateToFunne [...]
      adds  d56982b6f5f Remove unused variables.
      adds  554eb1f6dc4 Revert "[TableGen] Add the !substr() bang operator"
       new  e25afcfa51a [ELF][PPC64] Detect missing R_PPC64_TLSGD/R_PPC64_TLSLD and [...]
       new  fb3c1b3de5c [ELF] Reject local-exec TLS relocations for -shared
       new  9a93f95fce9 [clang] Fix expected errors in plugin attribute example
       new  26c8f9081b6 [mlir[[vector] Extend Transfer read/write ops to support te [...]
       new  a323682dcbf [AMDGPU][MC][NFC] Lit tests cleanup
       new  8ab5770a17f [AMDGPU][MC][NFC] Parser refactoring
The 6 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails.  The revisions
listed as "adds" were already present in the repository and have only
been added to this reference.
Summary of changes:
 clang/examples/Attribute/Attribute.cpp             |   49 +-
 clang/include/clang/Basic/LangOptions.def          |    2 +-
 clang/include/clang/Basic/LangOptions.h            |    5 +
 clang/include/clang/Driver/Options.td              |   44 +-
 clang/lib/Frontend/CompilerInvocation.cpp          |   88 +-
 clang/lib/Frontend/InitPreprocessor.cpp            |    2 +-
 clang/test/CodeGen/new-pass-manager-opt-bisect.c   |   12 +
 clang/test/Frontend/plugin-attribute.cpp           |   39 +-
 .../unittests/Frontend/CompilerInvocationTest.cpp  |   44 +-
 flang/unittests/Frontend/FrontendActionTest.cpp    |    4 +-
 lld/ELF/InputFiles.h                               |    4 +
 lld/ELF/Relocations.cpp                            |   61 +-
 lld/MachO/Driver.cpp                               |   94 +-
 lld/MachO/UnwindInfoSection.cpp                    |    5 +-
 lld/MachO/Writer.cpp                               |   18 +-
 lld/test/ELF/Inputs/i386-static-tls-model4.s       |    9 -
 lld/test/ELF/aarch64-tls-le.s                      |    8 +
 lld/test/ELF/arm-tls-le32.s                        |    7 +
 lld/test/ELF/i386-static-tls-model.s               |    8 -
 lld/test/ELF/i386-tls-le.s                         |   57 +-
 lld/test/ELF/i386-zrel-zrela.s                     |    8 +-
 lld/test/ELF/mips-tls-hilo.s                       |    6 +-
 lld/test/ELF/ppc64-local-exec-tls.s                |   12 +
 lld/test/ELF/ppc64-tls-missing-gdld.s              |   85 +-
 lld/test/ELF/riscv-tls-le.s                        |    7 +
 lld/test/ELF/tls.s                                 |   20 +
 lld/test/ELF/x86-64-reloc-tpoff32-fpic.s           |   14 -
 lld/test/MachO/invalid/order-file-bad-arch.test    |    9 -
 lld/test/MachO/invalid/order-file-bad-objfile.test |   10 -
 lld/test/MachO/order-file.s                        |  184 +-
 llvm/include/llvm/IR/IntrinsicsPowerPC.td          |   42 +-
 llvm/include/llvm/IR/IntrinsicsRISCV.td            |   36 +
 llvm/include/llvm/IR/OptBisect.h                   |   20 +-
 llvm/include/llvm/IR/VPIntrinsics.def              |    2 +-
 llvm/include/llvm/MC/MCAssembler.h                 |    7 +-
 llvm/include/llvm/MC/MCSymbol.h                    |    3 +-
 llvm/include/llvm/Object/ELF.h                     |    9 +-
 llvm/include/llvm/Option/OptParser.td              |   12 +-
 .../include/llvm/Passes/StandardInstrumentations.h |    2 +-
 llvm/lib/Analysis/InstructionSimplify.cpp          |   33 +
 llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp         |    4 +-
 llvm/lib/CodeGen/MachineLICM.cpp                   |   37 +-
 llvm/lib/CodeGen/RegAllocFast.cpp                  |   43 +
 .../CodeGen/SelectionDAG/StatepointLowering.cpp    |   24 +-
 llvm/lib/IR/LLVMContextImpl.cpp                    |   15 +-
 llvm/lib/IR/OptBisect.cpp                          |    2 +
 llvm/lib/MC/ELFObjectWriter.cpp                    |   26 +-
 llvm/lib/MC/MCContext.cpp                          |    4 +-
 llvm/lib/MC/MCELFStreamer.cpp                      |   16 +-
 llvm/lib/MC/MCParser/AsmParser.cpp                 |   15 +-
 llvm/lib/Passes/StandardInstrumentations.cpp       |    8 +-
 llvm/lib/Target/AArch64/AArch64ISelLowering.cpp    |    8 +-
 llvm/lib/Target/AArch64/AArch64InstrInfo.cpp       |   10 +-
 .../Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp    |  170 +-
 llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp           |    5 +-
 .../lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp |    2 -
 .../Target/Hexagon/AsmParser/HexagonAsmParser.cpp  |    2 +-
 llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp       |    3 +-
 llvm/lib/Target/Hexagon/HexagonGenInsert.cpp       |    8 +-
 llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp        |  534 ++---
 llvm/lib/Target/PowerPC/PPCInstrAltivec.td         |   91 +-
 llvm/lib/Target/RISCV/RISCVInstrInfo.cpp           |    5 +-
 llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td    |   60 +
 llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp        |    1 +
 llvm/lib/Target/RISCV/RISCVRegisterInfo.td         |    1 +
 llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.cpp |    4 +-
 llvm/lib/Target/VE/VECallingConv.td                |    4 +-
 llvm/lib/Target/VE/VEISelLowering.cpp              |   26 +
 llvm/lib/Target/VE/VEInstrInfo.td                  |    4 +
 .../WebAssemblyLowerEmscriptenEHSjLj.cpp           |    2 +-
 .../AggressiveInstCombine.cpp                      |   71 +-
 llvm/lib/Transforms/IPO/IROutliner.cpp             |    4 +-
 .../Instrumentation/PGOInstrumentation.cpp         |    3 -
 llvm/lib/Transforms/Vectorize/LoopVectorize.cpp    |   30 +-
 llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp    |   12 +-
 llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h    |    4 +-
 llvm/lib/Transforms/Vectorize/VPlan.cpp            |   48 +-
 llvm/lib/Transforms/Vectorize/VPlan.h              |  204 +-
 llvm/lib/Transforms/Vectorize/VPlanValue.h         |   35 +-
 llvm/runtimes/CMakeLists.txt                       |    3 +
 llvm/test/Analysis/BasicAA/noalias-param.ll        |   19 +-
 .../AMDGPU/GlobalISel/lds-zero-initializer.ll      |    4 +-
 llvm/test/CodeGen/AMDGPU/fast-regalloc-bundles.mir |   26 +
 llvm/test/CodeGen/AMDGPU/lds-initializer.ll        |    4 +-
 llvm/test/CodeGen/AMDGPU/lds-zero-initializer.ll   |    4 +-
 .../llvm.amdgcn.ds.gws.barrier-fastregalloc.ll     |   19 +
 llvm/test/CodeGen/PowerPC/aix-cc-abi.ll            |    2 +-
 llvm/test/CodeGen/PowerPC/arr-fp-arg-no-copy.ll    |    4 +-
 llvm/test/CodeGen/PowerPC/bperm.ll                 |   26 +-
 llvm/test/CodeGen/PowerPC/combine_ext_trunc.ll     |   11 +-
 llvm/test/CodeGen/PowerPC/constants-i64.ll         |  145 +-
 llvm/test/CodeGen/PowerPC/f128-fma.ll              |    8 +-
 llvm/test/CodeGen/PowerPC/f128-passByValue.ll      |    4 +-
 llvm/test/CodeGen/PowerPC/fast-isel-pcrel.ll       |    6 +-
 llvm/test/CodeGen/PowerPC/fp-strict-f128.ll        |    6 +-
 llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll       |    8 +-
 .../PowerPC/fp128-bitcast-after-operation.ll       |   12 +-
 llvm/test/CodeGen/PowerPC/funnel-shift.ll          |   12 +-
 .../CodeGen/PowerPC/machinelicm-cse-dead-flag.mir  |   84 +
 .../PowerPC/memCmpUsedInZeroEqualityComparison.ll  |    8 +-
 llvm/test/CodeGen/PowerPC/negctr.ll                |    7 +-
 llvm/test/CodeGen/PowerPC/ori_imm32.ll             |    2 +-
 llvm/test/CodeGen/PowerPC/ori_imm64.ll             |    9 +-
 llvm/test/CodeGen/PowerPC/pr43976.ll               |    2 +-
 llvm/test/CodeGen/PowerPC/pr45448.ll               |    5 +-
 .../rematerializable-instruction-machine-licm.ll   |  147 +-
 llvm/test/CodeGen/PowerPC/sat-register-clobber.ll  |   43 +
 llvm/test/CodeGen/PowerPC/sms-grp-order.ll         |   36 +-
 llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll       |   72 +-
 .../PowerPC/tailcall-speculatable-callee.ll        |    6 +-
 .../CodeGen/PowerPC/unaligned-addressing-mode.ll   |    5 +-
 llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll       |   56 +-
 llvm/test/CodeGen/RISCV/mul.ll                     |  410 ++++
 llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll          | 1441 ++++++++++++
 llvm/test/CodeGen/RISCV/rvv/vaadd-rv64.ll          | 1761 +++++++++++++++
 llvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll         | 1441 ++++++++++++
 llvm/test/CodeGen/RISCV/rvv/vaaddu-rv64.ll         | 1761 +++++++++++++++
 llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll          | 1441 ++++++++++++
 llvm/test/CodeGen/RISCV/rvv/vasub-rv64.ll          | 1761 +++++++++++++++
 llvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll         | 1441 ++++++++++++
 llvm/test/CodeGen/RISCV/rvv/vasubu-rv64.ll         | 1761 +++++++++++++++
 llvm/test/CodeGen/RISCV/rvv/vnclip-rv32.ll         | 1189 ++++++++++
 llvm/test/CodeGen/RISCV/rvv/vnclip-rv64.ll         | 1621 +++++++++++++
 llvm/test/CodeGen/RISCV/rvv/vnclipu-rv32.ll        | 1189 ++++++++++
 llvm/test/CodeGen/RISCV/rvv/vnclipu-rv64.ll        | 1621 +++++++++++++
 llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll          | 1441 ++++++++++++
 llvm/test/CodeGen/RISCV/rvv/vsmul-rv64.ll          | 1761 +++++++++++++++
 llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll          | 1945 ++++++++++++++++
 llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll          | 2377 ++++++++++++++++++++
 llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll          | 1945 ++++++++++++++++
 llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll          | 2377 ++++++++++++++++++++
 llvm/test/CodeGen/Thumb2/mve-vecreduce-add.ll      |  516 +++++
 llvm/test/CodeGen/Thumb2/mve-vecreduce-addpred.ll  |  575 +++++
 llvm/test/CodeGen/Thumb2/mve-vecreduce-mla.ll      |  447 ++++
 llvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll  |  738 ++++++
 llvm/test/CodeGen/VE/Scalar/lea-opt.ll             |   63 +
 llvm/test/CodeGen/VE/Scalar/returnaddr.ll          |   91 +
 llvm/test/CodeGen/VE/Scalar/stacksave.ll           |   26 +
 llvm/test/CodeGen/VE/Vector/fastcc_callee.ll       |    8 +
 llvm/test/CodeGen/X86/equiv_with_vardef.ll         |    5 +-
 llvm/test/CodeGen/X86/statepoint-vreg-invoke.ll    |   45 +-
 llvm/test/CodeGen/XCore/section-name.ll            |    4 +-
 llvm/test/MC/AMDGPU/flat-gfx9.s                    |    1 -
 llvm/test/MC/AMDGPU/flat-global.s                  |    1 -
 llvm/test/MC/AMDGPU/flat.s                         |    6 -
 llvm/test/MC/AMDGPU/fma-mix.s                      |    4 -
 llvm/test/MC/AMDGPU/literal16.s                    |    1 +
 llvm/test/MC/AMDGPU/mad-mix.s                      |    4 -
 llvm/test/MC/AMDGPU/smem.s                         |    1 -
 llvm/test/MC/AMDGPU/vop1-gfx9-err.s                |    1 -
 llvm/test/MC/AMDGPU/vop1.s                         |    2 +-
 llvm/test/MC/AsmParser/align_invalid.s             |    4 +
 llvm/test/MC/AsmParser/directive_ascii.s           |    8 +
 llvm/test/MC/Disassembler/AMDGPU/vop3_gfx9.txt     |    2 +-
 llvm/test/MC/Disassembler/AMDGPU/vop3_vi.txt       |    2 +-
 llvm/test/MC/ELF/basic-elf-32.s                    |    4 +-
 llvm/test/MC/ELF/compression.s                     |    4 +-
 llvm/test/MC/ELF/invalid-symver.s                  |    7 -
 llvm/test/MC/ELF/multiple-different-symver.s       |    6 -
 llvm/test/MC/ELF/multiple-equiv-symver.s           |    6 -
 llvm/test/MC/ELF/relocation-386.s                  |    5 +-
 llvm/test/MC/ELF/symver-err.s                      |   12 +
 llvm/test/MC/Mips/elf-relsym.s                     |   10 +-
 llvm/test/MC/Mips/xgot.s                           |    4 +-
 llvm/test/Reduce/remove-alias.ll                   |    3 +-
 .../Transforms/AggressiveInstCombine/funnel.ll     |  118 +-
 .../Transforms/AggressiveInstCombine/rotate.ll     |   11 +-
 llvm/test/Transforms/InstSimplify/AndOrXor.ll      |  324 ++-
 .../test/Transforms/LoopVectorize/X86/reg-usage.ll |    4 +-
 llvm/unittests/Transforms/Vectorize/VPlanTest.cpp  |   57 +-
 llvm/utils/TableGen/OptParserEmitter.cpp           |   41 +-
 mlir/docs/SPIRVToLLVMDialectConversion.md          |   53 +-
 mlir/include/mlir/Dialect/Vector/VectorOps.h       |    2 +-
 mlir/include/mlir/Dialect/Vector/VectorOps.td      |   65 +-
 mlir/include/mlir/Dialect/Vector/VectorUtils.h     |    4 +-
 mlir/include/mlir/Interfaces/VectorInterfaces.td   |   28 +-
 .../StandardToSPIRV/LegalizeStandardForSPIRV.cpp   |   16 +-
 .../VectorToLLVM/ConvertVectorToLLVM.cpp           |   46 +-
 .../lib/Conversion/VectorToROCDL/VectorToROCDL.cpp |    6 +-
 mlir/lib/Conversion/VectorToSCF/VectorToSCF.cpp    |   41 +-
 mlir/lib/Dialect/Linalg/Transforms/Hoisting.cpp    |    4 +-
 .../Dialect/Linalg/Transforms/Vectorization.cpp    |    4 +-
 mlir/lib/Dialect/Vector/VectorOps.cpp              |  154 +-
 .../Dialect/Vector/VectorTransferOpTransforms.cpp  |    4 +-
 mlir/lib/Dialect/Vector/VectorTransforms.cpp       |   47 +-
 mlir/lib/Dialect/Vector/VectorUtils.cpp            |   12 +-
 mlir/test/Dialect/Vector/invalid.mlir              |   12 +-
 mlir/test/Dialect/Vector/ops.mlir                  |   48 +
 188 files changed, 35910 insertions(+), 1922 deletions(-)
 create mode 100644 clang/test/CodeGen/new-pass-manager-opt-bisect.c
 delete mode 100644 lld/test/ELF/Inputs/i386-static-tls-model4.s
 delete mode 100644 lld/test/ELF/x86-64-reloc-tpoff32-fpic.s
 delete mode 100644 lld/test/MachO/invalid/order-file-bad-arch.test
 delete mode 100644 lld/test/MachO/invalid/order-file-bad-objfile.test
 create mode 100644 llvm/test/CodeGen/AMDGPU/fast-regalloc-bundles.mir
 create mode 100644 llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier-fastregalloc.ll
 create mode 100644 llvm/test/CodeGen/PowerPC/machinelicm-cse-dead-flag.mir
 create mode 100644 llvm/test/CodeGen/PowerPC/sat-register-clobber.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vaadd-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vaaddu-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vasub-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vasubu-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vnclip-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vnclip-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vnclipu-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vnclipu-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vsmul-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll
 create mode 100644 llvm/test/CodeGen/VE/Scalar/lea-opt.ll
 create mode 100644 llvm/test/CodeGen/VE/Scalar/returnaddr.ll
 create mode 100644 llvm/test/CodeGen/VE/Scalar/stacksave.ll
 delete mode 100644 llvm/test/MC/ELF/invalid-symver.s
 delete mode 100644 llvm/test/MC/ELF/multiple-different-symver.s
 delete mode 100644 llvm/test/MC/ELF/multiple-equiv-symver.s
 create mode 100644 llvm/test/MC/ELF/symver-err.s
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[Tcwg-commits] [toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-allnoconfig updated (3285ee143b7 -> 8ab5770a17f)