[Tcwg-commits] [gcc] branch master updated (d9f3ea61fe3 -> 6ae5565e78c)

8 Aug 2023


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unknown user pushed a change to branch master
in repository gcc.
from  d9f3ea61fe3 tree-optimization/49955 - BB reduction with odd number of lanes
       new  6ae5565e78c RISC-V: Support CALL conditional autovec patterns
The 1 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails.  The revisions
listed as "adds" were already present in the repository and have only
been added to this reference.
Summary of changes:
 gcc/config/riscv/autovec.md                        | 279 +++++++++++++
 gcc/config/riscv/riscv-protos.h                    |   5 +
 gcc/config/riscv/riscv-v.cc                        | 152 ++++++-
 gcc/config/riscv/riscv.cc                          |   2 +-
 gcc/config/riscv/vector.md                         | 440 +++++++--------------
 .../riscv/rvv/autovec/cond/cond_arith-1.c          |  48 +++
 .../riscv/rvv/autovec/cond/cond_arith-2.c          |  27 ++
 .../riscv/rvv/autovec/cond/cond_arith-3.c          |  55 +++
 .../riscv/rvv/autovec/cond/cond_arith-4.c          |  21 +
 .../riscv/rvv/autovec/cond/cond_arith-5.c          |  48 +++
 .../riscv/rvv/autovec/cond/cond_arith-6.c          |  27 ++
 .../riscv/rvv/autovec/cond/cond_arith-7.c          |  50 +++
 .../riscv/rvv/autovec/cond/cond_arith-8.c          |  64 +++
 .../{ternop/ternop-6.c => cond/cond_arith-9.c}     |  32 +-
 .../rvv/autovec/cond/cond_arith_run-1.c}           |   6 +-
 .../cond_arith_run-2.c}                            |   4 +-
 .../rvv/autovec/cond/cond_arith_run-3.c}           |   6 +-
 .../cond_arith_run-4.c}                            |   4 +-
 .../rvv/autovec/cond/cond_arith_run-5.c}           |   6 +-
 .../cond_arith_run-6.c}                            |   4 +-
 .../rvv/autovec/cond/cond_arith_run-7.c}           |   6 +-
 .../rvv/autovec/cond/cond_arith_run-8.c}           |   6 +-
 .../rvv/autovec/cond/cond_arith_run-9.c}           |   8 +-
 .../riscv/rvv/autovec/cond/cond_fadd-1.c           |  33 ++
 .../riscv/rvv/autovec/cond/cond_fadd-2.c           |  32 ++
 .../riscv/rvv/autovec/cond/cond_fadd-3.c           |  33 ++
 .../riscv/rvv/autovec/cond/cond_fadd-4.c           |  33 ++
 .../rvv/autovec/cond/cond_fadd_run-1.c}            |   6 +-
 .../rvv/autovec/cond/cond_fadd_run-2.c}            |   6 +-
 .../rvv/autovec/cond/cond_fadd_run-3.c}            |   6 +-
 .../rvv/autovec/cond/cond_fadd_run-4.c}            |   6 +-
 .../riscv/rvv/autovec/cond/cond_fma_fnma-1.c       |  35 ++
 .../riscv/rvv/autovec/cond/cond_fma_fnma-2.c       |  35 ++
 .../riscv/rvv/autovec/cond/cond_fma_fnma-3.c       |  35 ++
 .../riscv/rvv/autovec/cond/cond_fma_fnma-4.c       |  35 ++
 .../riscv/rvv/autovec/cond/cond_fma_fnma-5.c       |  35 ++
 .../riscv/rvv/autovec/cond/cond_fma_fnma-6.c       |  35 ++
 .../riscv/rvv/autovec/cond/cond_fma_fnma-7.c       |  35 ++
 .../riscv/rvv/autovec/cond/cond_fma_fnma-8.c       |  35 ++
 .../rvv/autovec/cond/cond_fma_fnma_run-1.c}        |   6 +-
 .../rvv/autovec/cond/cond_fma_fnma_run-2.c}        |   6 +-
 .../rvv/autovec/cond/cond_fma_fnma_run-3.c}        |   6 +-
 .../rvv/autovec/cond/cond_fma_fnma_run-4.c}        |   6 +-
 .../rvv/autovec/cond/cond_fma_fnma_run-5.c}        |   6 +-
 .../rvv/autovec/cond/cond_fma_fnma_run-6.c}        |   6 +-
 .../rvv/autovec/cond/cond_fma_fnma_run-7.c}        |   6 +-
 .../rvv/autovec/cond/cond_fma_fnma_run-8.c}        |   6 +-
 .../riscv/rvv/autovec/cond/cond_fmax-1.c           |  33 ++
 .../riscv/rvv/autovec/cond/cond_fmax-2.c           |  32 ++
 .../riscv/rvv/autovec/cond/cond_fmax-3.c           |  33 ++
 .../riscv/rvv/autovec/cond/cond_fmax-4.c           |  33 ++
 .../rvv/autovec/cond/cond_fmax_run-1.c}            |   6 +-
 .../rvv/autovec/cond/cond_fmax_run-2.c}            |   6 +-
 .../rvv/autovec/cond/cond_fmax_run-3.c}            |   6 +-
 .../rvv/autovec/cond/cond_fmax_run-4.c}            |   6 +-
 .../riscv/rvv/autovec/cond/cond_fmin-1.c           |  10 +
 .../riscv/rvv/autovec/cond/cond_fmin-2.c           |   9 +
 .../riscv/rvv/autovec/cond/cond_fmin-3.c           |   9 +
 .../riscv/rvv/autovec/cond/cond_fmin-4.c           |   9 +
 .../ternop_nofm_run-3.c => cond/cond_fmin_run-1.c} |   5 +-
 .../ternop_nofm_run-3.c => cond/cond_fmin_run-2.c} |   5 +-
 .../ternop_nofm_run-3.c => cond/cond_fmin_run-3.c} |   5 +-
 .../ternop_nofm_run-3.c => cond/cond_fmin_run-4.c} |   5 +-
 .../riscv/rvv/autovec/cond/cond_fms_fnms-1.c       |  29 ++
 .../riscv/rvv/autovec/cond/cond_fms_fnms-2.c       |  29 ++
 .../riscv/rvv/autovec/cond/cond_fms_fnms-3.c       |  29 ++
 .../riscv/rvv/autovec/cond/cond_fms_fnms-4.c       |  29 ++
 .../riscv/rvv/autovec/cond/cond_fms_fnms-5.c       |  29 ++
 .../riscv/rvv/autovec/cond/cond_fms_fnms-6.c       |  29 ++
 .../rvv/autovec/cond/cond_fms_fnms_run-1.c}        |   8 +-
 .../rvv/autovec/cond/cond_fms_fnms_run-2.c}        |   8 +-
 .../rvv/autovec/cond/cond_fms_fnms_run-3.c}        |   8 +-
 .../rvv/autovec/cond/cond_fms_fnms_run-4.c}        |   8 +-
 .../rvv/autovec/cond/cond_fms_fnms_run-5.c}        |   8 +-
 .../rvv/autovec/cond/cond_fms_fnms_run-6.c}        |   8 +-
 .../riscv/rvv/autovec/cond/cond_fmul-1.c           |  29 ++
 .../riscv/rvv/autovec/cond/cond_fmul-2.c           |  28 ++
 .../riscv/rvv/autovec/cond/cond_fmul-3.c           |  29 ++
 .../riscv/rvv/autovec/cond/cond_fmul-4.c           |  29 ++
 .../rvv/autovec/cond/cond_fmul_run-1.c}            |   6 +-
 .../rvv/autovec/cond/cond_fmul_run-2.c}            |   6 +-
 .../rvv/autovec/cond/cond_fmul_run-3.c}            |   6 +-
 .../rvv/autovec/cond/cond_fmul_run-4.c}            |   6 +-
 .../riscv/rvv/autovec/cond/cond_logical-1.c        |  43 ++
 .../riscv/rvv/autovec/cond/cond_logical-2.c        |  43 ++
 .../riscv/rvv/autovec/cond/cond_logical-3.c        |  43 ++
 .../riscv/rvv/autovec/cond/cond_logical-4.c        |  43 ++
 .../riscv/rvv/autovec/cond/cond_logical-5.c        |  43 ++
 .../rvv/autovec/cond/cond_logical_run-1.c}         |   6 +-
 .../rvv/autovec/cond/cond_logical_run-2.c}         |   6 +-
 .../rvv/autovec/cond/cond_logical_run-3.c}         |   6 +-
 .../rvv/autovec/cond/cond_logical_run-4.c}         |   6 +-
 .../rvv/autovec/cond/cond_logical_run-5.c}         |   6 +-
 .../riscv/rvv/autovec/cond/cond_shift-1.c          |  33 ++
 .../riscv/rvv/autovec/cond/cond_shift-2.c          |  33 ++
 .../riscv/rvv/autovec/cond/cond_shift-3.c          |  33 ++
 .../riscv/rvv/autovec/cond/cond_shift-4.c          |  33 ++
 .../riscv/rvv/autovec/cond/cond_shift-5.c          |  29 ++
 .../rvv/autovec/cond/cond_shift-6.c}               |  16 +-
 .../riscv/rvv/autovec/cond/cond_shift-7.c          |  29 ++
 .../riscv/rvv/autovec/cond/cond_shift-8.c          |  29 ++
 .../riscv/rvv/autovec/cond/cond_shift-9.c          |  29 ++
 .../rvv/autovec/cond/cond_shift_run-1.c}           |   6 +-
 .../rvv/autovec/cond/cond_shift_run-2.c}           |   7 +-
 .../rvv/autovec/cond/cond_shift_run-3.c}           |   6 +-
 .../rvv/autovec/cond/cond_shift_run-4.c}           |   6 +-
 .../rvv/autovec/cond/cond_shift_run-5.c}           |   6 +-
 .../rvv/autovec/cond/cond_shift_run-6.c}           |   6 +-
 .../rvv/autovec/cond/cond_shift_run-7.c}           |   6 +-
 .../rvv/autovec/cond/cond_shift_run-8.c}           |   6 +-
 .../rvv/autovec/cond/cond_shift_run-9.c}           |   6 +-
 .../riscv/rvv/autovec/reduc/reduc_call-1.c         |  12 +
 .../riscv/rvv/autovec/reduc/reduc_call-2.c         |   6 +
 .../riscv/rvv/autovec/reduc/reduc_call-3.c         |   6 +
 .../riscv/rvv/autovec/reduc/reduc_call-4.c         |   6 +
 .../riscv/rvv/autovec/reduc/reduc_call-5.c         |  16 +
 gcc/testsuite/gcc.target/riscv/rvv/rvv.exp         |   2 +
 117 files changed, 2472 insertions(+), 496 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{ternop/ternop-6.c => cond/cond_ar [...]
 copy gcc/testsuite/gcc.target/{aarch64/sve/cond_arith_1_run.c => riscv/rvv/autovec [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{ternop/ternop_nofm_run-3.c => con [...]
 copy gcc/testsuite/gcc.target/{aarch64/sve/cond_arith_2_run.c => riscv/rvv/autovec [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{ternop/ternop_nofm_run-3.c => con [...]
 copy gcc/testsuite/gcc.target/{aarch64/sve/cond_arith_3_run.c => riscv/rvv/autovec [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{ternop/ternop_nofm_run-3.c => con [...]
 copy gcc/testsuite/gcc.target/{aarch64/sve/cond_arith_4_run.c => riscv/rvv/autovec [...]
 copy gcc/testsuite/gcc.target/{aarch64/sve/cond_arith_5_run.c => riscv/rvv/autovec [...]
 copy gcc/testsuite/gcc.target/{aarch64/sve/cond_arith_1_run.c => riscv/rvv/autovec [...]
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c
 copy gcc/testsuite/gcc.target/{aarch64/sve/cond_fadd_1_run.c => riscv/rvv/autovec/ [...]
 copy gcc/testsuite/gcc.target/{aarch64/sve/cond_fadd_2_run.c => riscv/rvv/autovec/ [...]
 copy gcc/testsuite/gcc.target/{aarch64/sve/cond_fadd_3_run.c => riscv/rvv/autovec/ [...]
 copy gcc/testsuite/gcc.target/{aarch64/sve/cond_fadd_4_run.c => riscv/rvv/autovec/ [...]
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-7.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-8.c
 copy gcc/testsuite/gcc.target/{aarch64/sve/cond_mla_1_run.c => riscv/rvv/autovec/c [...]
 copy gcc/testsuite/gcc.target/{aarch64/sve/cond_mla_2_run.c => riscv/rvv/autovec/c [...]
 copy gcc/testsuite/gcc.target/{aarch64/sve/cond_mla_3_run.c => riscv/rvv/autovec/c [...]
 copy gcc/testsuite/gcc.target/{aarch64/sve/cond_mla_4_run.c => riscv/rvv/autovec/c [...]
 copy gcc/testsuite/gcc.target/{aarch64/sve/cond_mla_5_run.c => riscv/rvv/autovec/c [...]
 copy gcc/testsuite/gcc.target/{aarch64/sve/cond_mla_6_run.c => riscv/rvv/autovec/c [...]
 copy gcc/testsuite/gcc.target/{aarch64/sve/cond_mla_7_run.c => riscv/rvv/autovec/c [...]
 copy gcc/testsuite/gcc.target/{aarch64/sve/cond_mla_8_run.c => riscv/rvv/autovec/c [...]
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c
 copy gcc/testsuite/gcc.target/{aarch64/sve/cond_fmaxnm_1_run.c => riscv/rvv/autove [...]
 copy gcc/testsuite/gcc.target/{aarch64/sve/cond_fmaxnm_2_run.c => riscv/rvv/autove [...]
 copy gcc/testsuite/gcc.target/{aarch64/sve/cond_fmaxnm_3_run.c => riscv/rvv/autove [...]
 copy gcc/testsuite/gcc.target/{aarch64/sve/cond_fmaxnm_4_run.c => riscv/rvv/autove [...]
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{ternop/ternop_nofm_run-3.c => con [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{ternop/ternop_nofm_run-3.c => con [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{ternop/ternop_nofm_run-3.c => con [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{ternop/ternop_nofm_run-3.c => con [...]
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c
 copy gcc/testsuite/gcc.target/{aarch64/sve/cond_mla_1_run.c => riscv/rvv/autovec/c [...]
 copy gcc/testsuite/gcc.target/{aarch64/sve/cond_mla_2_run.c => riscv/rvv/autovec/c [...]
 copy gcc/testsuite/gcc.target/{aarch64/sve/cond_mla_1_run.c => riscv/rvv/autovec/c [...]
 copy gcc/testsuite/gcc.target/{aarch64/sve/cond_mla_4_run.c => riscv/rvv/autovec/c [...]
 copy gcc/testsuite/gcc.target/{aarch64/sve/cond_mla_1_run.c => riscv/rvv/autovec/c [...]
 copy gcc/testsuite/gcc.target/{aarch64/sve/cond_mla_1_run.c => riscv/rvv/autovec/c [...]
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c
 copy gcc/testsuite/gcc.target/{aarch64/sve/cond_fmul_1_run.c => riscv/rvv/autovec/ [...]
 copy gcc/testsuite/gcc.target/{aarch64/sve/cond_fmul_2_run.c => riscv/rvv/autovec/ [...]
 copy gcc/testsuite/gcc.target/{aarch64/sve/cond_fmul_3_run.c => riscv/rvv/autovec/ [...]
 copy gcc/testsuite/gcc.target/{aarch64/sve/cond_fmul_4_run.c => riscv/rvv/autovec/ [...]
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical-5.c
 copy gcc/testsuite/gcc.target/{aarch64/sve/cond_logical_1_run.c => riscv/rvv/autov [...]
 copy gcc/testsuite/gcc.target/{aarch64/sve/cond_logical_2_run.c => riscv/rvv/autov [...]
 copy gcc/testsuite/gcc.target/{aarch64/sve/cond_logical_3_run.c => riscv/rvv/autov [...]
 copy gcc/testsuite/gcc.target/{aarch64/sve/cond_logical_4_run.c => riscv/rvv/autov [...]
 copy gcc/testsuite/gcc.target/{aarch64/sve/cond_logical_5_run.c => riscv/rvv/autov [...]
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-5.c
 copy gcc/testsuite/gcc.target/{aarch64/sve/cond_shift_6.c => riscv/rvv/autovec/con [...]
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-7.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_shift-9.c
 copy gcc/testsuite/gcc.target/{aarch64/sve/cond_shift_1_run.c => riscv/rvv/autovec [...]
 copy gcc/testsuite/gcc.target/{aarch64/sve/cond_shift_2_run.c => riscv/rvv/autovec [...]
 copy gcc/testsuite/gcc.target/{gcn/cond_shift_3_run.c => riscv/rvv/autovec/cond/co [...]
 copy gcc/testsuite/gcc.target/{gcn/cond_shift_4_run.c => riscv/rvv/autovec/cond/co [...]
 copy gcc/testsuite/gcc.target/{aarch64/sve/cond_shift_5_run.c => riscv/rvv/autovec [...]
 copy gcc/testsuite/gcc.target/{aarch64/sve/cond_shift_6_run.c => riscv/rvv/autovec [...]
 copy gcc/testsuite/gcc.target/{aarch64/sve/cond_shift_7_run.c => riscv/rvv/autovec [...]
 copy gcc/testsuite/gcc.target/{gcn/cond_shift_8_run.c => riscv/rvv/autovec/cond/co [...]
 copy gcc/testsuite/gcc.target/{aarch64/sve/cond_shift_9_run.c => riscv/rvv/autovec [...]
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-5.c
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[Tcwg-commits] [gcc] branch master updated (d9f3ea61fe3 -> 6ae5565e78c)