This is an automated email from the git hooks/post-receive script.
tcwg-benchmark pushed a change to branch linaro-local/ci/tcwg_bmk_stm32/gnu_eabi-release-arm-eabi-coremark-Os_LTO in repository toolchain/ci/gcc.
from 83a51f1af92 Daily bump. adds ba616f85556 Daily bump. adds e1a08689ce2 Daily bump. adds a27067c70b7 Put PREFETCHW back to march=broadwell adds 6abef270285 Daily bump. adds c52868904b7 PR target/97682 - Fix to reuse t1 register between call add [...] adds 9d65095e725 AArch64: Fix overflow in memcopy expansion on aarch64. adds 7e785f4c764 AArch64: Skip test for pr97535 on ILP32 since it can't expr [...]
No new revisions were added by this update.
Summary of changes: gcc/ChangeLog | 5 + gcc/DATESTAMP | 2 +- gcc/config/aarch64/aarch64.c | 13 ++- gcc/config/i386/i386.h | 3 +- gcc/config/riscv/riscv.c | 23 ++-- gcc/config/riscv/riscv.h | 6 +- gcc/doc/invoke.texi | 25 +++-- gcc/testsuite/g++.target/riscv/pr97682.C | 160 +++++++++++++++++++++++++++ gcc/testsuite/gcc.target/aarch64/pr97535.c | 16 +++ gcc/testsuite/gcc.target/riscv/interrupt-3.c | 4 +- gcc/testsuite/gcc.target/riscv/interrupt-4.c | 4 +- 11 files changed, 227 insertions(+), 34 deletions(-) create mode 100644 gcc/testsuite/g++.target/riscv/pr97682.C create mode 100644 gcc/testsuite/gcc.target/aarch64/pr97535.c