[Tcwg-commits] [toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-next-defconfig updated (efeb50197091 -> 21dad9a52207)

16 Jan 2022


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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-next-defconfig
in repository toolchain/ci/llvm-project.
from  efeb50197091 [cmake] Use `GNUInstallDirs` to support custom installation dirs.
      adds  0f93448235fe enable noundef analysis with -fsanitize-memory-param-retval
      adds  a0a76fee0cf8 [RISCV] update zfh and zfhmin extention to v1.0
      adds  0a46b6ec4e47 [msan] Clear byval shadow in ignored functions
      adds  ea6c8b013e48 [BOLT][DWARF] Reduce overhead for sized dealloc
      adds  b148348ad486 [RISCV] Add patterns for vector widening integer add/subtract
      adds  a8ca4046e22d [LSR] Fix crash in Phi node with EHPad block
      adds  4cc514579f46 [NFCI][CMake] add space among flag sets in all_linker_flag [...]
      adds  0f499d1ed4a1 Revert "[X86][LLD] Update datelayout in LLD tests. NFCI"
      adds  f63a805a4e99 Revert "[X86][MS] Change the alignment of f80 to 16 bytes  [...]
      adds  21dad9a52207 [RISCV][NFC] Add IsRV64 predicate in xperm.w pattern
No new revisions were added by this update.
Summary of changes:
 bolt/include/bolt/Core/DebugData.h                 |  37 +-
 bolt/lib/Core/DebugData.cpp                        |  31 +-
 clang/include/clang/Driver/Options.td              |  16 +-
 clang/lib/Basic/Targets/X86.h                      |  11 +-
 .../CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c |   3 +-
 .../RISCV/rvv-intrinsics-overloaded/vfadd.c        |   2 +-
 .../RISCV/rvv-intrinsics-overloaded/vlseg.c        |   4 +-
 .../RISCV/rvv-intrinsics-overloaded/vlsegff.c      |   4 +-
 .../CodeGen/RISCV/rvv-intrinsics-overloaded/vnot.c |   3 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vadd.c     |   3 +-
 .../test/CodeGen/RISCV/rvv-intrinsics/vcompress.c  |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vfabs.c    |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vfadd.c    |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vfclass.c  |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vfcvt.c    |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vfdiv.c    |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vfmacc.c   |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vfmadd.c   |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vfmax.c    |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vfmerge.c  |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vfmin.c    |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsac.c   |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsub.c   |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vfmul.c    |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vfmv.c     |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vfncvt.c   |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vfneg.c    |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmacc.c  |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmadd.c  |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsac.c  |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsub.c  |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vfrdiv.c   |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vfrec7.c   |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vfredmax.c |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vfredmin.c |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vfredsum.c |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vfrsqrt7.c |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vfrsub.c   |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vfsgnj.c   |   2 +-
 .../CodeGen/RISCV/rvv-intrinsics/vfslide1down.c    |   2 +-
 .../test/CodeGen/RISCV/rvv-intrinsics/vfslide1up.c |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vfsqrt.c   |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vfsub.c    |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vfwadd.c   |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vfwcvt.c   |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmacc.c  |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmsac.c  |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmul.c   |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmacc.c |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmsac.c |   2 +-
 .../test/CodeGen/RISCV/rvv-intrinsics/vfwredsum.c  |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vfwsub.c   |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vget.c     |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vle.c      |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vleff.c    |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vlmul.c    |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vloxei.c   |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg.c  |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vlse.c     |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c    |   4 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c  |   4 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg.c   |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vluxei.c   |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg.c  |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vmerge.c   |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vmfeq.c    |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vmfge.c    |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vmfgt.c    |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vmfle.c    |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vmflt.c    |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vmfne.c    |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vmv.c      |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vnot.c     |   3 +-
 .../CodeGen/RISCV/rvv-intrinsics/vreinterpret.c    |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vrgather.c |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vse.c      |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vset.c     |   2 +-
 .../test/CodeGen/RISCV/rvv-intrinsics/vslidedown.c |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vslideup.c |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vsoxei.c   |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vsoxseg.c  |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vsse.c     |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vsseg.c    |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vssseg.c   |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vsuxei.c   |   2 +-
 clang/test/CodeGen/RISCV/rvv-intrinsics/vsuxseg.c  |   2 +-
 .../test/CodeGen/RISCV/rvv-intrinsics/vundefined.c |   2 +-
 clang/test/CodeGen/attr-noundef.cpp                |   6 +
 clang/test/CodeGen/indirect-noundef.cpp            |   5 +
 clang/test/CodeGen/msan-param-retval.c             |   2 +-
 clang/test/CodeGen/target-data.c                   |   2 +-
 clang/test/Driver/riscv-arch.c                     |  18 -
 clang/test/Preprocessor/riscv-target-features.c    |  18 +-
 compiler-rt/test/msan/noundef_analysis.cpp         |   2 +
 lld/test/COFF/libcall-archive.ll                   |   2 +-
 lld/test/COFF/lto-lazy-reference.ll                |   2 +-
 lld/test/COFF/lto-reloc-model.ll                   |   2 +-
 llvm/cmake/modules/HandleLLVMOptions.cmake         |  10 +-
 llvm/lib/IR/AutoUpgrade.cpp                        |  19 +-
 llvm/lib/Support/RISCVISAInfo.cpp                  |   6 +-
 llvm/lib/Target/RISCV/RISCV.td                     |   4 +-
 llvm/lib/Target/RISCV/RISCVInstrInfo.td            |  12 +
 llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td |  34 ++
 llvm/lib/Target/RISCV/RISCVInstrInfoZb.td          |   4 +-
 llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td         |   6 +-
 llvm/lib/Target/X86/X86TargetMachine.cpp           |   2 +-
 .../Transforms/Instrumentation/MemorySanitizer.cpp |  10 +-
 llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp  |  25 ++
 .../CostModel/RISCV/fixed-vector-gather.ll         |   2 +-
 .../CostModel/RISCV/fixed-vector-scatter.ll        |   2 +-
 llvm/test/Bitcode/upgrade-datalayout3.ll           |   2 +-
 llvm/test/CodeGen/RISCV/attributes.ll              |  20 +-
 llvm/test/CodeGen/RISCV/calling-conv-half.ll       |   4 +-
 llvm/test/CodeGen/RISCV/copysign-casts.ll          |   6 +-
 llvm/test/CodeGen/RISCV/half-arith-strict.ll       |   4 +-
 llvm/test/CodeGen/RISCV/half-arith.ll              |   4 +-
 .../CodeGen/RISCV/half-bitmanip-dagcombines.ll     |   4 +-
 llvm/test/CodeGen/RISCV/half-br-fcmp.ll            |   4 +-
 llvm/test/CodeGen/RISCV/half-convert-strict.ll     |   8 +-
 llvm/test/CodeGen/RISCV/half-convert.ll            |   8 +-
 llvm/test/CodeGen/RISCV/half-fcmp-strict.ll        |   4 +-
 llvm/test/CodeGen/RISCV/half-fcmp.ll               |   8 +-
 llvm/test/CodeGen/RISCV/half-frem.ll               |   4 +-
 llvm/test/CodeGen/RISCV/half-imm.ll                |   4 +-
 llvm/test/CodeGen/RISCV/half-intrinsics.ll         |   8 +-
 llvm/test/CodeGen/RISCV/half-isnan.ll              |   4 +-
 llvm/test/CodeGen/RISCV/half-mem.ll                |   4 +-
 llvm/test/CodeGen/RISCV/half-round-conv.ll         |   4 +-
 llvm/test/CodeGen/RISCV/half-select-fcmp.ll        |   4 +-
 .../CodeGen/RISCV/inline-asm-zfh-constraint-f.ll   |   8 +-
 .../CodeGen/RISCV/rv64zfh-half-convert-strict.ll   |   2 +-
 llvm/test/CodeGen/RISCV/rv64zfh-half-convert.ll    |   2 +-
 .../RISCV/rv64zfh-half-intrinsics-strict.ll        |   4 +-
 llvm/test/CodeGen/RISCV/rv64zfh-half-intrinsics.ll |   4 +-
 llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll  |   4 +-
 llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll   |   4 +-
 llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll  |   3 +-
 llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll  |   3 +-
 llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll |   3 +-
 llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll |   3 +-
 llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll        |   4 +-
 llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll       |   4 +-
 .../CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll     |   8 +-
 .../RISCV/rvv/fixed-vectors-calling-conv.ll        |   8 +-
 .../RISCV/rvv/fixed-vectors-extload-truncstore.ll  |   8 +-
 .../CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll  |   4 +-
 .../CodeGen/RISCV/rvv/fixed-vectors-extract.ll     |   5 +-
 .../CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll  |   4 +-
 .../CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll |   8 +-
 .../CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll     |   8 +-
 .../CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll    |   4 +-
 .../CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll |   4 +-
 .../CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll    |   8 +-
 .../CodeGen/RISCV/rvv/fixed-vectors-fp-vrgather.ll |   8 +-
 llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll    |   8 +-
 llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll  |   8 +-
 llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll  |   8 +-
 .../test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll |   4 +-
 .../RISCV/rvv/fixed-vectors-masked-gather.ll       |   4 +-
 .../RISCV/rvv/fixed-vectors-masked-load-fp.ll      |   4 +-
 .../RISCV/rvv/fixed-vectors-masked-scatter.ll      |   4 +-
 .../RISCV/rvv/fixed-vectors-masked-store-fp.ll     |   4 +-
 .../RISCV/rvv/fixed-vectors-reduction-fp-vp.ll     |   4 +-
 .../RISCV/rvv/fixed-vectors-reduction-fp.ll        |   4 +-
 .../CodeGen/RISCV/rvv/fixed-vectors-select-fp.ll   |   4 +-
 .../CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll    |   4 +-
 .../CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll    |   4 +-
 llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax.ll |   4 +-
 llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin.ll |   4 +-
 .../CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll    |   4 +-
 .../CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll   |   4 +-
 .../CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll   |   4 +-
 .../CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll    |   4 +-
 .../CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll    |   4 +-
 .../test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll |   4 +-
 .../CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll   |   4 +-
 .../CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll     |   4 +-
 .../CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll  |   4 +-
 .../CodeGen/RISCV/rvv/fixed-vectors-vselect.ll     |   4 +-
 llvm/test/CodeGen/RISCV/rvv/ftrunc-sdnode.ll       |   4 +-
 llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll    |   4 +-
 llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv32.ll   |   3 +-
 llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv64.ll   |   3 +-
 llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll  |   2 +-
 llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll  |   3 +-
 .../test/CodeGen/RISCV/rvv/legalize-load-sdnode.ll |   4 +-
 .../CodeGen/RISCV/rvv/legalize-store-sdnode.ll     |   4 +-
 llvm/test/CodeGen/RISCV/rvv/masked-load-fp.ll      |   4 +-
 llvm/test/CodeGen/RISCV/rvv/masked-store-fp.ll     |   4 +-
 llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll      |   4 +-
 llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll     |   4 +-
 .../RISCV/rvv/named-vector-shuffle-reverse.ll      |  12 +-
 llvm/test/CodeGen/RISCV/rvv/regalloc-fast-crash.ll |   2 +-
 llvm/test/CodeGen/RISCV/rvv/select-fp.ll           |   4 +-
 llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll       |   2 +-
 llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll       |   2 +-
 .../CodeGen/RISCV/rvv/unaligned-loads-stores.ll    |   4 +-
 llvm/test/CodeGen/RISCV/rvv/undef-vp-ops.ll        |   4 +-
 llvm/test/CodeGen/RISCV/rvv/vcompress-rv32.ll      |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vcompress-rv64.ll      |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll        |   4 +-
 llvm/test/CodeGen/RISCV/rvv/vfadd-rv32.ll          |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfadd-rv64.ll          |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll        |   5 +-
 llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll            |   4 +-
 llvm/test/CodeGen/RISCV/rvv/vfclass-rv32.ll        |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfclass-rv64.ll        |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll   |   4 +-
 llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x-rv32.ll      |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x-rv64.ll      |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu-rv32.ll     |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu-rv64.ll     |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f-rv32.ll  |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f-rv64.ll  |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f-rv32.ll |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f-rv64.ll |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f-rv32.ll      |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f-rv64.ll      |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f-rv32.ll     |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f-rv64.ll     |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfdiv-rv32.ll          |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfdiv-rv64.ll          |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode.ll        |   5 +-
 llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll            |   4 +-
 llvm/test/CodeGen/RISCV/rvv/vfmacc-rv32.ll         |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfmacc-rv64.ll         |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfmadd-rv32.ll         |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfmadd-rv64.ll         |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll       |   4 +-
 llvm/test/CodeGen/RISCV/rvv/vfmax-rv32.ll          |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfmax-rv64.ll          |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfmax-sdnode.ll        |   4 +-
 llvm/test/CodeGen/RISCV/rvv/vfmerge-rv32.ll        |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfmerge-rv64.ll        |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfmin-rv32.ll          |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfmin-rv64.ll          |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfmin-sdnode.ll        |   4 +-
 llvm/test/CodeGen/RISCV/rvv/vfmsac-rv32.ll         |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfmsac-rv64.ll         |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfmsub-rv32.ll         |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfmsub-rv64.ll         |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfmsub-sdnode.ll       |   4 +-
 llvm/test/CodeGen/RISCV/rvv/vfmul-rv32.ll          |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfmul-rv64.ll          |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode.ll        |   5 +-
 llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll            |   4 +-
 llvm/test/CodeGen/RISCV/rvv/vfmv.f.s.ll            |   4 +-
 llvm/test/CodeGen/RISCV/rvv/vfmv.s.f-rv32.ll       |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfmv.s.f-rv64.ll       |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv32.ll       |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv64.ll       |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv32.ll     |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv64.ll     |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv32.ll     |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv64.ll     |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv32.ll    |   2 +-
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 llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv32.ll |   2 +-
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 llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv64.ll |   2 +-
 .../test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv32.ll |   2 +-
 .../test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv64.ll |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv32.ll     |   2 +-
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 llvm/test/CodeGen/RISCV/rvv/vfnmsub-sdnode.ll      |   4 +-
 llvm/test/CodeGen/RISCV/rvv/vfpext-sdnode.ll       |   5 +-
 llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll       |   5 +-
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 llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv32.ll         |   2 +-
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 llvm/test/CodeGen/RISCV/rvv/vfrec7-rv32.ll         |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfrec7-rv64.ll         |   2 +-
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 llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv32.ll        |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv64.ll        |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv32.ll   |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv64.ll   |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll     |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv64.ll     |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfsqrt-rv32.ll         |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfsqrt-rv64.ll         |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfsqrt-sdnode.ll       |   4 +-
 llvm/test/CodeGen/RISCV/rvv/vfsub-rv32.ll          |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfsub-rv64.ll          |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll        |   5 +-
 llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll            |   4 +-
 llvm/test/CodeGen/RISCV/rvv/vfwadd-rv32.ll         |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfwadd-rv64.ll         |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll       |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll       |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv32.ll     |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv64.ll     |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv32.ll     |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv64.ll     |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv32.ll    |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv64.ll    |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv32.ll |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv64.ll |   2 +-
 .../test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv32.ll |   2 +-
 .../test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv64.ll |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv32.ll     |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv64.ll     |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv32.ll    |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv64.ll    |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv32.ll        |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv64.ll        |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv32.ll        |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv64.ll        |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfwmul-rv32.ll         |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfwmul-rv64.ll         |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv32.ll       |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv64.ll       |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv32.ll       |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv64.ll       |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv32.ll     |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv64.ll     |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfwredusum-rv32.ll     |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfwredusum-rv64.ll     |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfwsub-rv32.ll         |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfwsub-rv64.ll         |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll       |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll       |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll       |   5 +-
 llvm/test/CodeGen/RISCV/rvv/vle-rv32.ll            |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vle-rv64.ll            |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vleff-rv32.ll          |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vleff-rv64.ll          |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vloxei-rv32.ll         |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll         |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll        |   3 +-
 llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll        |   3 +-
 llvm/test/CodeGen/RISCV/rvv/vlse-rv32.ll           |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vlse-rv64.ll           |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll          |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll          |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll   |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll        |   3 +-
 llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll   |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll        |   3 +-
 llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll         |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll         |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vluxei-rv32.ll         |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll         |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll        |   3 +-
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 llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll         |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vmerge-rv64.ll         |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vmfeq-rv32.ll          |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll          |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll          |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll          |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll          |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll          |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll          |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll          |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll          |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll          |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll          |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll          |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vmset-rv32.ll          |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vmset-rv64.ll          |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vmv.v.v-rv32.ll        |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vmv.v.v-rv64.ll        |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll     |   4 +-
 llvm/test/CodeGen/RISCV/rvv/vpload.ll              |   4 +-
 llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll    |   4 +-
 llvm/test/CodeGen/RISCV/rvv/vpstore.ll             |   4 +-
 .../CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll     |   4 +-
 llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll   |   4 +-
 llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll       |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll       |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv32.ll   |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv64.ll   |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vse-rv32.ll            |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vse-rv64.ll            |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll     |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll     |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll          |   4 +-
 llvm/test/CodeGen/RISCV/rvv/vslidedown-rv32.ll     |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vslidedown-rv64.ll     |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vslideup-rv32.ll       |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vslideup-rv64.ll       |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vsoxei-rv32.ll         |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vsoxei-rv64.ll         |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll        |   3 +-
 llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll        |   3 +-
 llvm/test/CodeGen/RISCV/rvv/vsplats-fp.ll          |   4 +-
 llvm/test/CodeGen/RISCV/rvv/vsse-rv32.ll           |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vsse-rv64.ll           |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vsseg-rv32.ll          |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vsseg-rv64.ll          |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vssseg-rv32.ll         |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vssseg-rv64.ll         |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vsuxei-rv32.ll         |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vsuxei-rv64.ll         |   2 +-
 llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll        |   3 +-
 llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll        |   3 +-
 llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll        | 427 +++++++++++++++++++++
 llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll     |   2 +-
 llvm/test/CodeGen/RISCV/spill-fpr-scalar.ll        |   2 +-
 .../CodeGen/RISCV/zfh-half-intrinsics-strict.ll    |   8 +-
 llvm/test/CodeGen/RISCV/zfh-half-intrinsics.ll     |   8 +-
 llvm/test/CodeGen/RISCV/zfh-imm.ll                 |   8 +-
 llvm/test/CodeGen/X86/long-double-abi-align.ll     |   4 +-
 llvm/test/CodeGen/X86/scalar-fp-to-i32.ll          | 219 ++++-------
 llvm/test/CodeGen/X86/scalar-fp-to-i64.ll          |  32 +-
 llvm/test/Instrumentation/MemorySanitizer/byval.ll |   6 +-
 llvm/test/MC/RISCV/attribute-arch-invalid.s        |   6 -
 llvm/test/MC/RISCV/attribute-arch.s                |   8 +-
 llvm/test/MC/RISCV/rv32zfh-invalid.s               |   2 +-
 llvm/test/MC/RISCV/rv32zfh-valid.s                 |  12 +-
 llvm/test/MC/RISCV/rv32zfhmin-invalid.s            |   2 +-
 llvm/test/MC/RISCV/rv32zfhmin-valid.s              |  12 +-
 llvm/test/MC/RISCV/rv64zfh-invalid.s               |   2 +-
 llvm/test/MC/RISCV/rv64zfh-valid.s                 |   8 +-
 llvm/test/MC/RISCV/rvzfh-aliases-valid.s           |  24 +-
 llvm/test/MC/RISCV/rvzfh-pseudos.s                 |   4 +-
 .../LoopStrengthReduce/phi_ehpad_ignore_sameval.ll |  55 +++
 llvm/unittests/Bitcode/DataLayoutUpgradeTest.cpp   |   2 +-
 451 files changed, 1370 insertions(+), 915 deletions(-)
 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll
 create mode 100644 llvm/test/Transforms/LoopStrengthReduce/phi_ehpad_ignore_sameval.ll
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[Tcwg-commits] [toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-next-defconfig updated (efeb50197091 -> 21dad9a52207)