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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_check/master-arm in repository toolchain/ci/gcc.
from f907cf4c07c vect: Move suggested_unroll_factor applying [PR105940] adds be6676286a0 Restore bootstrap on ARM adds 90467f0ad64 middle-end/105965 - add missing v_c_e <{ el }> simplification adds e07a876c076 tree-optimization/105946 - avoid accessing excess args from [...] adds 4bf0dcb0492 RISC-V: add consecutive_bits_operand predicate adds 0247ad3e0f4 RISC-V: Split slli+sh[123]add.uw opportunities to avoid zext.w adds 8f6c317b3a1 Fix ipa-cp wrt volatile loads adds e8609768fbb c++: Elide calls to NOP module initializers
No new revisions were added by this update.
Summary of changes: gcc/config/riscv/bitmanip.md | 44 +++++++++++++++++++ gcc/config/riscv/predicates.md | 11 +++++ gcc/cp/cp-tree.h | 2 +- gcc/cp/decl2.cc | 10 +++-- gcc/cp/module.cc | 49 +++++++++++++--------- gcc/ipa-prop.cc | 4 ++ gcc/match.pd | 17 ++++++-- gcc/testsuite/g++.dg/modules/init-2_a.C | 9 +++- gcc/testsuite/g++.dg/modules/init-2_c.C | 11 +++-- .../g++.dg/modules/{init-2_c.C => init-2_d.C} | 3 ++ gcc/testsuite/g++.dg/warn/Wuse-after-free5.C | 15 +++++++ gcc/testsuite/gcc.dg/ipa/pr105739.c | 30 +++++++++++++ gcc/testsuite/gcc.target/i386/pr105965.c | 12 ++++++ gcc/testsuite/gcc.target/riscv/zba-shadd.c | 13 ++++++ gcc/tree-ssa-uninit.cc | 3 ++ gcc/warning-control.cc | 8 +++- 16 files changed, 203 insertions(+), 38 deletions(-) copy gcc/testsuite/g++.dg/modules/{init-2_c.C => init-2_d.C} (67%) create mode 100644 gcc/testsuite/g++.dg/warn/Wuse-after-free5.C create mode 100644 gcc/testsuite/gcc.dg/ipa/pr105739.c create mode 100644 gcc/testsuite/gcc.target/i386/pr105965.c create mode 100644 gcc/testsuite/gcc.target/riscv/zba-shadd.c