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from b243ad1afb7 aarch64: correctly handle zero-sized bit-fields in AAPCS64 [...] new 9f9ccc4a578 Allow vsx_extract_<mode> to use Altivec registers.
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Summary of changes: gcc/config/rs6000/vsx.md | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-)