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from 63623d97024 [mips] Remove codegen support from some 16 bit instructions new 148bc17b95d [PowerPC] Fix transform in table gen file causing UB new 7267bdf4929 [X86][SSE] Allow float domain crossing if we are merging 2 [...]
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Summary of changes: lib/Target/PowerPC/PPCInstrInfo.td | 2 +- lib/Target/X86/X86ISelLowering.cpp | 1 + .../CodeGen/X86/clear_upper_vector_element_bits.ll | 2 +- test/CodeGen/X86/combine-sra.ll | 4 +-- test/CodeGen/X86/oddshuffles.ll | 37 ++++++++++------------ test/CodeGen/X86/pmul.ll | 8 ++--- test/CodeGen/X86/vector-trunc.ll | 18 +++-------- 7 files changed, 28 insertions(+), 44 deletions(-)