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from 6a74133 Updating branches/google/stable to r288672 adds da70d5a [x86] fold fand (fxor X, -1) Y --> fandn X, Y adds bb03f57 [TargetLowering] add special-case for demanded bits analysis [...] adds 79adb74 [CMake] Fix symlink refactor for multi-configuration generators adds 460dd60 [DIExpression] Introduce a dedicated DW_OP_LLVM_fragment oper [...] adds 0689e74 [AArch64][RegisterBankInfo] Fix typo in the logic used in assert. adds 9478556 TableGen/AsmMatcherEmitter: Bring sorting check back under EX [...] adds 5b9f351 [lit] Support custom parsers in parseIntegratedTestScript adds 350d0da AMDGPU: Refactor exp instructions adds 3acbc32 AMDGPU: Change how exp is printed adds 923a400 AMDGPU: Assembler support for exp adds 8bb9ea4 [X86] Fix non-intrinsic roundss/roundsd to not read the desti [...] adds 99ca522 [LAA] Prevent invalid IR for loop-invariant bound in loop body adds 14a3520 GlobalISel: handle 1-element aggregates during ABI lowering. adds bcadc27 GlobalISel: improve translation fallback for constants. adds ad46a07 GlobalISel: make G_CONSTANT take a ConstantInt rather than int64_t. adds e1db4f7 GlobalISel: translate constants larger than 64 bits. adds cfa4450 [IR] Fix some Clang-tidy modernize-use-equals-delete and Incl [...] adds b51e031 AMDGPU: Minor assembler refactoring adds 75dfa0e GlobalISel: handle pointer arguments that get assigned to the stack. adds 792cdf8 AMDGPU: Consolidate inline immediate predicate functions adds 9fef274 GlobalISel: place constants correctly in the entry block. adds 9398e86 [pdb] handle missing pdb streams more gracefully adds fb77f46 [TableGen] Centralize/Unify error handling. adds 8ea5797 [SCCP] Remove manual folding of terminator instructions. adds 416ccca GlobalISel: avoid looking too closely at PHIs when we bail. adds fe3cc4d [libFuzzer] refactor the code to allow collecting features in [...] adds 943496f Summary: Currently there is no way to disable deprecated warn [...] adds db18d34 revert inadvertedly introduced build break adds a079dfc AMDGPU: Don't required structured CFG adds 1e11739 Introduces cmake option `LLVM_DISABLE_ABI_BREAKING_CHECKS_ENFORCING` adds 1af757c Refactor TargetParserTests. adds 4b6e5ec Revert "[SCCP] Remove manual folding of terminator instructions." adds d37747e [LVI] Remove duplicate code using existing helper function adds 9196899 [llvm] Fix D26214: Move error handling out of MC and to the callers. adds 36c7a94 [LVI] Hide a confusing internal interface adds ab3b56e [LVI] Hide the last markX function on LVILatticeVal adds 19937b0 [LVI] Extract a helper function adds 7c651d6 [LVI] Remove dead code in mergeIn adds dfe568d [CMake] Cleanup TableGen include flags adds 25dd36e [X86] Remove scalar logical op alias instructions. Just use C [...] adds 4a6766e [ObjectYAML] First bit of support for encoding DWARF in MachO adds 64ddc83 [X86] Correct pattern for VSQRTSSr_Int, VSQRTSDr_Int, VRCPSSr [...] adds de4f9d5 [X86] Add test case that shows a scalar sqrtsd intrinsic of a [...] adds c7da972 [X86] Remove bad pattern that caused 128-bit loads being used [...] adds 0659581 [X86] Regenerate a test using update_llc_test_checks.py adds 10b8bf3 [X86] Add test case demonstrating a case where a vector sqrt [...] adds 8368f75 [X86] Remove another weird scalar sqrt/rcp/rsqrt pattern. adds ff117bc [PM] Basic cleanups to CGSCC update code, NFC. adds ec5ae20 Add missing parens in assert. adds c153f03 [framelowering] Improve tracking of first CS pop instruction. adds 04d6448 [LCG] Add some much needed asserts and verify runs to uncover [...] adds 7b48d47 Fix MSVC bool to uint64_t promotion warning adds 975669a Fix MSVC -Wmicrosoft-enum-value 'enumerator value is not repr [...] adds a0010d9 [globalisel][aarch64] Prefix PartialMappingIdx enumerators wi [...] adds 3d641da [PowerPC] Improvements for BUILD_VECTOR Vol. 4 adds 01544ba [X86] Add tests to show missed opportunities to calculate kno [...] adds c700b40 [X86][AVX512] Detect repeated constant patterns in BUILD_VECT [...] adds 91bc1bb [ARM] Better error message for invalid flag-preserving Thumb1 insts adds 8c88727 [SLPVectorizer][X86] Tests to show missed buildvector sitofp/ [...] adds 10ef691 [globalisel][aarch64] Correct argument names in comments. adds 462ab86 [globalisel][aarch64] Replace magic numbers with correspondin [...] adds cef5592 [globalisel][aarch64] Fix unintended assumptions about Partia [...] adds 44a9007 Avoid repeated calls to Op.getOpcode(). NFCI. adds 42fe8f5 [X86] Improve UMAX/UMIN knownbits test adds e513e25 [Support/ELF] - Add OpenBSD PT_OPENBSD_BOOTDATA constant. adds 614f299 Removed trailing whitespaces. NFC. adds 06ec4e5 [X86][SSE] Added vector sext_in_reg combine tests adds 057100d [X86][SSE] Add knownbits test demonstrating demandedelts not [...] adds 461b461 [CMake] Fixing clang standalone build adds b1960d4 [InstSimplify] add tests for or-of-icmps; NFC adds 1f9118e [llvm-readobj] - Teach readobj to print PT_OPENBSD_BOOTDATA header adds b4824c6 [InstSimplify] add folds for or-of-icmps with same operands adds a5cd8a6 GlobalISel: stop the legalizer from trying to handle oddly-si [...] adds 22c48aa GlobalISel: allow G_SELECT instructions for pointers. adds 3a783f8 GlobalISel: handle G_SEQUENCE fallbacks gracefully. adds feccc03 [InstSimplify] add tests for and-of-icmps; NFC adds 3074f79 [SelectionDAG] We can ignore knownbits from an undef shuffle [...] adds 9c3d059 GlobalISel: fall back gracefully when we hit unhandled legali [...] adds 02d8347 [InstSimplify] add folds for and-of-icmps with same operands adds 6e9255f [DAGCombine] Add (sext_in_reg (zext x)) -> (sext x) combine adds 42694a3a [X86] Prefer reduced width multiplication over pmulld on Silvermont adds 2c23a5b GlobalISel: correctly handle small args via memory. adds 4fae32e AMDGPU/SI: Don't move copies of immediates to the VALU adds 7f581f5 [BDCE/DebugInfo] Preserve llvm.dbg.value's argument. adds 2fff37f AMDGPU/SI: Set correct value for amd_kernel_code_t::kernarg_s [...] adds e0732bd [IR] Fix some Clang-tidy modernize-use-equals-delete and Incl [...] adds 43179a0 [InstSimplify] fixed (?) to not mutate icmps adds 6b92e1a AMDGPU: Fix operand name for v_interp_* adds 0e51e5e [CodeGen] Fix result type for SMULO/UMULO legalization adds 8dc8a8b [X86][XOP] Add test case for PR31296 adds 0bf16a5 LowerTypeTests: Improve performance by optimising type metada [...] adds 9bdddba AMDGPU: Fix crash on i16 constant expression adds 1e15122 [llc] Fix -stop-after=consthoist initializing the pass. adds 89ce124 AMDGPU: Add llvm.amdgcn.interp.mov intrinsic adds 2af93f1 IR: Reduce the amount of boilerplate required for a metadata [...] adds 4825f8a [LVI] Simplify obfuscated code adds 7e3547c [LVI] Simplify mergeIn code adds d0422a4 [LVI] Remove used return value from markX functions adds 742805e [LCG] Add basic verification of the parent set and fix bugs i [...] adds d55bd2e [AArch64] Correct the check of signed 9-bit imm in isLegalAdd [...] adds c53f76c AMDGPU : Add S_SETREG instructions to fix fdiv precision issues. adds 99d6e95 LowerTypeTests: Add a test that covers "unsatisfiable" type m [...] adds 315dd32 Fix a warning introduced in r288874 adds 59d0d38 Reintroduce a check accidentally removed in 288873 to fix clang bots adds 9a9268b [PM] Add some more logging to make it more clear when the CGS [...] adds 0736f44 [InlineFunction] Do not propagate the callsite debug location [...] adds 0007d14 [AVR] Allow loading from stack slots where src and dest regis [...] adds 714162b [X86][XOP] Fix VPERMIL2 non-constant pool shuffle decoding (PR31296) adds f7450dd [AVR] Move a pseudo expansion test into a folder adds 17b733b [mips][rtdyld] Merge code to write relocated values to the se [...] adds dbcb7ad [InlineFunction] Refactor code in function `fixupLineNumbers' [...] adds d2a4d81 [X86][SSE] Consistently set MOVD/MOVQ load/store/move instruc [...] adds 4632c8a When GVN removes a redundant load, it should not modify the d [...] adds fe16faa [LowerTypeTests] Use the TrailingObjects infrastructure for t [...] adds 038449d [AVR] Expand 'SELECT_CC' nodes whereever possible adds 03f6191 [X86][SSE] Regenerate test. adds 1517e2e Try unbreaking the MSVC build. adds b6b20e1 [LV] Scalarize operands of predicated instructions adds c57b7e5 [X86][SSE] Force execution domain of 32-bit extractps/pextrd [...] adds 5ab68dc [X86][SSE] Fix vpextrd/vpextrq checks adds b23f6fe [X86] Add test to show missed opportunities to calculate know [...] adds 9b37990 [SelectionDAG] Removed old knownbits TODO comment. NFCI. new 5e6a492 Updating branches/google/stable to r288914
The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.
Summary of changes: CMakeLists.txt | 3 + cmake/modules/AddLLVM.cmake | 26 +- cmake/modules/TableGen.cmake | 18 +- include/llvm/Analysis/CGSCCPassManager.h | 16 +- include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h | 15 +- include/llvm/Config/abi-breaking.h.cmake | 7 + include/llvm/DebugInfo/PDB/Raw/PDBFile.h | 16 +- include/llvm/IR/BasicBlock.h | 32 +- include/llvm/IR/Comdat.h | 8 +- include/llvm/IR/DIBuilder.h | 32 +- include/llvm/IR/DebugInfoMetadata.h | 10 +- include/llvm/IR/DerivedTypes.h | 43 +- include/llvm/IR/GetElementPtrTypeIterator.h | 2 +- include/llvm/IR/GlobalAlias.h | 10 +- include/llvm/IR/GlobalIFunc.h | 10 +- include/llvm/IR/GlobalIndirectSymbol.h | 15 +- include/llvm/IR/GlobalObject.h | 15 +- include/llvm/IR/GlobalValue.h | 21 +- include/llvm/IR/GlobalVariable.h | 26 +- include/llvm/IR/IRBuilder.h | 41 +- include/llvm/IR/InlineAsm.h | 17 +- include/llvm/IR/Instruction.h | 33 +- include/llvm/IR/Instructions.h | 374 +- include/llvm/IR/IntrinsicInst.h | 29 +- include/llvm/IR/IntrinsicsAMDGPU.td | 8 + include/llvm/IR/LLVMContext.h | 37 +- include/llvm/IR/Operator.h | 53 +- include/llvm/IR/Statepoint.h | 21 +- include/llvm/IR/Use.h | 14 +- include/llvm/IR/ValueMap.h | 37 +- include/llvm/MC/MCContext.h | 2 +- include/llvm/MC/MCTargetOptions.h | 2 + include/llvm/MC/MCTargetOptionsCommandFlags.h | 4 + include/llvm/ObjectYAML/MachOYAML.h | 11 + include/llvm/Support/CommandLine.h | 1 - include/llvm/Support/Dwarf.h | 3 +- include/llvm/Support/ELF.h | 1 + include/llvm/Transforms/Utils/FunctionComparator.h | 43 +- lib/Analysis/CGSCCPassManager.cpp | 77 +- lib/Analysis/InstructionSimplify.cpp | 63 +- lib/Analysis/LazyCallGraph.cpp | 43 +- lib/Analysis/LazyValueInfo.cpp | 260 +- lib/Analysis/LoopAccessAnalysis.cpp | 20 +- lib/Bitcode/Reader/BitcodeReader.cpp | 9 +- lib/Bitcode/Writer/BitcodeWriter.cpp | 3 +- lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 8 +- lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp | 4 +- lib/CodeGen/AsmPrinter/CodeViewDebug.cpp | 9 +- lib/CodeGen/AsmPrinter/DebugHandlerBase.cpp | 33 +- lib/CodeGen/AsmPrinter/DebugHandlerBase.h | 12 +- lib/CodeGen/AsmPrinter/DebugLocEntry.h | 10 +- lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp | 2 +- lib/CodeGen/AsmPrinter/DwarfDebug.cpp | 78 +- lib/CodeGen/AsmPrinter/DwarfDebug.h | 2 +- lib/CodeGen/AsmPrinter/DwarfExpression.cpp | 58 +- lib/CodeGen/AsmPrinter/DwarfExpression.h | 51 +- lib/CodeGen/AsmPrinter/DwarfUnit.cpp | 11 +- lib/CodeGen/AsmPrinter/DwarfUnit.h | 10 +- lib/CodeGen/GlobalISel/CallLowering.cpp | 5 +- lib/CodeGen/GlobalISel/IRTranslator.cpp | 30 +- lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 2 +- lib/CodeGen/GlobalISel/LegalizerInfo.cpp | 9 +- lib/CodeGen/GlobalISel/MachineIRBuilder.cpp | 31 +- lib/CodeGen/GlobalISel/RegBankSelect.cpp | 3 + lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 9 + lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 9 + lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 16 +- lib/CodeGen/SelectionDAG/TargetLowering.cpp | 24 +- lib/DebugInfo/MSF/MappedBlockStream.cpp | 2 + lib/DebugInfo/PDB/Raw/PDBFile.cpp | 103 +- lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp | 231 +- lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.h | 6 +- lib/Fuzzer/FuzzerLoop.cpp | 6 +- lib/Fuzzer/FuzzerTracePC.cpp | 35 - lib/Fuzzer/FuzzerTracePC.h | 38 +- lib/IR/DIBuilder.cpp | 4 +- lib/IR/DebugInfoMetadata.cpp | 18 +- lib/IR/LLVMContext.cpp | 136 +- lib/IR/Verifier.cpp | 18 +- lib/MC/MCContext.cpp | 19 +- lib/MC/MCTargetOptions.cpp | 3 +- lib/ObjectYAML/MachOYAML.cpp | 17 +- lib/Support/Dwarf.cpp | 3 + lib/TableGen/Main.cpp | 44 +- lib/Target/AArch64/AArch64CallLowering.cpp | 6 +- lib/Target/AArch64/AArch64GenRegisterBankInfo.def | 117 +- lib/Target/AArch64/AArch64ISelLowering.cpp | 2 +- lib/Target/AArch64/AArch64InstructionSelector.cpp | 3 + lib/Target/AArch64/AArch64RegisterBankInfo.cpp | 134 +- lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp | 5 + lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp | 5 +- lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 38 + lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 5 + lib/Target/AMDGPU/AMDGPUISelLowering.h | 8 +- lib/Target/AMDGPU/AMDGPUInstrInfo.td | 39 + lib/Target/AMDGPU/AMDGPUMachineFunction.h | 4 + lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 5 +- lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 336 +- .../AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp | 80 +- lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.h | 25 +- lib/Target/AMDGPU/R600ISelLowering.cpp | 6 +- lib/Target/AMDGPU/R600Instructions.td | 7 +- lib/Target/AMDGPU/SIDefines.h | 21 +- lib/Target/AMDGPU/SIFixSGPRCopies.cpp | 44 +- lib/Target/AMDGPU/SIFoldOperands.cpp | 7 + lib/Target/AMDGPU/SIISelLowering.cpp | 141 +- lib/Target/AMDGPU/SIInsertSkips.cpp | 11 +- lib/Target/AMDGPU/SIInsertWaits.cpp | 10 +- lib/Target/AMDGPU/SIInstrFormats.td | 31 +- lib/Target/AMDGPU/SIInstrInfo.cpp | 63 +- lib/Target/AMDGPU/SIInstrInfo.h | 8 + lib/Target/AMDGPU/SIInstrInfo.td | 102 +- lib/Target/AMDGPU/SIInstructions.td | 42 +- lib/Target/AMDGPU/SIIntrinsics.td | 15 +- lib/Target/AMDGPU/SOPInstructions.td | 6 +- lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 50 +- lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 8 +- lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 5 +- lib/Target/AVR/AVR.h | 2 + lib/Target/AVR/AVRExpandPseudoInsts.cpp | 47 +- lib/Target/AVR/AVRISelLowering.cpp | 4 +- lib/Target/AVR/AVRInstrInfo.td | 4 +- lib/Target/AVR/AVRTargetMachine.cpp | 3 + lib/Target/CMakeLists.txt | 2 + lib/Target/PowerPC/PPCInstrVSX.td | 34 +- lib/Target/PowerPC/PPCMIPeephole.cpp | 119 +- lib/Target/X86/Utils/X86ShuffleDecode.cpp | 14 +- lib/Target/X86/X86.td | 3 + lib/Target/X86/X86FastISel.cpp | 16 +- lib/Target/X86/X86FrameLowering.cpp | 13 +- lib/Target/X86/X86ISelLowering.cpp | 163 +- lib/Target/X86/X86InstrAVX512.td | 130 +- lib/Target/X86/X86InstrFragmentsSIMD.td | 9 - lib/Target/X86/X86InstrInfo.cpp | 12 +- lib/Target/X86/X86InstrSSE.td | 309 +- lib/Target/X86/X86Subtarget.cpp | 4 + lib/Target/X86/X86Subtarget.h | 5 + lib/Transforms/IPO/LowerTypeTests.cpp | 221 +- lib/Transforms/Scalar/BDCE.cpp | 5 + lib/Transforms/Scalar/GVN.cpp | 5 +- lib/Transforms/Scalar/SROA.cpp | 42 +- lib/Transforms/Utils/InlineFunction.cpp | 43 +- lib/Transforms/Utils/Local.cpp | 18 +- lib/Transforms/Vectorize/LoopVectorize.cpp | 217 +- test/Analysis/CostModel/AArch64/gep.ll | 98 +- test/Assembler/diexpression.ll | 8 +- test/Bitcode/DIExpression-4.0.ll | 20 + test/Bitcode/DIExpression-4.0.ll.bc | Bin 0 -> 980 bytes .../AArch64/GlobalISel/arm64-callingconv.ll | 7 + test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll | 68 +- .../AArch64/GlobalISel/arm64-instructionselect.mir | 6 +- .../AArch64/GlobalISel/arm64-irtranslator.ll | 60 +- .../AArch64/GlobalISel/call-translator-ios.ll | 8 +- test/CodeGen/AArch64/GlobalISel/call-translator.ll | 36 +- .../AArch64/GlobalISel/irtranslator-exceptions.ll | 2 +- test/CodeGen/AArch64/GlobalISel/legalize-add.mir | 2 +- .../AArch64/GlobalISel/legalize-constant.mir | 24 +- test/CodeGen/AArch64/GlobalISel/translate-gep.ll | 14 +- .../AMDGPU/amdgpu-codegenprepare-i16-to-i32.ll | 28 + test/CodeGen/AMDGPU/basic-branch.ll | 11 +- test/CodeGen/AMDGPU/br_cc.f16.ll | 25 +- test/CodeGen/AMDGPU/branch-relaxation.ll | 8 +- test/CodeGen/AMDGPU/fdiv.ll | 139 +- test/CodeGen/AMDGPU/indirect-addressing-si.ll | 6 + test/CodeGen/AMDGPU/kernel-args.ll | 28 + test/CodeGen/AMDGPU/lds-m0-init-in-loop.ll | 5 +- test/CodeGen/AMDGPU/llvm.SI.export.ll | 237 + test/CodeGen/AMDGPU/llvm.amdgcn.interp.ll | 6 +- test/CodeGen/AMDGPU/ret.ll | 13 +- test/CodeGen/AMDGPU/salu-to-valu.ll | 25 + test/CodeGen/AMDGPU/sgpr-control-flow.ll | 47 +- test/CodeGen/AMDGPU/sgpr-copy.ll | 31 +- test/CodeGen/AMDGPU/skip-if-dead.ll | 10 +- test/CodeGen/AMDGPU/uniform-cfg.ll | 10 +- test/CodeGen/ARM/deprecated-asm.s | 43 + test/CodeGen/AVR/error-srcreg-destreg-same.ll | 56 - test/CodeGen/AVR/expand-integer-failure.ll | 2 - .../AVR/pseudo/expand-lddw-dst-src-same.mir | 33 + test/CodeGen/MIR/AMDGPU/insert-waits-exp.mir | 63 + test/CodeGen/MIR/AMDGPU/movrels-bug.mir | 2 +- test/CodeGen/MSP430/umulo-16.ll | 32 + test/CodeGen/PowerPC/build-vector-tests.ll | 4858 ++++++++++++++++++++ test/CodeGen/PowerPC/power9-moves-and-splats.ll | 8 +- .../PowerPC/vsx-partword-int-loads-and-stores.ll | 32 +- .../2011-12-26-extractelement-duplicate-load.ll | 16 +- test/CodeGen/X86/2012-1-10-buildvector.ll | 2 +- test/CodeGen/X86/avg.ll | 4 +- test/CodeGen/X86/avx-arith.ll | 288 +- test/CodeGen/X86/avx2-vbroadcast.ll | 14 +- test/CodeGen/X86/bit-piece-comment.ll | 2 +- test/CodeGen/X86/broadcast-elm-cross-splat-vec.ll | 1205 +++++ .../CodeGen/X86/clear_upper_vector_element_bits.ll | 2 +- test/CodeGen/X86/combine-sext-in-reg.ll | 46 + test/CodeGen/X86/exedepsfix-broadcast.ll | 12 +- test/CodeGen/X86/extractelement-index.ll | 38 +- test/CodeGen/X86/fp-logic-replace.ll | 9 +- test/CodeGen/X86/fp-logic.ll | 6 +- test/CodeGen/X86/frame-lowering-debug-intrinsic.ll | 41 + test/CodeGen/X86/known-bits-vector.ll | 145 + test/CodeGen/X86/masked_memop.ll | 2 +- test/CodeGen/X86/merge-consecutive-loads-128.ll | 26 +- test/CodeGen/X86/not-and-simplify.ll | 23 +- test/CodeGen/X86/pr31143.ll | 60 + test/CodeGen/X86/pshufb-mask-comments.ll | 2 +- test/CodeGen/X86/scalar-int-to-fp.ll | 2 +- test/CodeGen/X86/slow-pmulld.ll | 71 + test/CodeGen/X86/sqrt-fastmath-mir.ll | 8 +- test/CodeGen/X86/sse2-intrinsics-x86.ll | 27 + test/CodeGen/X86/stack-folding-fp-avx1.ll | 48 +- test/CodeGen/X86/stack-folding-fp-sse42.ll | 10 +- test/CodeGen/X86/stack-folding-int-avx1.ll | 12 +- test/CodeGen/X86/stack-folding-int-sse42.ll | 8 +- test/CodeGen/X86/uint_to_fp-2.ll | 2 +- test/CodeGen/X86/vec_fp_to_int.ll | 4 +- test/CodeGen/X86/vec_ins_extract-1.ll | 4 +- test/CodeGen/X86/vec_shift6.ll | 6 +- test/CodeGen/X86/vector-shuffle-512-v64.ll | 6 +- test/CodeGen/X86/vector-shuffle-combining-xop.ll | 26 + test/DebugInfo/AArch64/frameindices.ll | 8 +- test/DebugInfo/ARM/PR26163.ll | 4 +- test/DebugInfo/ARM/split-complex.ll | 4 +- test/DebugInfo/ARM/sroa-complex.ll | 4 +- test/DebugInfo/COFF/pieces.ll | 26 +- test/DebugInfo/Generic/inline-debug-loc.ll | 47 + test/DebugInfo/Generic/piece-verifier.ll | 6 +- test/DebugInfo/X86/PR26148.ll | 6 +- test/DebugInfo/X86/array2.ll | 2 +- test/DebugInfo/X86/deleted-bit-piece.ll | 2 +- test/DebugInfo/X86/nophysreg.ll | 4 +- test/DebugInfo/X86/pieces-1.ll | 4 +- test/DebugInfo/X86/pieces-2.ll | 2 +- test/DebugInfo/X86/pieces-3.ll | 10 +- test/DebugInfo/X86/pieces-4.ll | 8 +- test/DebugInfo/X86/sroasplit-1.ll | 4 +- test/DebugInfo/X86/sroasplit-2.ll | 6 +- test/DebugInfo/X86/sroasplit-3.ll | 2 +- test/DebugInfo/X86/sroasplit-4.ll | 8 +- test/DebugInfo/X86/sroasplit-5.ll | 10 +- test/DebugInfo/X86/stack-value-piece.ll | 4 +- test/MC/AMDGPU/exp-err.s | 107 + test/MC/AMDGPU/exp.s | 86 + test/MC/ARM/thumb-diagnostics.s | 2 +- test/MC/Disassembler/AMDGPU/missing_op.txt | 2 +- test/Object/Inputs/openbsd-phdrs.elf-x86-64 | Bin 544 -> 600 bytes test/ObjectYAML/MachO/DWARF-debug_str.yaml | 266 ++ test/Transforms/BDCE/pr26587.ll | 46 + test/Transforms/GVN/dbg-redundant-load.ll | 52 + test/Transforms/Inline/alloca-dbgdeclare.ll | 4 +- test/Transforms/InstSimplify/and-icmps-same-ops.ll | 1239 +++++ test/Transforms/InstSimplify/or-icmps-same-ops.ll | 1239 +++++ .../LoopVectorize/AArch64/aarch64-predication.ll | 63 + .../LoopVectorize/AArch64/predication_costs.ll | 148 +- .../LoopVectorize/X86/x86-predication.ll | 60 + test/Transforms/LoopVectorize/if-pred-non-void.ll | 54 + test/Transforms/LoopVectorize/if-pred-stores.ll | 11 +- .../LoopVersioning/loop-invariant-bound.ll | 37 + test/Transforms/LowerTypeTests/unsat.ll | 12 + test/Transforms/SLPVectorizer/X86/fptosi.ll | 50 + test/Transforms/SLPVectorizer/X86/sitofp.ll | 50 + test/Transforms/SROA/dbg-single-piece.ll | 2 +- test/Transforms/Util/split-bit-piece.ll | 2 +- test/tools/llvm-readobj/program-headers.test | 16 +- tools/llc/llc.cpp | 1 + tools/llvm-mc/llvm-mc.cpp | 17 +- tools/llvm-pdbdump/LLVMOutputStyle.cpp | 44 +- tools/llvm-readobj/ELFDumper.cpp | 1 + tools/obj2yaml/CMakeLists.txt | 1 + tools/obj2yaml/macho2yaml.cpp | 19 + tools/yaml2obj/yaml2macho.cpp | 22 +- unittests/IR/MetadataTest.cpp | 15 +- unittests/Support/TargetParserTest.cpp | 844 ++-- utils/TableGen/AsmMatcherEmitter.cpp | 20 +- utils/lit/lit/TestRunner.py | 207 +- .../tests/Inputs/testrunner-custom-parsers/lit.cfg | 14 + .../Inputs/testrunner-custom-parsers/test.txt | 13 + utils/lit/tests/unit/TestRunner.py | 114 + 276 files changed, 15963 insertions(+), 2849 deletions(-) create mode 100644 test/Bitcode/DIExpression-4.0.ll create mode 100644 test/Bitcode/DIExpression-4.0.ll.bc create mode 100644 test/CodeGen/AMDGPU/llvm.SI.export.ll create mode 100644 test/CodeGen/ARM/deprecated-asm.s delete mode 100644 test/CodeGen/AVR/error-srcreg-destreg-same.ll create mode 100644 test/CodeGen/AVR/pseudo/expand-lddw-dst-src-same.mir create mode 100644 test/CodeGen/MIR/AMDGPU/insert-waits-exp.mir create mode 100644 test/CodeGen/MSP430/umulo-16.ll create mode 100644 test/CodeGen/PowerPC/build-vector-tests.ll create mode 100644 test/CodeGen/X86/broadcast-elm-cross-splat-vec.ll create mode 100644 test/CodeGen/X86/combine-sext-in-reg.ll create mode 100644 test/CodeGen/X86/frame-lowering-debug-intrinsic.ll create mode 100644 test/CodeGen/X86/pr31143.ll create mode 100644 test/CodeGen/X86/slow-pmulld.ll create mode 100644 test/DebugInfo/Generic/inline-debug-loc.ll create mode 100644 test/MC/AMDGPU/exp-err.s create mode 100644 test/MC/AMDGPU/exp.s create mode 100644 test/ObjectYAML/MachO/DWARF-debug_str.yaml create mode 100644 test/Transforms/BDCE/pr26587.ll create mode 100644 test/Transforms/GVN/dbg-redundant-load.ll create mode 100644 test/Transforms/InstSimplify/and-icmps-same-ops.ll create mode 100644 test/Transforms/InstSimplify/or-icmps-same-ops.ll create mode 100644 test/Transforms/LoopVectorize/AArch64/aarch64-predication.ll create mode 100644 test/Transforms/LoopVectorize/X86/x86-predication.ll create mode 100644 test/Transforms/LoopVersioning/loop-invariant-bound.ll create mode 100644 test/Transforms/LowerTypeTests/unsat.ll create mode 100644 utils/lit/tests/Inputs/testrunner-custom-parsers/lit.cfg create mode 100644 utils/lit/tests/Inputs/testrunner-custom-parsers/test.txt create mode 100644 utils/lit/tests/unit/TestRunner.py