[Tcwg-commits] [toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-allmodconfig updated (3715c99be9d -> 32c47ebef18)

5 Jan 2021


      This is an automated email from the git hooks/post-receive script.
tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-allmodconfig
in repository toolchain/ci/llvm-project.
from  3715c99be9d [InstSimplify] Fold nnan/ninf violation to poison
      adds  4fc908025fd [NFC][SimplifyCFG] Add a test where we fail to preserve Dom [...]
      adds  70935b9595a [NFC][SimplifyCFG] SimplifyTerminatorOnSelect(): pull out O [...]
      adds  a7684940f0e [SimplifyCFG] SimplifyTerminatorOnSelect(): fix/tune DomTre [...]
      adds  98cd1c33e3c [NFC][SimplifyCFG] Hoist 'original' DomTree verification fr [...]
      adds  59810c51e76 [clang-tidy] Fix windows tests
      adds  6988f7a6f4a [compiler-rt] [Sanitizers] Extend ThreadDescriptorSize() fo [...]
      adds  6280bc1cc34 [Flang][openmp][5.0] Add task_reduction clause.
      adds  05e6ac4eb81 [IROutliner] Removing a duplicate addition, causing overest [...]
      adds  5c951623bc8 [IROutliner] Refactoring errors in the cost model from past [...]
      adds  f6515b05205 [PowerPC] Do not fold `cmp(d|w)` and `subf` instruction to  [...]
      adds  09b3f3f22cb [benchmark] Fixed a build error when using CMake 3.15.1 + NDK-R20
      adds  94257d12cb2 [RISCV] Remove unused method isUImm5NonZero() from RISCVAsm [...]
      adds  a65092040ad [SVE] Fix inline assembly parsing crash
      adds  74e7cb26b9a [VE] Remove VA.needsCustom checks
      adds  e43b3d1f5e0 Revert "[Sema] Fix deleted function problem in implicitly m [...]
      adds  e0905553b42 [ArgPromotion] Delay dead GEP removal until doPromotion.
      adds  685c8b537af [AARCH64] Improve accumulator forwarding for Cortex-A57 model
      adds  c287f90ccd3 [VE] Change default CPU name to "generic"
      adds  6c89f6fae49 [AArch64] Attempt to fix Mac tests with a more specific tri [...]
      adds  975b64b2937 [docs] Release notes for IsDecl in DIModule.
      adds  42652c1d6e2 [Sparc] Fixes for the internal assembler
      adds  901cc9b6f30 [ARM] Extend lowering for i64 reductions
      adds  23b41986527 [Support] Add KnownBits::icmp helpers.
      adds  d38a0258a5f [AArch64] Add patterns for FMCLA*_indexed.
      adds  060cfd97954 [AArch64][SVE]Add cost model for masked gather and scatter  [...]
      adds  4d7cb6da9fc [Sparc] SparcMCExpr::printVariantKind - fix Wcovered-switch [...]
      adds  82a29a62aba [OpenMP] Add definition/interface for target memory routines
      adds  9f8c0d15c7f DeclCXX - Fix getAs<> null-dereference static analyzer warn [...]
      adds  e9f401d8a26 [IR] CallBase::getBundleOpInfoForOperand - ensure Current i [...]
      adds  ed936aad781 [InterleavedAccess] Return correct 'modified' status.
      adds  e2d3d501ef8 [RISCV][NFC] Add additional cmov tests
      adds  c367258b5cc [SimplifyCFG] Enabled hoisting late in LTO pipeline.
      adds  c55b609b777 [Hexagon] Fix bad SDNodeXForm
      adds  76bfbb74d38 [libomptarget][amdgpu] Call into deviceRTL instead of ockl
      adds  f7463ca3cc5 [ProfileData] GCOVFile::readGCNO - silence undefined pointe [...]
      adds  fe5d51a4897 [OpenMP] Add using bit flags to select Libomptarget Information
      adds  dd6bb367d19 [LoopDeletion] Break backedge of loops when known not taken
      adds  7c63aac7bd4 Revert "[LoopDeletion] Break backedge of loops when known n [...]
      adds  d8938c8bb54 CodeGen: Use Register
      adds  6976812129b [InstCombine] add tests for ashr+icmp; NFC
      adds  dc9ac0e8207 [RISCV] Replace i32 with XLenVT in (add AddrFI, simm12) ise [...]
      adds  b8f22f9d300 [NewPM][AMDGPU] Run InternalizePass when -amdgpu-internaliz [...]
      adds  848e8f938fd [llvm] Construct SmallVector with iterator ranges (NFC)
      adds  0edbc90ec56 [DebugInfo] Use llvm::append_range (NFC)
      adds  eb198f4c3ce [llvm] Use llvm::any_of (NFC)
      adds  a5f863e0765 [NewPM][AMDGPU] Port amdgpu-propagate-attributes-early/late
      adds  e1833e7493a [NewPM][AMDGPU] Port amdgpu-unify-metadata
      adds  9a17bff4f71 [LoopNest] Allow empty basic blocks without loops
      adds  4034f9273ed Switching Clang UniqueInternalLinkageNamesPass scheduling t [...]
      adds  4d0aad96e43 [flang][openmp] Make Reduction clause part of OmpClause
      adds  fe597efc30b [RISCV] Remove unused method RISCVInstPrinter::printSImm5Pl [...]
      adds  fd323a897c6 [NewPM][AMDGPU] Port amdgpu-printf-runtime-binding
      adds  4e838ba9ea2 [NewPM][AMDGPU] Port amdgpu-always-inline
      adds  191552344bb [NewPM][AMDGPU] Make amdgpu-aa work with NewPM
      adds  de6d43f16cb Revert "[LoopNest] Allow empty basic blocks without loops"
      adds  92be640bd7d [FPEnv][AMDGPU] Disable FSUB(-0,X)->FNEG(X) DAGCombine when [...]
      adds  58b6c5d932a [LoopUtils] reorder logic for creating reduction; NFC
      adds  97669575241 [LoopUtils] reduce code for creatng reduction; NFC
      adds  aa169033892 [test] Pin backedge-id-bug-xfail.ll to legacy PM
      adds  8e293fe6ad0 [NewPM][AMDGPU] Pass TargetMachine to AMDGPUSimplifyLibCallsPass
      adds  abbef2fd46d [ValueTracking] isGuaranteedNotToBePoison should return tru [...]
      adds  efc82c4ad2b [NFC, Refactor] Modernize StorageClass from Specifiers.h to [...]
      adds  36263a7cccc [LoopUtils] remove redundant opcode parameter; NFC
      adds  2fd11e0b1ef Revert "[NFC, Refactor] Modernize StorageClass from Specifi [...]
      adds  f67d3dbdb93 [clang] - Also look for devtoolset-10
      adds  b4f519bddda [NFCI] DwarfEHPrepare: update DomTree in non-permissive mod [...]
      adds  3fb57222c4c [NFCI] SimplifyCFG: switch to non-permissive DomTree update [...]
      adds  ed9de61cc3e [SimplifyCFGPass] mergeEmptyReturnBlocks(): switch to non-p [...]
      adds  a8604e3d5b7 [SimplifyCFG] simplifyIndirectBr(): switch to non-permissiv [...]
      adds  110b3d7855e [SimplifyCFG] SimplifyEqualityComparisonWithOnlyPredecessor [...]
      adds  32c47ebef18 [SimplifyCFG] SimplifyCondBranchToTwoReturns(): switch to n [...]
No new revisions were added by this update.
Summary of changes:
 .../cppcoreguidelines-macro-usage-custom.cpp       |   7 +-
 ...eadability-identifier-naming-ignored-regexp.cpp |  13 +-
 clang/lib/AST/DeclCXX.cpp                          |   6 +-
 clang/lib/CodeGen/BackendUtil.cpp                  |   6 +-
 clang/lib/CodeGen/CGOpenMPRuntimeAMDGCN.cpp        |   7 +-
 clang/lib/Driver/ToolChains/Gnu.cpp                |   1 +
 clang/lib/Sema/SemaInit.cpp                        |  67 +--
 clang/lib/Sema/SemaStmt.cpp                        |  36 +-
 .../CXX/class/class.init/class.copy.elision/p3.cpp |  50 --
 clang/test/OpenMP/amdgcn_target_codegen.cpp        |  10 +-
 .../sanitizer_common/sanitizer_linux_libcdep.cpp   |   4 +-
 flang/include/flang/Parser/parse-tree.h            |   2 +-
 flang/lib/Parser/openmp-parsers.cpp                |   9 +-
 flang/lib/Parser/unparse.cpp                       |   4 +-
 flang/lib/Semantics/check-omp-structure.cpp        |   3 +-
 flang/lib/Semantics/check-omp-structure.h          |   3 +-
 flang/test/Semantics/omp-clause-validity01.f90     |   6 +-
 llvm/docs/ReleaseNotes.rst                         |   6 +
 llvm/include/llvm/Analysis/IVDescriptors.h         |   9 +-
 llvm/include/llvm/Analysis/TargetTransformInfo.h   |  11 +-
 .../llvm/Analysis/TargetTransformInfoImpl.h        |   5 +-
 llvm/include/llvm/CodeGen/BasicTTIImpl.h           |   6 +-
 llvm/include/llvm/CodeGen/LiveInterval.h           |   7 +-
 llvm/include/llvm/CodeGen/MachineFrameInfo.h       |   7 +-
 llvm/include/llvm/DebugInfo/CodeView/TypeRecord.h  |   2 +-
 llvm/include/llvm/Frontend/OpenMP/OMP.td           |   3 +-
 llvm/include/llvm/IR/DebugInfoMetadata.h           |   5 +-
 llvm/include/llvm/IR/Metadata.h                    |   3 +-
 llvm/include/llvm/IR/PredIteratorCache.h           |   2 +-
 llvm/include/llvm/Support/KnownBits.h              |  31 ++
 llvm/include/llvm/Transforms/Utils/LoopUtils.h     |   3 +-
 llvm/lib/Analysis/IVDescriptors.cpp                |   5 +-
 llvm/lib/Analysis/InstructionSimplify.cpp          |   4 +-
 llvm/lib/Analysis/ScalarEvolution.cpp              |  16 +-
 llvm/lib/Analysis/TargetTransformInfo.cpp          |   4 +
 llvm/lib/Analysis/ValueTracking.cpp                |   2 +-
 llvm/lib/CodeGen/DwarfEHPrepare.cpp                |   2 +-
 llvm/lib/CodeGen/InterleavedAccessPass.cpp         |  25 +-
 llvm/lib/CodeGen/MachineSink.cpp                   |   6 +-
 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp      |  21 +-
 llvm/lib/DebugInfo/DWARF/DWARFDie.cpp              |   3 +-
 llvm/lib/DebugInfo/MSF/MSFBuilder.cpp              |   6 +-
 llvm/lib/DebugInfo/PDB/Native/NamedStreamMap.cpp   |   2 +-
 llvm/lib/DebugInfo/PDB/Native/SymbolCache.cpp      |   3 +-
 llvm/lib/DebugInfo/PDB/Native/TpiStreamBuilder.cpp |   2 +-
 .../ExecutionEngine/Orc/TargetProcessControl.cpp   |   8 +-
 llvm/lib/IR/Constants.cpp                          |   2 +-
 llvm/lib/IR/Instructions.cpp                       |   2 +-
 llvm/lib/IR/Verifier.cpp                           |   4 +-
 llvm/lib/Passes/PassBuilder.cpp                    |  10 +-
 llvm/lib/ProfileData/GCOV.cpp                      |   2 +-
 llvm/lib/Support/KnownBits.cpp                     |  69 +++
 llvm/lib/Support/SourceMgr.cpp                     |   2 +-
 llvm/lib/TableGen/Record.cpp                       |   4 +-
 llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp      |   3 +-
 llvm/lib/Target/AArch64/AArch64InstrInfo.cpp       |   2 +-
 llvm/lib/Target/AArch64/AArch64InstrInfo.td        |  21 +
 llvm/lib/Target/AArch64/AArch64SchedA57.td         |  61 ++-
 llvm/lib/Target/AArch64/AArch64SchedA57WriteRes.td |  19 +
 .../Target/AArch64/AArch64TargetTransformInfo.cpp  |  20 +
 .../Target/AArch64/AArch64TargetTransformInfo.h    |  11 +
 llvm/lib/Target/AMDGPU/AMDGPU.h                    |  40 ++
 llvm/lib/Target/AMDGPU/AMDGPUAliasAnalysis.cpp     |   2 +
 llvm/lib/Target/AMDGPU/AMDGPUAliasAnalysis.h       |   7 +-
 llvm/lib/Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp  |  20 +-
 llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp          |   2 +-
 .../Target/AMDGPU/AMDGPUPrintfRuntimeBinding.cpp   |  77 ++-
 .../Target/AMDGPU/AMDGPUPropagateAttributes.cpp    |  19 +
 llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp     |  70 ++-
 llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h       |   1 +
 llvm/lib/Target/AMDGPU/AMDGPUUnifyMetadata.cpp     |  59 +--
 llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp           |   2 +-
 llvm/lib/Target/ARM/ARMISelLowering.cpp            |  53 +-
 llvm/lib/Target/Hexagon/HexagonPatterns.td         |   2 +-
 llvm/lib/Target/PowerPC/PPCInstrInfo.cpp           |   8 +
 llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp |  12 +-
 .../Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp |   9 -
 .../Target/RISCV/MCTargetDesc/RISCVInstPrinter.h   |   2 -
 llvm/lib/Target/RISCV/RISCVFrameLowering.cpp       |   2 +-
 llvm/lib/Target/RISCV/RISCVInstrInfo.td            |   8 +-
 llvm/lib/Target/RISCV/RISCVInstrInfoV.td           |   1 -
 llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp | 158 +++++-
 .../Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp |  30 +-
 .../Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp      |  52 +-
 llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.cpp |  73 +--
 llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.h   |   1 +
 llvm/lib/Target/Sparc/SparcAsmPrinter.cpp          |   2 +-
 llvm/lib/Target/Sparc/SparcISelLowering.cpp        |   6 +-
 llvm/lib/Target/Sparc/SparcInstr64Bit.td           |   6 +-
 llvm/lib/Target/Sparc/SparcInstrFormats.td         |   4 +-
 llvm/lib/Target/Sparc/SparcInstrInfo.td            |  25 +-
 llvm/lib/Target/VE/MCTargetDesc/VEMCTargetDesc.cpp |   2 +-
 llvm/lib/Target/VE/VE.td                           |   2 +-
 llvm/lib/Target/VE/VEISelLowering.cpp              |  15 +-
 llvm/lib/Target/VE/VESubtarget.cpp                 |   2 +-
 llvm/lib/Transforms/IPO/ArgumentPromotion.cpp      |  18 +-
 llvm/lib/Transforms/IPO/IROutliner.cpp             |   4 +-
 llvm/lib/Transforms/IPO/PassManagerBuilder.cpp     |   6 +-
 llvm/lib/Transforms/Scalar/SimplifyCFGPass.cpp     |   7 +-
 llvm/lib/Transforms/Utils/LoopUtils.cpp            | 112 ++---
 llvm/lib/Transforms/Utils/SimplifyCFG.cpp          | 142 +++---
 llvm/lib/Transforms/Vectorize/LoopVectorize.cpp    |   6 +-
 llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp    |   6 +-
 llvm/lib/Transforms/Vectorize/VPlan.cpp            |   2 +-
 .../AArch64/sve-getIntrinsicInstrCost-gather.ll    |  37 ++
 .../AArch64/sve-getIntrinsicInstrCost-scatter.ll   |  40 ++
 .../AArch64/inline-asm-constraints-bad-sve.ll      |   9 +
 llvm/test/CodeGen/AArch64/neon-vcmla.ll            |  95 ++++
 llvm/test/CodeGen/AMDGPU/amdgpu-alias-analysis.ll  |   2 +
 llvm/test/CodeGen/AMDGPU/clamp-modifier.ll         |   2 +-
 llvm/test/CodeGen/AMDGPU/clamp.ll                  |   4 +-
 llvm/test/CodeGen/AMDGPU/fdiv32-to-rcp-folding.ll  |   8 +-
 llvm/test/CodeGen/AMDGPU/fma-combine.ll            |   4 +-
 llvm/test/CodeGen/AMDGPU/fneg-combines.ll          |  42 +-
 .../force-alwaysinline-lds-global-address.ll       |   2 +
 llvm/test/CodeGen/AMDGPU/fpext-free.ll             |   2 +-
 llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll            |   4 +-
 llvm/test/CodeGen/AMDGPU/internalize.ll            |   4 +-
 llvm/test/CodeGen/AMDGPU/known-never-snan.ll       |   2 +-
 llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmad.ftz.ll   |   4 +-
 .../CodeGen/AMDGPU/llvm.amdgcn.wavefrontsize.ll    |   1 +
 llvm/test/CodeGen/AMDGPU/mad-combine.ll            |   6 +-
 llvm/test/CodeGen/AMDGPU/mad-mix.ll                |   8 +-
 llvm/test/CodeGen/AMDGPU/opencl-printf.ll          |   1 +
 .../CodeGen/AMDGPU/propagate-attributes-clone.ll   |   2 +
 .../propagate-attributes-flat-work-group-size.ll   |   1 +
 .../AMDGPU/propagate-attributes-single-set.ll      |   1 +
 llvm/test/CodeGen/AMDGPU/rcp-pattern.ll            |   4 +-
 llvm/test/CodeGen/AMDGPU/rsq.ll                    |   2 +-
 llvm/test/CodeGen/AMDGPU/unify-metadata.ll         |   1 +
 llvm/test/CodeGen/AMDGPU/v_mac.ll                  |   6 +-
 llvm/test/CodeGen/AMDGPU/v_mac_f16.ll              |  12 +-
 .../CodeGen/Hexagon/isel-splat-vector-neg-i8.ll    |  16 +
 llvm/test/CodeGen/PowerPC/pr47830.ll               |   5 +-
 llvm/test/CodeGen/RISCV/rv32Zbt.ll                 | 560 +++++++++++++++++----
 llvm/test/CodeGen/RISCV/rv64Zbt.ll                 | 260 +++++++++-
 llvm/test/CodeGen/RISCV/vararg.ll                  |  48 +-
 llvm/test/CodeGen/Thumb2/mve-vecreduce-add.ll      | 122 +----
 llvm/test/CodeGen/Thumb2/mve-vecreduce-addpred.ll  | 200 +-------
 llvm/test/CodeGen/Thumb2/mve-vecreduce-mla.ll      | 298 +----------
 llvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll  | 534 ++------------------
 llvm/test/CodeGen/VE/Scalar/cpu.ll                 |   5 +
 llvm/test/MC/Sparc/sparc-asm-errors.s              |   6 +
 llvm/test/MC/Sparc/sparc-ctrl-instructions.s       |   7 +
 llvm/test/MC/Sparc/sparc-relocations.s             |   4 +
 .../ArgumentPromotion/dead-gep-no-promotion.ll     |  30 ++
 llvm/test/Transforms/IROutliner/opt-remarks.ll     | 108 +++-
 llvm/test/Transforms/IROutliner/outlining-calls.ll |   2 +-
 .../outlining-compatible-and-attribute-transfer.ll |   2 +-
 .../outlining-compatible-or-attribute-transfer.ll  |   2 +-
 .../Transforms/IROutliner/outlining-cost-model.ll  |   8 +
 .../IROutliner/outlining-different-constants.ll    |   2 +-
 .../IROutliner/outlining-different-structure.ll    |   2 +-
 .../IROutliner/outlining-isomorphic-predicates.ll  |   2 +-
 llvm/test/Transforms/InstCombine/icmp-shr.ll       | 419 +++++++++++++--
 .../X86/interleave-load-extract-shuffle-changes.ll |  58 +++
 ...inatorOnSelect-domtree-preservation-edgecase.ll |  58 +++
 .../StructurizeCFG/AMDGPU/backedge-id-bug-xfail.ll |   2 +-
 .../tools/llvm-mca/AArch64/Cortex/forwarding-A57.s | 501 ++++++++++++++++++
 llvm/tools/llvm-readobj/ELFDumper.cpp              |   5 +-
 llvm/tools/opt/opt.cpp                             |  12 +-
 llvm/unittests/Analysis/ValueTrackingTest.cpp      |   4 +
 llvm/unittests/Support/KnownBitsTest.cpp           |  87 ++++
 llvm/utils/TableGen/AsmMatcherEmitter.cpp          |   5 +-
 llvm/utils/TableGen/GICombinerEmitter.cpp          |   8 +-
 llvm/utils/benchmark/include/benchmark/benchmark.h |   2 +-
 .../deviceRTLs/amdgcn/src/amdgcn_interface.h       |   2 +
 .../deviceRTLs/amdgcn/src/target_impl.hip          |   6 +-
 openmp/libomptarget/include/Debug.h                |  44 +-
 openmp/libomptarget/include/SourceInfo.h           |   9 +-
 openmp/libomptarget/plugins/cuda/src/rtl.cpp       |  28 +-
 openmp/libomptarget/src/device.cpp                 |  23 +-
 openmp/libomptarget/src/interface.cpp              |  42 +-
 openmp/libomptarget/src/private.h                  |  63 ++-
 openmp/libomptarget/test/offloading/info.c         |  35 +-
 openmp/runtime/src/include/omp.h.var               |  18 +
 openmp/runtime/src/include/omp_lib.f90.var         |  97 ++++
 openmp/runtime/src/include/omp_lib.h.var           | 107 ++++
 178 files changed, 3870 insertions(+), 2046 deletions(-)
 delete mode 100644 clang/test/CXX/class/class.init/class.copy.elision/p3.cpp
 create mode 100644 llvm/test/Analysis/CostModel/AArch64/sve-getIntrinsicInstrCost- [...]
 create mode 100644 llvm/test/Analysis/CostModel/AArch64/sve-getIntrinsicInstrCost- [...]
 create mode 100644 llvm/test/CodeGen/Hexagon/isel-splat-vector-neg-i8.ll
 create mode 100644 llvm/test/CodeGen/VE/Scalar/cpu.ll
 create mode 100644 llvm/test/Transforms/ArgumentPromotion/dead-gep-no-promotion.ll
 create mode 100644 llvm/test/Transforms/InterleavedAccess/X86/interleave-load-extr [...]
 create mode 100644 llvm/test/Transforms/SimplifyCFG/SimplifyTerminatorOnSelect-dom [...]
 create mode 100644 llvm/test/tools/llvm-mca/AArch64/Cortex/forwarding-A57.s
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[Tcwg-commits] [toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-allmodconfig updated (3715c99be9d -> 32c47ebef18)